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gerrit-public.fairphone.software / toolchain / llvm-project / a0a1164ce41b5fbb68d86759e96b51e8a2529ece / . / llvm / test / CodeGen / SystemZ / cond-move-03.ll
blob: a9bf1c803109bbf14293cb90e6ccab6e3ad47c16 [file] [log] [blame]
Ulrich Weigand524f2762016-11-28 13:34:08 +0000[diff] [blame]1; Test LOCFHR and LOCHHI.
2; See comments in asm-18.ll about testing high-word operations.
3;
4; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -mcpu=z13 \
5; RUN: -no-integrated-as | FileCheck %s
6
7define void @f1(i32 %limit) {
8; CHECK-LABEL: f1:
9; CHECK-DAG: stepa [[REG1:%r[0-5]]]
10; CHECK-DAG: stepb [[REG2:%r[0-5]]]
11; CHECK-DAG: clfi %r2, 42
12; CHECK: locfhrl [[REG2]], [[REG1]]
13; CHECK: stepc [[REG2]]
14; CHECK: br %r14
15 %a = call i32 asm sideeffect "stepa $0", "=h"()
16 %b = call i32 asm sideeffect "stepb $0", "=h"()
17 %cond = icmp ult i32 %limit, 42
18 %res = select i1 %cond, i32 %a, i32 %b
19 call void asm sideeffect "stepc $0", "h"(i32 %res)
20 ret void
21}
22
23; FIXME: We should commute the LOCRMux to save one move.
24define void @f2(i32 %limit) {
25; CHECK-LABEL: f2:
26; CHECK-DAG: stepa [[REG1:%r[0-5]]]
27; CHECK-DAG: stepb [[REG2:%r[0-5]]]
28; CHECK-DAG: clijhe %r2, 42,
29; CHECK: risblg [[REG2]], [[REG1]], 0, 159, 32
30; CHECK: risbhg [[REG1]], [[REG2]], 0, 159, 32
31; CHECK: stepc [[REG1]]
32; CHECK: br %r14
33 %dummy = call i32 asm sideeffect "dummy $0", "=h"()
34 %a = call i32 asm sideeffect "stepa $0", "=h"()
35 %b = call i32 asm sideeffect "stepb $0", "=r"()
36 %cond = icmp ult i32 %limit, 42
37 %res = select i1 %cond, i32 %a, i32 %b
38 call void asm sideeffect "stepc $0", "h"(i32 %res)
39 call void asm sideeffect "dummy $0", "h"(i32 %dummy)
40 ret void
41}
42
43define void @f3(i32 %limit) {
44; CHECK-LABEL: f3:
45; CHECK-DAG: stepa [[REG2:%r[0-5]]]
46; CHECK-DAG: stepb [[REG1:%r[0-5]]]
47; CHECK-DAG: clijhe %r2, 42,
48; CHECK: risbhg [[REG1]], [[REG2]], 0, 159, 32
49; CHECK: stepc [[REG1]]
50; CHECK: br %r14
51 %dummy = call i32 asm sideeffect "dummy $0", "=h"()
52 %a = call i32 asm sideeffect "stepa $0", "=r"()
53 %b = call i32 asm sideeffect "stepb $0", "=h"()
54 %cond = icmp ult i32 %limit, 42
55 %res = select i1 %cond, i32 %a, i32 %b
56 call void asm sideeffect "stepc $0", "h"(i32 %res)
57 call void asm sideeffect "dummy $0", "h"(i32 %dummy)
58 ret void
59}
60
61; FIXME: We should commute the LOCRMux to save one move.
62define void @f4(i32 %limit) {
63; CHECK-LABEL: f4:
64; CHECK-DAG: stepa [[REG1:%r[0-5]]]
65; CHECK-DAG: stepb [[REG2:%r[0-5]]]
66; CHECK-DAG: clijhe %r2, 42,
67; CHECK: risbhg [[REG2]], [[REG1]], 0, 159, 32
68; CHECK: risblg [[REG1]], [[REG2]], 0, 159, 32
69; CHECK: stepc [[REG1]]
70; CHECK: br %r14
71 %dummy = call i32 asm sideeffect "dummy $0", "=h"()
72 %a = call i32 asm sideeffect "stepa $0", "=r"()
73 %b = call i32 asm sideeffect "stepb $0", "=h"()
74 %cond = icmp ult i32 %limit, 42
75 %res = select i1 %cond, i32 %a, i32 %b
76 call void asm sideeffect "stepc $0", "r"(i32 %res)
77 call void asm sideeffect "dummy $0", "h"(i32 %dummy)
78 ret void
79}
80
81define void @f5(i32 %limit) {
82; CHECK-LABEL: f5:
83; CHECK-DAG: stepa [[REG2:%r[0-5]]]
84; CHECK-DAG: stepb [[REG1:%r[0-5]]]
85; CHECK-DAG: clijhe %r2, 42,
86; CHECK: risblg [[REG1]], [[REG2]], 0, 159, 32
87; CHECK: stepc [[REG1]]
88; CHECK: br %r14
89 %dummy = call i32 asm sideeffect "dummy $0", "=h"()
90 %a = call i32 asm sideeffect "stepa $0", "=h"()
91 %b = call i32 asm sideeffect "stepb $0", "=r"()
92 %cond = icmp ult i32 %limit, 42
93 %res = select i1 %cond, i32 %a, i32 %b
94 call void asm sideeffect "stepc $0", "r"(i32 %res)
95 call void asm sideeffect "dummy $0", "h"(i32 %dummy)
96 ret void
97}
98
99; Check that we also get LOCFHR as a result of early if-conversion.
100define void @f6(i32 %limit) {
101; CHECK-LABEL: f6:
102; CHECK-DAG: stepa [[REG1:%r[0-5]]]
103; CHECK-DAG: stepb [[REG2:%r[0-5]]]
104; CHECK-DAG: clfi %r2, 41
105; CHECK: locfhrle [[REG2]], [[REG1]]
106; CHECK: stepc [[REG2]]
107; CHECK: br %r14
108entry:
109 %a = call i32 asm sideeffect "stepa $0", "=h"()
110 %b = call i32 asm sideeffect "stepb $0", "=h"()
111 %cond = icmp ult i32 %limit, 42
112 br i1 %cond, label %if.then, label %return
113
114if.then:
115 br label %return
116
117return:
118 %res = phi i32 [ %a, %if.then ], [ %b, %entry ]
119 call void asm sideeffect "stepc $0", "h"(i32 %res)
120 ret void
121}
122
123; Check that inverting the condition works as well.
124define void @f7(i32 %limit) {
125; CHECK-LABEL: f7:
126; CHECK-DAG: stepa [[REG1:%r[0-5]]]
127; CHECK-DAG: stepb [[REG2:%r[0-5]]]
128; CHECK-DAG: clfi %r2, 41
129; CHECK: locfhrh [[REG2]], [[REG1]]
130; CHECK: stepc [[REG2]]
131; CHECK: br %r14
132entry:
133 %a = call i32 asm sideeffect "stepa $0", "=h"()
134 %b = call i32 asm sideeffect "stepb $0", "=h"()
135 %cond = icmp ult i32 %limit, 42
136 br i1 %cond, label %if.then, label %return
137
138if.then:
139 br label %return
140
141return:
142 %res = phi i32 [ %b, %if.then ], [ %a, %entry ]
143 call void asm sideeffect "stepc $0", "h"(i32 %res)
144 ret void
145}
146
147define void @f8(i32 %limit) {
148; CHECK-LABEL: f8:
149; CHECK: clfi %r2, 42
150; CHECK: lochhil [[REG:%r[0-5]]], 32767
151; CHECK: stepa [[REG]]
152; CHECK: br %r14
153 %cond = icmp ult i32 %limit, 42
154 %res = select i1 %cond, i32 32767, i32 0
155 call void asm sideeffect "stepa $0", "h"(i32 %res)
156 ret void
157}
158
159define void @f9(i32 %limit) {
160; CHECK-LABEL: f9:
161; CHECK: clfi %r2, 42
162; CHECK: lochhil [[REG:%r[0-5]]], -32768
163; CHECK: stepa [[REG]]
164; CHECK: br %r14
165 %cond = icmp ult i32 %limit, 42
166 %res = select i1 %cond, i32 -32768, i32 0
167 call void asm sideeffect "stepa $0", "h"(i32 %res)
168 ret void
169}
170
171; Check that we also get LOCHHI as a result of early if-conversion.
172define void @f10(i32 %limit) {
173; CHECK-LABEL: f10:
174; CHECK-DAG: stepa [[REG:%r[0-5]]]
175; CHECK-DAG: clfi %r2, 41
176; CHECK: lochhile [[REG]], 123
177; CHECK: stepb [[REG]]
178; CHECK: br %r14
179entry:
180 %a = call i32 asm sideeffect "stepa $0", "=h"()
181 %cond = icmp ult i32 %limit, 42
182 br i1 %cond, label %if.then, label %return
183
184if.then:
185 br label %return
186
187return:
188 %res = phi i32 [ 123, %if.then ], [ %a, %entry ]
189 call void asm sideeffect "stepb $0", "h"(i32 %res)
190 ret void
191}
192
193; Check that inverting the condition works as well.
194define void @f11(i32 %limit) {
195; CHECK-LABEL: f11:
196; CHECK-DAG: stepa [[REG:%r[0-5]]]
197; CHECK-DAG: clfi %r2, 41
198; CHECK: lochhih [[REG]], 123
199; CHECK: stepb [[REG]]
200; CHECK: br %r14
201entry:
202 %a = call i32 asm sideeffect "stepa $0", "=h"()
203 %cond = icmp ult i32 %limit, 42
204 br i1 %cond, label %if.then, label %return
205
206if.then:
207 br label %return
208
209return:
210 %res = phi i32 [ %a, %if.then ], [ 123, %entry ]
211 call void asm sideeffect "stepb $0", "h"(i32 %res)
212 ret void
213}