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gerrit-public.fairphone.software / toolchain / llvm-project / a1fe17c9adb2b6093f1ce848a48fb8954c27c595 / . / llvm / test / CodeGen / AMDGPU / indirect-private-64.ll
blob: 1f851f9de53558909e6e8b575f6c075e5c07a1c5 [file] [log] [blame]
Matt Arsenaulte8ed8e52016-05-11 00:28:54 +0000[diff] [blame]1; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA16 -check-prefix=SI %s
2; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=SI-ALLOCA4 -check-prefix=SI %s
Matt Arsenaultc5fce692016-04-28 18:38:48 +0000[diff] [blame]3; RUN: llc -march=amdgcn -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=SI-PROMOTE -check-prefix=SI %s
Changpeng Fang71369b32016-05-26 19:35:29 +0000[diff] [blame]4; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca,+max-private-element-size-16 -verify-machineinstrs < %s | FileCheck -check-prefix=CI-ALLOCA16 -check-prefix=SI %s
5; RUN: llc -march=amdgcn -mcpu=tonga -mattr=+promote-alloca -verify-machineinstrs < %s | FileCheck -check-prefix=CI-PROMOTE -check-prefix=SI %s
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]6
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000[diff] [blame]7declare void @llvm.amdgcn.s.barrier() #0
Matt Arsenault6e63dd22014-02-02 00:13:12 +0000[diff] [blame]8
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]9; SI-LABEL: {{^}}private_access_f64_alloca:
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]10
Matt Arsenaulte8ed8e52016-05-11 00:28:54 +0000[diff] [blame]11; SI-ALLOCA16: buffer_store_dwordx2
12; SI-ALLOCA16: buffer_load_dwordx2
13
14; SI-ALLOCA4: buffer_store_dword v
15; SI-ALLOCA4: buffer_store_dword v
16; SI-ALLOCA4: buffer_load_dword v
17; SI-ALLOCA4: buffer_load_dword v
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]18
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]19; SI-PROMOTE: ds_write_b64
20; SI-PROMOTE: ds_read_b64
Changpeng Fang71369b32016-05-26 19:35:29 +0000[diff] [blame]21; CI-PROMOTE: ds_write_b64
22; CI-PROMOTE: ds_read_b64
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]23define void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) #1 {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]24 %val = load double, double addrspace(1)* %in, align 8
Matt Arsenaultc5fce692016-04-28 18:38:48 +0000[diff] [blame]25 %array = alloca [16 x double], align 8
26 %ptr = getelementptr inbounds [16 x double], [16 x double]* %array, i32 0, i32 %b
Matt Arsenault6e63dd22014-02-02 00:13:12 +0000[diff] [blame]27 store double %val, double* %ptr, align 8
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]28 call void @llvm.amdgcn.s.barrier()
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]29 %result = load double, double* %ptr, align 8
Matt Arsenault6e63dd22014-02-02 00:13:12 +0000[diff] [blame]30 store double %result, double addrspace(1)* %out, align 8
31 ret void
32}
33
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]34; SI-LABEL: {{^}}private_access_v2f64_alloca:
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]35
Matt Arsenaulte8ed8e52016-05-11 00:28:54 +0000[diff] [blame]36; SI-ALLOCA16: buffer_store_dwordx4
37; SI-ALLOCA16: buffer_load_dwordx4
38
39; SI-ALLOCA4: buffer_store_dword v
40; SI-ALLOCA4: buffer_store_dword v
41; SI-ALLOCA4: buffer_store_dword v
42; SI-ALLOCA4: buffer_store_dword v
43; SI-ALLOCA4: buffer_load_dword v
44; SI-ALLOCA4: buffer_load_dword v
45; SI-ALLOCA4: buffer_load_dword v
46; SI-ALLOCA4: buffer_load_dword v
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]47
Matt Arsenaultff05da82015-11-24 12:18:54 +0000[diff] [blame]48; SI-PROMOTE: ds_write_b64
49; SI-PROMOTE: ds_write_b64
50; SI-PROMOTE: ds_read_b64
51; SI-PROMOTE: ds_read_b64
Changpeng Fang71369b32016-05-26 19:35:29 +0000[diff] [blame]52; CI-PROMOTE: ds_write2_b64
53; CI-PROMOTE: ds_read2_b64
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]54define void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) #1 {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]55 %val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16
Matt Arsenaultc5fce692016-04-28 18:38:48 +0000[diff] [blame]56 %array = alloca [8 x <2 x double>], align 16
57 %ptr = getelementptr inbounds [8 x <2 x double>], [8 x <2 x double>]* %array, i32 0, i32 %b
Matt Arsenault6e63dd22014-02-02 00:13:12 +0000[diff] [blame]58 store <2 x double> %val, <2 x double>* %ptr, align 16
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]59 call void @llvm.amdgcn.s.barrier()
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]60 %result = load <2 x double>, <2 x double>* %ptr, align 16
Matt Arsenault6e63dd22014-02-02 00:13:12 +0000[diff] [blame]61 store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16
62 ret void
63}
Matt Arsenaultad41d7b2014-03-24 17:50:46 +0000[diff] [blame]64
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]65; SI-LABEL: {{^}}private_access_i64_alloca:
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]66
Matt Arsenaulte8ed8e52016-05-11 00:28:54 +0000[diff] [blame]67; SI-ALLOCA16: buffer_store_dwordx2
68; SI-ALLOCA16: buffer_load_dwordx2
69
70; SI-ALLOCA4: buffer_store_dword v
71; SI-ALLOCA4: buffer_store_dword v
72; SI-ALLOCA4: buffer_load_dword v
73; SI-ALLOCA4: buffer_load_dword v
74
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]75
Tom Stellard326d6ec2014-11-05 14:50:53 +0000[diff] [blame]76; SI-PROMOTE: ds_write_b64
77; SI-PROMOTE: ds_read_b64
Changpeng Fang71369b32016-05-26 19:35:29 +0000[diff] [blame]78; CI-PROMOTE: ds_write_b64
79; CI-PROMOTE: ds_read_b64
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]80define void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) #1 {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]81 %val = load i64, i64 addrspace(1)* %in, align 8
Matt Arsenaultc5fce692016-04-28 18:38:48 +0000[diff] [blame]82 %array = alloca [8 x i64], align 8
83 %ptr = getelementptr inbounds [8 x i64], [8 x i64]* %array, i32 0, i32 %b
Matt Arsenaultad41d7b2014-03-24 17:50:46 +0000[diff] [blame]84 store i64 %val, i64* %ptr, align 8
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]85 call void @llvm.amdgcn.s.barrier()
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]86 %result = load i64, i64* %ptr, align 8
Matt Arsenaultad41d7b2014-03-24 17:50:46 +0000[diff] [blame]87 store i64 %result, i64 addrspace(1)* %out, align 8
88 ret void
89}
90
Tom Stellard79243d92014-10-01 17:15:17 +0000[diff] [blame]91; SI-LABEL: {{^}}private_access_v2i64_alloca:
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]92
Matt Arsenaulte8ed8e52016-05-11 00:28:54 +0000[diff] [blame]93; SI-ALLOCA16: buffer_store_dwordx4
94; SI-ALLOCA16: buffer_load_dwordx4
95
96; SI-ALLOCA4: buffer_store_dword v
97; SI-ALLOCA4: buffer_store_dword v
98; SI-ALLOCA4: buffer_store_dword v
99; SI-ALLOCA4: buffer_store_dword v
100
101; SI-ALLOCA4: buffer_load_dword v
102; SI-ALLOCA4: buffer_load_dword v
103; SI-ALLOCA4: buffer_load_dword v
104; SI-ALLOCA4: buffer_load_dword v
Matt Arsenault7d5e2cb2014-07-13 02:46:17 +0000[diff] [blame]105
Matt Arsenaultff05da82015-11-24 12:18:54 +0000[diff] [blame]106; SI-PROMOTE: ds_write_b64
107; SI-PROMOTE: ds_write_b64
108; SI-PROMOTE: ds_read_b64
109; SI-PROMOTE: ds_read_b64
Changpeng Fang71369b32016-05-26 19:35:29 +0000[diff] [blame]110; CI-PROMOTE: ds_write2_b64
111; CI-PROMOTE: ds_read2_b64
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]112define void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) #1 {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]113 %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
Matt Arsenaultc5fce692016-04-28 18:38:48 +0000[diff] [blame]114 %array = alloca [8 x <2 x i64>], align 16
115 %ptr = getelementptr inbounds [8 x <2 x i64>], [8 x <2 x i64>]* %array, i32 0, i32 %b
Matt Arsenaultad41d7b2014-03-24 17:50:46 +0000[diff] [blame]116 store <2 x i64> %val, <2 x i64>* %ptr, align 16
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]117 call void @llvm.amdgcn.s.barrier()
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]118 %result = load <2 x i64>, <2 x i64>* %ptr, align 16
Matt Arsenaultad41d7b2014-03-24 17:50:46 +0000[diff] [blame]119 store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16
120 ret void
121}
Matt Arsenault9c47dd52016-02-11 06:02:01 +0000[diff] [blame]122
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000[diff] [blame]123attributes #0 = { convergent nounwind }
124attributes #1 = { nounwind "amdgpu-max-waves-per-eu"="2" "amdgpu-max-work-group-size"="64" }