blob: 4ab2480acf31018dc2812b2f490060fd226234af [file] [log] [blame]
Tom Stellardcb6ba622016-04-30 00:23:06 +00001//===-- GCNHazardRecognizers.h - GCN Hazard Recognizers ---------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines hazard recognizers for scheduling on GCN processors.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
15#define LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H
16
17#include "llvm/CodeGen/ScheduleHazardRecognizer.h"
18#include <functional>
19#include <list>
20
21namespace llvm {
22
23class MachineFunction;
24class MachineInstr;
25class ScheduleDAG;
26class SIInstrInfo;
27
28class GCNHazardRecognizer final : public ScheduleHazardRecognizer {
29
30 // This variable stores the instruction that has been emitted this cycle.
31 // It will be added to EmittedInstrs, when AdvanceCycle() or RecedeCycle() is
32 // called.
33 MachineInstr *CurrCycleInstr;
34 std::list<MachineInstr*> EmittedInstrs;
35 const MachineFunction &MF;
36
37 int getWaitStatesSinceDef(unsigned Reg,
38 std::function<bool(MachineInstr*)> IsHazardDef =
39 [](MachineInstr*) {return true;});
40
41 int checkSMRDHazards(MachineInstr *SMRD);
42 int checkVMEMHazards(MachineInstr* VMEM);
Tom Stellarda27007e2016-05-02 16:23:09 +000043 int checkDPPHazards(MachineInstr *DPP);
Tom Stellardcb6ba622016-04-30 00:23:06 +000044public:
45 GCNHazardRecognizer(const MachineFunction &MF);
46 // We can only issue one instruction per cycle.
47 bool atIssueLimit() const override { return true; }
48 void EmitInstruction(SUnit *SU) override;
49 void EmitInstruction(MachineInstr *MI) override;
50 HazardType getHazardType(SUnit *SU, int Stalls) override;
51 void EmitNoop() override;
52 unsigned PreEmitNoops(SUnit *SU) override;
53 unsigned PreEmitNoops(MachineInstr *) override;
54 void AdvanceCycle() override;
55 void RecedeCycle() override;
56};
57
58} // end namespace llvm
59
60#endif //LLVM_LIB_TARGET_AMDGPUHAZARDRECOGNIZERS_H