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Andrea Di Biagio3a6b0922018-03-08 13:05:02 +00001//===--------------------- BackendStatistics.h ------------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10///
11/// This file implements a printer class for printing generic Backend
12/// statistics related to the dispatch logic, scheduler and retire unit.
13///
14/// Example:
15/// ========
16///
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000017/// Dynamic Dispatch Stall Cycles:
18/// RAT - Register unavailable: 0
19/// RCU - Retire tokens unavailable: 0
20/// SCHEDQ - Scheduler full: 42
21/// LQ - Load queue full: 0
22/// SQ - Store queue full: 0
23/// GROUP - Static restrictions on the dispatch group: 0
24///
25///
26/// Register Alias Table:
27/// Total number of mappings created: 210
28/// Max number of mappings used: 35
29///
30///
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000031/// Dispatch Logic - number of cycles where we saw N instructions dispatched:
32/// [# dispatched], [# cycles]
33/// 0, 15 (11.5%)
34/// 5, 4 (3.1%)
35///
36/// Schedulers - number of cycles where we saw N instructions issued:
37/// [# issued], [# cycles]
38/// 0, 7 (5.4%)
39/// 1, 4 (3.1%)
40/// 2, 8 (6.2%)
41///
42/// Retire Control Unit - number of cycles where we saw N instructions retired:
43/// [# retired], [# cycles]
44/// 0, 9 (6.9%)
45/// 1, 6 (4.6%)
46/// 2, 1 (0.8%)
47/// 4, 3 (2.3%)
48///
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000049///
50/// Scheduler's queue usage:
51/// JALU01, 0/20
52/// JFPU01, 18/18
53/// JLSAGU, 0/12
54///
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000055//===----------------------------------------------------------------------===//
56
57#ifndef LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H
58#define LLVM_TOOLS_LLVM_MCA_BACKENDSTATISTICS_H
59
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000060#include "Backend.h"
61#include "View.h"
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +000062#include "llvm/ADT/SmallVector.h"
Andrea Di Biagio09771ad2018-03-16 22:21:52 +000063#include "llvm/MC/MCSubtargetInfo.h"
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000064#include "llvm/Support/raw_ostream.h"
65#include <map>
66
67namespace mca {
68
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000069class BackendStatistics : public View {
70 // TODO: remove the dependency from Backend.
71 const Backend &B;
Andrea Di Biagio09771ad2018-03-16 22:21:52 +000072 const llvm::MCSubtargetInfo &STI;
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +000073
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000074 using Histogram = std::map<unsigned, unsigned>;
75 Histogram DispatchGroupSizePerCycle;
76 Histogram RetiredPerCycle;
77 Histogram IssuedPerCycle;
78
79 unsigned NumDispatched;
80 unsigned NumIssued;
81 unsigned NumRetired;
82 unsigned NumCycles;
83
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +000084 // Counts dispatch stall events caused by unavailability of resources. There
85 // is one counter for every generic stall kind (see class HWStallEvent).
86 llvm::SmallVector<unsigned, 8> HWStalls;
87
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +000088 // Tracks the usage of a scheduler's queue.
89 struct BufferUsage {
90 unsigned SlotsInUse;
91 unsigned MaxUsedSlots;
92 };
93
94 // There is a map entry for each buffered resource in the scheduling model.
95 // Every time a buffer is consumed/freed, this view updates the corresponding
96 // entry.
97 llvm::DenseMap<unsigned, BufferUsage> BufferedResources;
98
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000099 void updateHistograms() {
100 DispatchGroupSizePerCycle[NumDispatched]++;
101 IssuedPerCycle[NumIssued]++;
102 RetiredPerCycle[NumRetired]++;
103 NumDispatched = 0;
104 NumIssued = 0;
105 NumRetired = 0;
106 }
107
108 void printRetireUnitStatistics(llvm::raw_ostream &OS) const;
109 void printDispatchUnitStatistics(llvm::raw_ostream &OS) const;
110 void printSchedulerStatistics(llvm::raw_ostream &OS) const;
111
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +0000112 void printDispatchStalls(llvm::raw_ostream &OS) const;
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000113 void printRATStatistics(llvm::raw_ostream &OS, unsigned Mappings,
114 unsigned MaxUsedMappings) const;
115 void printRCUStatistics(llvm::raw_ostream &OS, const Histogram &Histogram,
116 unsigned Cycles) const;
117 void printDispatchUnitUsage(llvm::raw_ostream &OS, const Histogram &Stats,
118 unsigned Cycles) const;
119 void printIssuePerCycle(const Histogram &IssuePerCycle,
120 unsigned TotalCycles) const;
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000121 void printSchedulerUsage(llvm::raw_ostream &OS,
122 const llvm::MCSchedModel &SM) const;
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000123
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000124public:
Andrea Di Biagio09771ad2018-03-16 22:21:52 +0000125 BackendStatistics(const Backend &backend, const llvm::MCSubtargetInfo &sti)
126 : B(backend), STI(sti), NumDispatched(0), NumIssued(0), NumRetired(0),
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +0000127 NumCycles(0), HWStalls(HWStallEvent::LastGenericEvent) {}
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000128
Clement Courbet844f22d2018-03-13 13:11:01 +0000129 void onInstructionEvent(const HWInstructionEvent &Event) override;
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000130
131 void onCycleBegin(unsigned Cycle) override { NumCycles++; }
132
133 void onCycleEnd(unsigned Cycle) override { updateHistograms(); }
134
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +0000135 void onStallEvent(const HWStallEvent &Event) override {
136 if (Event.Type < HWStallEvent::LastGenericEvent)
137 HWStalls[Event.Type]++;
138 }
139
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000140 // Increases the number of used scheduler queue slots of every buffered
141 // resource in the Buffers set.
142 void onReservedBuffers(llvm::ArrayRef<unsigned> Buffers);
143
144 // Decreases by one the number of used scheduler queue slots of every
145 // buffered resource in the Buffers set.
146 void onReleasedBuffers(llvm::ArrayRef<unsigned> Buffers);
147
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000148 void printView(llvm::raw_ostream &OS) const override {
Andrea Di Biagio91ab2ee2018-03-19 13:23:07 +0000149 printDispatchStalls(OS);
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000150 printRATStatistics(OS, B.getTotalRegisterMappingsCreated(),
Andrea Di Biagio53e6ade2018-03-09 12:50:42 +0000151 B.getMaxUsedRegisterMappings());
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000152 printDispatchUnitStatistics(OS);
153 printSchedulerStatistics(OS);
154 printRetireUnitStatistics(OS);
Andrea Di Biagio8af3fe82018-03-08 16:08:43 +0000155
Andrea Di Biagioa3f2e482018-03-20 18:20:39 +0000156 printSchedulerUsage(OS, STI.getSchedModel());
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000157 }
158};
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000159} // namespace mca
160
161#endif