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gerrit-public.fairphone.software / toolchain / llvm-project / a55333003d33ceb5857c315093bdd7e58af4ee92 / . / clang / test / CodeGen / builtins-mips-msa.c
blob: 125679545601f37f80b7fdd3b980f679b5c7f74d [file] [log] [blame]
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]1// REQUIRES: mips-registered-target
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]2// RUN: %clang_cc1 -triple mips-unknown-linux-gnu -emit-llvm %s \
3// RUN: -target-feature +msa -target-feature +fp64 \
4// RUN: -mfloat-abi hard -o - | FileCheck %s
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]5
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]6#include <msa.h>
7
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]8typedef __fp16 v8f16 __attribute__ ((vector_size(16)));
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]9
10void test(void) {
11 v16i8 v16i8_a = (v16i8) {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
12 v16i8 v16i8_b = (v16i8) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
13 v16i8 v16i8_r;
14 v8i16 v8i16_a = (v8i16) {0, 1, 2, 3, 4, 5, 6, 7};
15 v8i16 v8i16_b = (v8i16) {1, 2, 3, 4, 5, 6, 7, 8};
16 v8i16 v8i16_r;
17 v4i32 v4i32_a = (v4i32) {0, 1, 2, 3};
18 v4i32 v4i32_b = (v4i32) {1, 2, 3, 4};
19 v4i32 v4i32_r;
20 v2i64 v2i64_a = (v2i64) {0, 1};
21 v2i64 v2i64_b = (v2i64) {1, 2};
22 v2i64 v2i64_r;
23
24 v16u8 v16u8_a = (v16u8) {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
25 v16u8 v16u8_b = (v16u8) {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16};
26 v16u8 v16u8_r;
27 v8u16 v8u16_a = (v8u16) {0, 1, 2, 3, 4, 5, 6, 7};
28 v8u16 v8u16_b = (v8u16) {1, 2, 3, 4, 5, 6, 7, 8};
29 v8u16 v8u16_r;
30 v4u32 v4u32_a = (v4u32) {0, 1, 2, 3};
31 v4u32 v4u32_b = (v4u32) {1, 2, 3, 4};
32 v4u32 v4u32_r;
33 v2u64 v2u64_a = (v2u64) {0, 1};
34 v2u64 v2u64_b = (v2u64) {1, 2};
35 v2u64 v2u64_r;
36
37 v8f16 v8f16_a = (v8f16) {0.5, 1, 2, 3, 4, 5, 6, 7};
38 v8f16 v8f16_b = (v8f16) {1.5, 2, 3, 4, 5, 6, 7, 8};
39 v8f16 v8f16_r;
40 v4f32 v4f32_a = (v4f32) {0.5, 1, 2, 3};
41 v4f32 v4f32_b = (v4f32) {1.5, 2, 3, 4};
42 v4f32 v4f32_r;
43 v2f64 v2f64_a = (v2f64) {0.5, 1};
44 v2f64 v2f64_b = (v2f64) {1.5, 2};
45 v2f64 v2f64_r;
46
47 int int_r;
Daniel Sandersffd8df22013-10-23 10:12:44 +0000[diff] [blame]48 long long ll_r;
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]49 int int_a = 0;
50
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]51 v16i8_r = __msa_add_a_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.add.a.b(
52 v8i16_r = __msa_add_a_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.add.a.h(
53 v4i32_r = __msa_add_a_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.add.a.w(
54 v2i64_r = __msa_add_a_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.add.a.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]55
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]56 v16i8_r = __msa_adds_a_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.adds.a.b(
57 v8i16_r = __msa_adds_a_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.adds.a.h(
58 v4i32_r = __msa_adds_a_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.adds.a.w(
59 v2i64_r = __msa_adds_a_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.adds.a.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]60
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]61 v16i8_r = __msa_adds_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.adds.s.b(
62 v8i16_r = __msa_adds_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.adds.s.h(
63 v4i32_r = __msa_adds_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.adds.s.w(
64 v2i64_r = __msa_adds_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.adds.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]65
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]66 v16u8_r = __msa_adds_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.adds.u.b(
67 v8u16_r = __msa_adds_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.adds.u.h(
68 v4u32_r = __msa_adds_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.adds.u.w(
69 v2u64_r = __msa_adds_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.adds.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]70
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]71 v16i8_r = __msa_addv_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.addv.b(
72 v8i16_r = __msa_addv_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.addv.h(
73 v4i32_r = __msa_addv_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.addv.w(
74 v2i64_r = __msa_addv_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.addv.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]75
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]76 v16u8_r = __msa_addv_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.addv.b(
77 v8u16_r = __msa_addv_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.addv.h(
78 v4u32_r = __msa_addv_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.addv.w(
79 v2u64_r = __msa_addv_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.addv.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]80
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]81 v16i8_r = __msa_addvi_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.addvi.b(
82 v8i16_r = __msa_addvi_h(v8i16_a, 25); // CHECK: call <8 x i16> @llvm.mips.addvi.h(
83 v4i32_r = __msa_addvi_w(v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.addvi.w(
84 v2i64_r = __msa_addvi_d(v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.addvi.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]85
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]86 v16u8_r = __msa_addvi_b(v16u8_a, 25); // CHECK: call <16 x i8> @llvm.mips.addvi.b(
87 v8u16_r = __msa_addvi_h(v8u16_a, 25); // CHECK: call <8 x i16> @llvm.mips.addvi.h(
88 v4u32_r = __msa_addvi_w(v4u32_a, 25); // CHECK: call <4 x i32> @llvm.mips.addvi.w(
89 v2u64_r = __msa_addvi_d(v2u64_a, 25); // CHECK: call <2 x i64> @llvm.mips.addvi.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]90
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]91 v16i8_r = __msa_and_v(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.and.v(
92 v8i16_r = __msa_and_v(v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.and.v(
93 v4i32_r = __msa_and_v(v4i32_a, v4i32_b); // CHECK: call <16 x i8> @llvm.mips.and.v(
94 v2i64_r = __msa_and_v(v2i64_a, v2i64_b); // CHECK: call <16 x i8> @llvm.mips.and.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]95
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]96 v16i8_r = __msa_andi_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
97 v8i16_r = __msa_andi_b(v8i16_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
98 v4i32_r = __msa_andi_b(v4i32_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
99 v2i64_r = __msa_andi_b(v2i64_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]100
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]101 v16u8_r = __msa_andi_b(v16u8_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
102 v8u16_r = __msa_andi_b(v8u16_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
103 v4u32_r = __msa_andi_b(v4u32_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
104 v2u64_r = __msa_andi_b(v2u64_a, 25); // CHECK: call <16 x i8> @llvm.mips.andi.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]105
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]106 v16i8_r = __msa_asub_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.asub.s.b(
107 v8i16_r = __msa_asub_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.asub.s.h(
108 v4i32_r = __msa_asub_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.asub.s.w(
109 v2i64_r = __msa_asub_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.asub.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]110
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]111 v16u8_r = __msa_asub_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.asub.u.b(
112 v8u16_r = __msa_asub_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.asub.u.h(
113 v4u32_r = __msa_asub_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.asub.u.w(
114 v2u64_r = __msa_asub_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.asub.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]115
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]116 v16i8_r = __msa_ave_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.ave.s.b(
117 v8i16_r = __msa_ave_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.ave.s.h(
118 v4i32_r = __msa_ave_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.ave.s.w(
119 v2i64_r = __msa_ave_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.ave.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]120
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]121 v16u8_r = __msa_ave_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.ave.u.b(
122 v8u16_r = __msa_ave_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.ave.u.h(
123 v4u32_r = __msa_ave_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.ave.u.w(
124 v2u64_r = __msa_ave_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.ave.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]125
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]126 v16i8_r = __msa_aver_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.aver.s.b(
127 v8i16_r = __msa_aver_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.aver.s.h(
128 v4i32_r = __msa_aver_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.aver.s.w(
129 v2i64_r = __msa_aver_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.aver.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]130
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]131 v16u8_r = __msa_aver_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.aver.u.b(
132 v8u16_r = __msa_aver_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.aver.u.h(
133 v4u32_r = __msa_aver_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.aver.u.w(
134 v2u64_r = __msa_aver_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.aver.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]135
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]136 v16i8_r = __msa_bclr_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.bclr.b(
137 v8i16_r = __msa_bclr_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.bclr.h(
138 v4i32_r = __msa_bclr_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.bclr.w(
139 v2i64_r = __msa_bclr_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.bclr.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]140
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]141 v16i8_r = __msa_bclri_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.bclri.b(
142 v8i16_r = __msa_bclri_h(v8i16_a, 8); // CHECK: call <8 x i16> @llvm.mips.bclri.h(
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]143 v4i32_r = __msa_bclri_w(v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.bclri.w(
144 v2i64_r = __msa_bclri_d(v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.bclri.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]145
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]146 v16i8_r = __msa_binsl_b(v16i8_r, v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.binsl.b(
147 v8i16_r = __msa_binsl_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.binsl.h(
148 v4i32_r = __msa_binsl_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.binsl.w(
149 v2i64_r = __msa_binsl_d(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.binsl.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]150
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]151 v16i8_r = __msa_binsli_b(v16i8_r, v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.binsli.b(
152 v8i16_r = __msa_binsli_h(v8i16_r, v8i16_a, 8); // CHECK: call <8 x i16> @llvm.mips.binsli.h(
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]153 v4i32_r = __msa_binsli_w(v4i32_r, v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.binsli.w(
154 v2i64_r = __msa_binsli_d(v2i64_r, v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.binsli.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]155
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]156 v16i8_r = __msa_binsr_b(v16i8_r, v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.binsr.b(
157 v8i16_r = __msa_binsr_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.binsr.h(
158 v4i32_r = __msa_binsr_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.binsr.w(
159 v2i64_r = __msa_binsr_d(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.binsr.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]160
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]161 v16i8_r = __msa_binsri_b(v16i8_r, v16i8_a, 5); // CHECK: call <16 x i8> @llvm.mips.binsri.b(
162 v8i16_r = __msa_binsri_h(v8i16_r, v8i16_a, 15); // CHECK: call <8 x i16> @llvm.mips.binsri.h(
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]163 v4i32_r = __msa_binsri_w(v4i32_r, v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.binsri.w(
164 v2i64_r = __msa_binsri_d(v2i64_r, v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.binsri.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]165
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]166 v16i8_r = __msa_bmnz_v(v16i8_r, v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.bmnz.v(
167 v8i16_r = __msa_bmnz_v(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.bmnz.v(
168 v4i32_r = __msa_bmnz_v(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <16 x i8> @llvm.mips.bmnz.v(
169 v2i64_r = __msa_bmnz_v(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <16 x i8> @llvm.mips.bmnz.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]170
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]171 v16i8_r = __msa_bmnzi_b(v16i8_r, v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.bmnzi.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]172
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]173 v16i8_r = __msa_bmz_v(v16i8_r, v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.bmz.v(
174 v8i16_r = __msa_bmz_v(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.bmz.v(
175 v4i32_r = __msa_bmz_v(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <16 x i8> @llvm.mips.bmz.v(
176 v2i64_r = __msa_bmz_v(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <16 x i8> @llvm.mips.bmz.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]177
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]178 v16i8_r = __msa_bmzi_b(v16i8_r, v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.bmzi.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]179
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]180 v16i8_r = __msa_bneg_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.bneg.b(
181 v8i16_r = __msa_bneg_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.bneg.h(
182 v4i32_r = __msa_bneg_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.bneg.w(
183 v2i64_r = __msa_bneg_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.bneg.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]184
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]185 v16i8_r = __msa_bnegi_b(v16i8_a, 6); // CHECK: call <16 x i8> @llvm.mips.bnegi.b(
186 v8i16_r = __msa_bnegi_h(v8i16_a, 14); // CHECK: call <8 x i16> @llvm.mips.bnegi.h(
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]187 v4i32_r = __msa_bnegi_w(v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.bnegi.w(
188 v2i64_r = __msa_bnegi_d(v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.bnegi.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]189
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]190 int_r = __msa_test_bnz_b(v16i8_a); // CHECK: call i32 @llvm.mips.bnz.b(
191 int_r = __msa_test_bnz_h(v16i8_a); // CHECK: call i32 @llvm.mips.bnz.h(
192 int_r = __msa_test_bnz_w(v16i8_a); // CHECK: call i32 @llvm.mips.bnz.w(
193 int_r = __msa_test_bnz_d(v16i8_a); // CHECK: call i32 @llvm.mips.bnz.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]194
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]195 int_r = __msa_test_bnz_v(v16i8_a); // CHECK: call i32 @llvm.mips.bnz.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]196
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]197 v16i8_r = __msa_bsel_v(v16i8_r, v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.bsel.v(
198 v8i16_r = __msa_bsel_v(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.bsel.v(
199 v4i32_r = __msa_bsel_v(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <16 x i8> @llvm.mips.bsel.v(
200 v2i64_r = __msa_bsel_v(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <16 x i8> @llvm.mips.bsel.v(
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]201
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]202 v16i8_r = __msa_bseli_b(v16i8_r, v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.bseli.b(
Daniel Sandersab94b532013-10-30 15:20:38 +0000[diff] [blame]203
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]204 v16i8_r = __msa_bset_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.bset.b(
205 v8i16_r = __msa_bset_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.bset.h(
206 v4i32_r = __msa_bset_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.bset.w(
207 v2i64_r = __msa_bset_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.bset.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]208
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]209 v16i8_r = __msa_bseti_b(v16i8_a, 5); // CHECK: call <16 x i8> @llvm.mips.bseti.b(
210 v8i16_r = __msa_bseti_h(v8i16_a, 15); // CHECK: call <8 x i16> @llvm.mips.bseti.h(
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]211 v4i32_r = __msa_bseti_w(v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.bseti.w(
212 v2i64_r = __msa_bseti_d(v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.bseti.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]213
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]214 int_r = __msa_test_bz_b(v16i8_a); // CHECK: call i32 @llvm.mips.bz.b(
215 int_r = __msa_test_bz_h(v16i8_a); // CHECK: call i32 @llvm.mips.bz.h(
216 int_r = __msa_test_bz_w(v16i8_a); // CHECK: call i32 @llvm.mips.bz.w(
217 int_r = __msa_test_bz_d(v16i8_a); // CHECK: call i32 @llvm.mips.bz.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]218
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]219 int_r = __msa_test_bz_v(v16i8_a); // CHECK: call i32 @llvm.mips.bz.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]220
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]221 v16i8_r = __msa_ceq_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.ceq.b(
222 v8i16_r = __msa_ceq_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.ceq.h(
223 v4i32_r = __msa_ceq_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.ceq.w(
224 v2i64_r = __msa_ceq_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.ceq.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]225
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]226 v16i8_r = __msa_ceqi_b(v16i8_a, -3); // CHECK: call <16 x i8> @llvm.mips.ceqi.b(
227 v8i16_r = __msa_ceqi_h(v8i16_a, -12); // CHECK: call <8 x i16> @llvm.mips.ceqi.h(
228 v4i32_r = __msa_ceqi_w(v4i32_a, 14); // CHECK: call <4 x i32> @llvm.mips.ceqi.w(
229 v2i64_r = __msa_ceqi_d(v2i64_a, 15); // CHECK: call <2 x i64> @llvm.mips.ceqi.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]230
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]231 int_r = __msa_cfcmsa(1); // CHECK: call i32 @llvm.mips.cfcmsa(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]232
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]233 v16i8_r = __msa_cle_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.cle.s.b(
234 v8i16_r = __msa_cle_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.cle.s.h(
235 v4i32_r = __msa_cle_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.cle.s.w(
236 v2i64_r = __msa_cle_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.cle.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]237
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]238 v16u8_r = __msa_cle_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.cle.u.b(
239 v8u16_r = __msa_cle_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.cle.u.h(
240 v4u32_r = __msa_cle_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.cle.u.w(
241 v2u64_r = __msa_cle_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.cle.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]242
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]243 v16i8_r = __msa_clei_s_b(v16i8_a, 12); // CHECK: call <16 x i8> @llvm.mips.clei.s.b(
244 v8i16_r = __msa_clei_s_h(v8i16_a, 13); // CHECK: call <8 x i16> @llvm.mips.clei.s.h(
245 v4i32_r = __msa_clei_s_w(v4i32_a, 14); // CHECK: call <4 x i32> @llvm.mips.clei.s.w(
246 v2i64_r = __msa_clei_s_d(v2i64_a, 15); // CHECK: call <2 x i64> @llvm.mips.clei.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]247
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]248 v16u8_r = __msa_clei_u_b(v16u8_a, 25); // CHECK: call <16 x i8> @llvm.mips.clei.u.b(
249 v8u16_r = __msa_clei_u_h(v8u16_a, 25); // CHECK: call <8 x i16> @llvm.mips.clei.u.h(
250 v4u32_r = __msa_clei_u_w(v4u32_a, 25); // CHECK: call <4 x i32> @llvm.mips.clei.u.w(
251 v2u64_r = __msa_clei_u_d(v2u64_a, 25); // CHECK: call <2 x i64> @llvm.mips.clei.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]252
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]253 v16i8_r = __msa_clt_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.clt.s.b(
254 v8i16_r = __msa_clt_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.clt.s.h(
255 v4i32_r = __msa_clt_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.clt.s.w(
256 v2i64_r = __msa_clt_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.clt.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]257
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]258 v16u8_r = __msa_clt_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.clt.u.b(
259 v8u16_r = __msa_clt_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.clt.u.h(
260 v4u32_r = __msa_clt_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.clt.u.w(
261 v2u64_r = __msa_clt_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.clt.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]262
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]263 v16i8_r = __msa_clti_s_b(v16i8_a, 15); // CHECK: call <16 x i8> @llvm.mips.clti.s.b(
264 v8i16_r = __msa_clti_s_h(v8i16_a, 15); // CHECK: call <8 x i16> @llvm.mips.clti.s.h(
265 v4i32_r = __msa_clti_s_w(v4i32_a, 15); // CHECK: call <4 x i32> @llvm.mips.clti.s.w(
266 v2i64_r = __msa_clti_s_d(v2i64_a, 15); // CHECK: call <2 x i64> @llvm.mips.clti.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]267
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]268 v16u8_r = __msa_clti_u_b(v16u8_a, 25); // CHECK: call <16 x i8> @llvm.mips.clti.u.b(
269 v8u16_r = __msa_clti_u_h(v8u16_a, 25); // CHECK: call <8 x i16> @llvm.mips.clti.u.h(
270 v4u32_r = __msa_clti_u_w(v4u32_a, 25); // CHECK: call <4 x i32> @llvm.mips.clti.u.w(
271 v2u64_r = __msa_clti_u_d(v2u64_a, 25); // CHECK: call <2 x i64> @llvm.mips.clti.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]272
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]273 int_r = __msa_copy_s_b(v16i8_a, 1); // CHECK: call i32 @llvm.mips.copy.s.b(
274 int_r = __msa_copy_s_h(v8i16_a, 1); // CHECK: call i32 @llvm.mips.copy.s.h(
275 int_r = __msa_copy_s_w(v4i32_a, 1); // CHECK: call i32 @llvm.mips.copy.s.w(
276 ll_r = __msa_copy_s_d(v2i64_a, 1); // CHECK: call i64 @llvm.mips.copy.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]277
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]278 int_r = __msa_copy_u_b(v16u8_a, 1); // CHECK: call i32 @llvm.mips.copy.u.b(
279 int_r = __msa_copy_u_h(v8u16_a, 1); // CHECK: call i32 @llvm.mips.copy.u.h(
280 int_r = __msa_copy_u_w(v4u32_a, 1); // CHECK: call i32 @llvm.mips.copy.u.w(
281 ll_r = __msa_copy_u_d(v2i64_a, 1); // CHECK: call i64 @llvm.mips.copy.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]282
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]283 __builtin_msa_ctcmsa(1, int_a); // CHECK: call void @llvm.mips.ctcmsa(
284
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]285 v16i8_r = __msa_div_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.div.s.b(
286 v8i16_r = __msa_div_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.div.s.h(
287 v4i32_r = __msa_div_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.div.s.w(
288 v2i64_r = __msa_div_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.div.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]289
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]290 v16u8_r = __msa_div_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.div.u.b(
291 v8u16_r = __msa_div_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.div.u.h(
292 v4u32_r = __msa_div_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.div.u.w(
293 v2u64_r = __msa_div_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.div.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]294
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]295 v8i16_r = __msa_dotp_s_h(v16i8_a, v16i8_b); // CHECK: call <8 x i16> @llvm.mips.dotp.s.h(
296 v4i32_r = __msa_dotp_s_w(v8i16_a, v8i16_b); // CHECK: call <4 x i32> @llvm.mips.dotp.s.w(
297 v2i64_r = __msa_dotp_s_d(v4i32_a, v4i32_b); // CHECK: call <2 x i64> @llvm.mips.dotp.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]298
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]299 v8u16_r = __msa_dotp_u_h(v16u8_a, v16u8_b); // CHECK: call <8 x i16> @llvm.mips.dotp.u.h(
300 v4u32_r = __msa_dotp_u_w(v8u16_a, v8u16_b); // CHECK: call <4 x i32> @llvm.mips.dotp.u.w(
301 v2u64_r = __msa_dotp_u_d(v4u32_a, v4u32_b); // CHECK: call <2 x i64> @llvm.mips.dotp.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]302
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]303 v8i16_r = __msa_dpadd_s_h(v8i16_r, v16i8_a, v16i8_b); // CHECK: call <8 x i16> @llvm.mips.dpadd.s.h(
304 v4i32_r = __msa_dpadd_s_w(v4i32_r, v8i16_a, v8i16_b); // CHECK: call <4 x i32> @llvm.mips.dpadd.s.w(
305 v2i64_r = __msa_dpadd_s_d(v2i64_r, v4i32_a, v4i32_b); // CHECK: call <2 x i64> @llvm.mips.dpadd.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]306
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]307 v8u16_r = __msa_dpadd_u_h(v8u16_r, v16u8_a, v16u8_b); // CHECK: call <8 x i16> @llvm.mips.dpadd.u.h(
308 v4u32_r = __msa_dpadd_u_w(v4u32_r, v8u16_a, v8u16_b); // CHECK: call <4 x i32> @llvm.mips.dpadd.u.w(
309 v2u64_r = __msa_dpadd_u_d(v2u64_r, v4u32_a, v4u32_b); // CHECK: call <2 x i64> @llvm.mips.dpadd.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]310
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]311 v8i16_r = __msa_dpsub_s_h(v8i16_r, v16i8_a, v16i8_b); // CHECK: call <8 x i16> @llvm.mips.dpsub.s.h(
312 v4i32_r = __msa_dpsub_s_w(v4i32_r, v8i16_a, v8i16_b); // CHECK: call <4 x i32> @llvm.mips.dpsub.s.w(
313 v2i64_r = __msa_dpsub_s_d(v2i64_r, v4i32_a, v4i32_b); // CHECK: call <2 x i64> @llvm.mips.dpsub.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]314
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]315 v8u16_r = __msa_dpsub_u_h(v8u16_r, v16u8_a, v16u8_b); // CHECK: call <8 x i16> @llvm.mips.dpsub.u.h(
316 v4u32_r = __msa_dpsub_u_w(v4u32_r, v8u16_a, v8u16_b); // CHECK: call <4 x i32> @llvm.mips.dpsub.u.w(
317 v2u64_r = __msa_dpsub_u_d(v2u64_r, v4u32_a, v4u32_b); // CHECK: call <2 x i64> @llvm.mips.dpsub.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]318
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]319 v4f32_r = __msa_fadd_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fadd.w(
320 v2f64_r = __msa_fadd_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fadd.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]321
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]322 v4i32_r = __msa_fcaf_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcaf.w(
323 v2i64_r = __msa_fcaf_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcaf.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]324
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]325 v4i32_r = __msa_fceq_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fceq.w(
326 v2i64_r = __msa_fceq_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fceq.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]327
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]328 v4i32_r = __msa_fclass_w(v4f32_a); // CHECK: call <4 x i32> @llvm.mips.fclass.w(
329 v2i64_r = __msa_fclass_d(v2f64_a); // CHECK: call <2 x i64> @llvm.mips.fclass.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]330
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]331 v4i32_r = __msa_fcle_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcle.w(
332 v2i64_r = __msa_fcle_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcle.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]333
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]334 v4i32_r = __msa_fclt_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fclt.w(
335 v2i64_r = __msa_fclt_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fclt.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]336
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]337 v4i32_r = __msa_fcne_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcne.w(
338 v2i64_r = __msa_fcne_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcne.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]339
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]340 v4i32_r = __msa_fcor_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcor.w(
341 v2i64_r = __msa_fcor_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcor.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]342
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]343 v4i32_r = __msa_fcueq_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcueq.w(
344 v2i64_r = __msa_fcueq_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcueq.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]345
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]346 v4i32_r = __msa_fcule_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcule.w(
347 v2i64_r = __msa_fcule_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcule.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]348
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]349 v4i32_r = __msa_fcult_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcult.w(
350 v2i64_r = __msa_fcult_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcult.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]351
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]352 v4i32_r = __msa_fcun_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcun.w(
353 v2i64_r = __msa_fcun_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcun.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]354
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]355 v4i32_r = __msa_fcune_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fcune.w(
356 v2i64_r = __msa_fcune_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fcune.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]357
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]358 v4f32_r = __msa_fdiv_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fdiv.w(
359 v2f64_r = __msa_fdiv_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fdiv.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]360
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]361 v8f16_r = __msa_fexdo_h(v4f32_a, v4f32_b); // CHECK: call <8 x half> @llvm.mips.fexdo.h(
362 v4f32_r = __msa_fexdo_w(v2f64_a, v2f64_b); // CHECK: call <4 x float> @llvm.mips.fexdo.w(
Daniel Sandersb545c252013-08-20 09:47:12 +0000[diff] [blame]363
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]364 v4f32_r = __msa_fexp2_w(v4f32_a, v4i32_b); // CHECK: call <4 x float> @llvm.mips.fexp2.w(
365 v2f64_r = __msa_fexp2_d(v2f64_a, v2i64_b); // CHECK: call <2 x double> @llvm.mips.fexp2.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]366
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]367 v4f32_r = __msa_fexupl_w(v8f16_a); // CHECK: call <4 x float> @llvm.mips.fexupl.w(
368 v2f64_r = __msa_fexupl_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.fexupl.d(
Daniel Sandersb545c252013-08-20 09:47:12 +0000[diff] [blame]369
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]370 v4f32_r = __msa_fexupr_w(v8f16_a); // CHECK: call <4 x float> @llvm.mips.fexupr.w(
371 v2f64_r = __msa_fexupr_d(v4f32_a); // CHECK: call <2 x double> @llvm.mips.fexupr.d(
Daniel Sandersb545c252013-08-20 09:47:12 +0000[diff] [blame]372
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]373 v4f32_r = __msa_ffint_s_w(v4i32_a); // CHECK: call <4 x float> @llvm.mips.ffint.s.w(
374 v2f64_r = __msa_ffint_s_d(v2i64_a); // CHECK: call <2 x double> @llvm.mips.ffint.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]375
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]376 v4f32_r = __msa_ffint_u_w(v4i32_a); // CHECK: call <4 x float> @llvm.mips.ffint.u.w(
377 v2f64_r = __msa_ffint_u_d(v2i64_a); // CHECK: call <2 x double> @llvm.mips.ffint.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]378
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]379 v4f32_r = __msa_ffql_w(v8i16_a); // CHECK: call <4 x float> @llvm.mips.ffql.w(
380 v2f64_r = __msa_ffql_d(v4i32_a); // CHECK: call <2 x double> @llvm.mips.ffql.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]381
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]382 v4f32_r = __msa_ffqr_w(v8i16_a); // CHECK: call <4 x float> @llvm.mips.ffqr.w(
383 v2f64_r = __msa_ffqr_d(v4i32_a); // CHECK: call <2 x double> @llvm.mips.ffqr.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]384
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]385 v16i8_r = __msa_fill_b(3); // CHECK: call <16 x i8> @llvm.mips.fill.b(
386 v8i16_r = __msa_fill_h(3); // CHECK: call <8 x i16> @llvm.mips.fill.h(
387 v4i32_r = __msa_fill_w(3); // CHECK: call <4 x i32> @llvm.mips.fill.w(
388 v2i64_r = __msa_fill_d(3); // CHECK: call <2 x i64> @llvm.mips.fill.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]389
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]390 v4f32_r = __msa_flog2_w(v4f32_a); // CHECK: call <4 x float> @llvm.mips.flog2.w(
391 v2f64_r = __msa_flog2_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.flog2.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]392
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]393 v4f32_r = __msa_fmadd_w(v4f32_r, v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fmadd.w(
394 v2f64_r = __msa_fmadd_d(v2f64_r, v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmadd.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]395
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]396 v4f32_r = __msa_fmax_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fmax.w(
397 v2f64_r = __msa_fmax_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmax.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]398
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]399 v4f32_r = __msa_fmax_a_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fmax.a.w(
400 v2f64_r = __msa_fmax_a_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmax.a.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]401
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]402 v4f32_r = __msa_fmin_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fmin.w(
403 v2f64_r = __msa_fmin_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmin.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]404
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]405 v4f32_r = __msa_fmin_a_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fmin.a.w(
406 v2f64_r = __msa_fmin_a_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmin.a.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]407
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]408 v4f32_r = __msa_fmsub_w(v4f32_r, v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fmsub.w(
409 v2f64_r = __msa_fmsub_d(v2f64_r, v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmsub.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]410
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]411 v4f32_r = __msa_fmul_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fmul.w(
412 v2f64_r = __msa_fmul_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fmul.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]413
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]414 v4f32_r = __msa_frint_w(v4f32_a); // CHECK: call <4 x float> @llvm.mips.frint.w(
415 v2f64_r = __msa_frint_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.frint.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]416
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]417 v4f32_r = __msa_frcp_w(v4f32_a); // CHECK: call <4 x float> @llvm.mips.frcp.w(
418 v2f64_r = __msa_frcp_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.frcp.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]419
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]420 v4f32_r = __msa_frsqrt_w(v4f32_a); // CHECK: call <4 x float> @llvm.mips.frsqrt.w(
421 v2f64_r = __msa_frsqrt_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.frsqrt.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]422
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]423 v4i32_r = __msa_fseq_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fseq.w(
424 v2i64_r = __msa_fseq_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fseq.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]425
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]426 v4i32_r = __msa_fsaf_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsaf.w(
427 v2i64_r = __msa_fsaf_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsaf.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]428
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]429 v4i32_r = __msa_fsle_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsle.w(
430 v2i64_r = __msa_fsle_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsle.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]431
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]432 v4i32_r = __msa_fslt_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fslt.w(
433 v2i64_r = __msa_fslt_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fslt.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]434
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]435 v4i32_r = __msa_fsne_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsne.w(
436 v2i64_r = __msa_fsne_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsne.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]437
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]438 v4i32_r = __msa_fsor_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsor.w(
439 v2i64_r = __msa_fsor_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsor.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]440
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]441 v4f32_r = __msa_fsqrt_w(v4f32_a); // CHECK: call <4 x float> @llvm.mips.fsqrt.w(
442 v2f64_r = __msa_fsqrt_d(v2f64_a); // CHECK: call <2 x double> @llvm.mips.fsqrt.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]443
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]444 v4f32_r = __msa_fsub_w(v4f32_a, v4f32_b); // CHECK: call <4 x float> @llvm.mips.fsub.w(
445 v2f64_r = __msa_fsub_d(v2f64_a, v2f64_b); // CHECK: call <2 x double> @llvm.mips.fsub.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]446
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]447 v4i32_r = __msa_fsueq_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsueq.w(
448 v2i64_r = __msa_fsueq_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsueq.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]449
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]450 v4i32_r = __msa_fsule_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsule.w(
451 v2i64_r = __msa_fsule_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsule.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]452
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]453 v4i32_r = __msa_fsult_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsult.w(
454 v2i64_r = __msa_fsult_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsult.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]455
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]456 v4i32_r = __msa_fsun_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsun.w(
457 v2i64_r = __msa_fsun_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsun.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]458
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]459 v4i32_r = __msa_fsune_w(v4f32_a, v4f32_b); // CHECK: call <4 x i32> @llvm.mips.fsune.w(
460 v2i64_r = __msa_fsune_d(v2f64_a, v2f64_b); // CHECK: call <2 x i64> @llvm.mips.fsune.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]461
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]462 v4i32_r = __msa_ftint_s_w(v4f32_a); // CHECK: call <4 x i32> @llvm.mips.ftint.s.w(
463 v2i64_r = __msa_ftint_s_d(v2f64_a); // CHECK: call <2 x i64> @llvm.mips.ftint.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]464
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]465 v4i32_r = __msa_ftint_u_w(v4f32_a); // CHECK: call <4 x i32> @llvm.mips.ftint.u.w(
466 v2i64_r = __msa_ftint_u_d(v2f64_a); // CHECK: call <2 x i64> @llvm.mips.ftint.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]467
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]468 v8i16_r = __msa_ftq_h(v4f32_a, v4f32_b); // CHECK: call <8 x i16> @llvm.mips.ftq.h(
469 v4i32_r = __msa_ftq_w(v2f64_a, v2f64_b); // CHECK: call <4 x i32> @llvm.mips.ftq.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]470
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]471 v4i32_r = __msa_ftrunc_s_w(v4f32_a); // CHECK: call <4 x i32> @llvm.mips.ftrunc.s.w(
472 v2i64_r = __msa_ftrunc_s_d(v2f64_a); // CHECK: call <2 x i64> @llvm.mips.ftrunc.s.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]473
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]474 v4i32_r = __msa_ftrunc_u_w(v4f32_a); // CHECK: call <4 x i32> @llvm.mips.ftrunc.u.w(
475 v2i64_r = __msa_ftrunc_u_d(v2f64_a); // CHECK: call <2 x i64> @llvm.mips.ftrunc.u.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]476
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]477 v8i16_r = __msa_hadd_s_h(v16i8_a, v16i8_b); // CHECK: call <8 x i16> @llvm.mips.hadd.s.h(
478 v4i32_r = __msa_hadd_s_w(v8i16_a, v8i16_b); // CHECK: call <4 x i32> @llvm.mips.hadd.s.w(
479 v2i64_r = __msa_hadd_s_d(v4i32_a, v4i32_b); // CHECK: call <2 x i64> @llvm.mips.hadd.s.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]480
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]481 v8u16_r = __msa_hadd_u_h(v16u8_a, v16u8_b); // CHECK: call <8 x i16> @llvm.mips.hadd.u.h(
482 v4u32_r = __msa_hadd_u_w(v8u16_a, v8u16_b); // CHECK: call <4 x i32> @llvm.mips.hadd.u.w(
483 v2u64_r = __msa_hadd_u_d(v4u32_a, v4u32_b); // CHECK: call <2 x i64> @llvm.mips.hadd.u.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]484
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]485 v8i16_r = __msa_hsub_s_h(v16i8_a, v16i8_b); // CHECK: call <8 x i16> @llvm.mips.hsub.s.h(
486 v4i32_r = __msa_hsub_s_w(v8i16_a, v8i16_b); // CHECK: call <4 x i32> @llvm.mips.hsub.s.w(
487 v2i64_r = __msa_hsub_s_d(v4i32_a, v4i32_b); // CHECK: call <2 x i64> @llvm.mips.hsub.s.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]488
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]489 v8u16_r = __msa_hsub_u_h(v16u8_a, v16u8_b); // CHECK: call <8 x i16> @llvm.mips.hsub.u.h(
490 v4u32_r = __msa_hsub_u_w(v8u16_a, v8u16_b); // CHECK: call <4 x i32> @llvm.mips.hsub.u.w(
491 v2u64_r = __msa_hsub_u_d(v4u32_a, v4u32_b); // CHECK: call <2 x i64> @llvm.mips.hsub.u.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]492
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]493 v16i8_r = __msa_ilvev_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.ilvev.b(
494 v8i16_r = __msa_ilvev_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.ilvev.h(
495 v4i32_r = __msa_ilvev_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.ilvev.w(
496 v2i64_r = __msa_ilvev_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.ilvev.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]497
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]498 v16i8_r = __msa_ilvl_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.ilvl.b(
499 v8i16_r = __msa_ilvl_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.ilvl.h(
500 v4i32_r = __msa_ilvl_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.ilvl.w(
501 v2i64_r = __msa_ilvl_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.ilvl.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]502
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]503 v16i8_r = __msa_ilvod_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.ilvod.b(
504 v8i16_r = __msa_ilvod_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.ilvod.h(
505 v4i32_r = __msa_ilvod_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.ilvod.w(
506 v2i64_r = __msa_ilvod_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.ilvod.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]507
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]508 v16i8_r = __msa_ilvr_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.ilvr.b(
509 v8i16_r = __msa_ilvr_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.ilvr.h(
510 v4i32_r = __msa_ilvr_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.ilvr.w(
511 v2i64_r = __msa_ilvr_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.ilvr.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]512
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]513 v16i8_r = __msa_insert_b(v16i8_r, 1, 25); // CHECK: call <16 x i8> @llvm.mips.insert.b(
514 v8i16_r = __msa_insert_h(v8i16_r, 1, 25); // CHECK: call <8 x i16> @llvm.mips.insert.h(
515 v4i32_r = __msa_insert_w(v4i32_r, 1, 25); // CHECK: call <4 x i32> @llvm.mips.insert.w(
516 v2i64_r = __msa_insert_d(v2i64_r, 1, 25); // CHECK: call <2 x i64> @llvm.mips.insert.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]517
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]518 v16i8_r = __msa_insve_b(v16i8_r, 1, v16i8_a); // CHECK: call <16 x i8> @llvm.mips.insve.b(
519 v8i16_r = __msa_insve_h(v8i16_r, 1, v8i16_a); // CHECK: call <8 x i16> @llvm.mips.insve.h(
520 v4i32_r = __msa_insve_w(v4i32_r, 1, v4i32_a); // CHECK: call <4 x i32> @llvm.mips.insve.w(
521 v2i64_r = __msa_insve_d(v2i64_r, 1, v2i64_a); // CHECK: call <2 x i64> @llvm.mips.insve.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]522
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]523 v16i8_r = __msa_ld_b(&v16i8_a, 16); // CHECK: call <16 x i8> @llvm.mips.ld.b(
524 v8i16_r = __msa_ld_h(&v8i16_a, 32); // CHECK: call <8 x i16> @llvm.mips.ld.h(
525 v4i32_r = __msa_ld_w(&v4i32_a, 48); // CHECK: call <4 x i32> @llvm.mips.ld.w(
526 v2i64_r = __msa_ld_d(&v2i64_a, 96); // CHECK: call <2 x i64> @llvm.mips.ld.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]527
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]528 v16i8_r = __msa_ldi_b(3); // CHECK: call <16 x i8> @llvm.mips.ldi.b(
529 v8i16_r = __msa_ldi_h(3); // CHECK: call <8 x i16> @llvm.mips.ldi.h(
530 v4i32_r = __msa_ldi_w(3); // CHECK: call <4 x i32> @llvm.mips.ldi.w(
531 v2i64_r = __msa_ldi_d(3); // CHECK: call <2 x i64> @llvm.mips.ldi.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]532
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]533 v8i16_r = __msa_madd_q_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.madd.q.h(
534 v4i32_r = __msa_madd_q_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.madd.q.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]535
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]536 v8i16_r = __msa_maddr_q_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.maddr.q.h(
537 v4i32_r = __msa_maddr_q_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.maddr.q.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]538
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]539 v16i8_r = __msa_maddv_b(v16i8_r, v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.maddv.b(
540 v8i16_r = __msa_maddv_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.maddv.h(
541 v4i32_r = __msa_maddv_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.maddv.w(
542 v2i64_r = __msa_maddv_d(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.maddv.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]543
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]544 v16i8_r = __msa_max_a_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.max.a.b(
545 v8i16_r = __msa_max_a_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.max.a.h(
546 v4i32_r = __msa_max_a_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.max.a.w(
547 v2i64_r = __msa_max_a_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.max.a.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]548
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]549 v16i8_r = __msa_max_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.max.s.b(
550 v8i16_r = __msa_max_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.max.s.h(
551 v4i32_r = __msa_max_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.max.s.w(
552 v2i64_r = __msa_max_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.max.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]553
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]554 v16u8_r = __msa_max_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.max.u.b(
555 v8u16_r = __msa_max_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.max.u.h(
556 v4u32_r = __msa_max_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.max.u.w(
557 v2u64_r = __msa_max_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.max.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]558
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]559 v16i8_r = __msa_maxi_s_b(v16i8_a, 2); // CHECK: call <16 x i8> @llvm.mips.maxi.s.b(
560 v8i16_r = __msa_maxi_s_h(v8i16_a, 2); // CHECK: call <8 x i16> @llvm.mips.maxi.s.h(
561 v4i32_r = __msa_maxi_s_w(v4i32_a, 2); // CHECK: call <4 x i32> @llvm.mips.maxi.s.w(
562 v2i64_r = __msa_maxi_s_d(v2i64_a, 2); // CHECK: call <2 x i64> @llvm.mips.maxi.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]563
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]564 v16u8_r = __msa_maxi_u_b(v16u8_a, 2); // CHECK: call <16 x i8> @llvm.mips.maxi.u.b(
565 v8u16_r = __msa_maxi_u_h(v8u16_a, 2); // CHECK: call <8 x i16> @llvm.mips.maxi.u.h(
566 v4u32_r = __msa_maxi_u_w(v4u32_a, 2); // CHECK: call <4 x i32> @llvm.mips.maxi.u.w(
567 v2u64_r = __msa_maxi_u_d(v2u64_a, 2); // CHECK: call <2 x i64> @llvm.mips.maxi.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]568
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]569 v16i8_r = __msa_min_a_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.min.a.b(
570 v8i16_r = __msa_min_a_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.min.a.h(
571 v4i32_r = __msa_min_a_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.min.a.w(
572 v2i64_r = __msa_min_a_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.min.a.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]573
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]574 v16i8_r = __msa_min_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.min.s.b(
575 v8i16_r = __msa_min_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.min.s.h(
576 v4i32_r = __msa_min_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.min.s.w(
577 v2i64_r = __msa_min_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.min.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]578
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]579 v16u8_r = __msa_min_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.min.u.b(
580 v8u16_r = __msa_min_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.min.u.h(
581 v4u32_r = __msa_min_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.min.u.w(
582 v2u64_r = __msa_min_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.min.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]583
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]584 v16i8_r = __msa_mini_s_b(v16i8_a, 2); // CHECK: call <16 x i8> @llvm.mips.mini.s.b(
585 v8i16_r = __msa_mini_s_h(v8i16_a, 2); // CHECK: call <8 x i16> @llvm.mips.mini.s.h(
586 v4i32_r = __msa_mini_s_w(v4i32_a, 2); // CHECK: call <4 x i32> @llvm.mips.mini.s.w(
587 v2i64_r = __msa_mini_s_d(v2i64_a, 2); // CHECK: call <2 x i64> @llvm.mips.mini.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]588
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]589 v16u8_r = __msa_mini_u_b(v16u8_a, 2); // CHECK: call <16 x i8> @llvm.mips.mini.u.b(
590 v8u16_r = __msa_mini_u_h(v8u16_a, 2); // CHECK: call <8 x i16> @llvm.mips.mini.u.h(
591 v4u32_r = __msa_mini_u_w(v4u32_a, 2); // CHECK: call <4 x i32> @llvm.mips.mini.u.w(
592 v2u64_r = __msa_mini_u_d(v2u64_a, 2); // CHECK: call <2 x i64> @llvm.mips.mini.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]593
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]594 v16i8_r = __msa_mod_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.mod.s.b(
595 v8i16_r = __msa_mod_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.mod.s.h(
596 v4i32_r = __msa_mod_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.mod.s.w(
597 v2i64_r = __msa_mod_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.mod.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]598
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]599 v16u8_r = __msa_mod_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.mod.u.b(
600 v8u16_r = __msa_mod_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.mod.u.h(
601 v4u32_r = __msa_mod_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.mod.u.w(
602 v2u64_r = __msa_mod_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.mod.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]603
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]604 v16i8_r = __msa_move_v(v16i8_a); // CHECK: call <16 x i8> @llvm.mips.move.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]605
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]606 v8i16_r = __msa_msub_q_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.msub.q.h(
607 v4i32_r = __msa_msub_q_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.msub.q.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]608
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]609 v8i16_r = __msa_msubr_q_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.msubr.q.h(
610 v4i32_r = __msa_msubr_q_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.msubr.q.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]611
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]612 v16i8_r = __msa_msubv_b(v16i8_r, v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.msubv.b(
613 v8i16_r = __msa_msubv_h(v8i16_r, v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.msubv.h(
614 v4i32_r = __msa_msubv_w(v4i32_r, v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.msubv.w(
615 v2i64_r = __msa_msubv_d(v2i64_r, v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.msubv.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]616
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]617 v8i16_r = __msa_mul_q_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.mul.q.h(
618 v4i32_r = __msa_mul_q_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.mul.q.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]619
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]620 v8i16_r = __msa_mulr_q_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.mulr.q.h(
621 v4i32_r = __msa_mulr_q_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.mulr.q.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]622
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]623 v16i8_r = __msa_mulv_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.mulv.b(
624 v8i16_r = __msa_mulv_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.mulv.h(
625 v4i32_r = __msa_mulv_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.mulv.w(
626 v2i64_r = __msa_mulv_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.mulv.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]627
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]628 v16i8_r = __msa_nloc_b(v16i8_a); // CHECK: call <16 x i8> @llvm.mips.nloc.b(
629 v8i16_r = __msa_nloc_h(v8i16_a); // CHECK: call <8 x i16> @llvm.mips.nloc.h(
630 v4i32_r = __msa_nloc_w(v4i32_a); // CHECK: call <4 x i32> @llvm.mips.nloc.w(
631 v2i64_r = __msa_nloc_d(v2i64_a); // CHECK: call <2 x i64> @llvm.mips.nloc.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]632
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]633 v16i8_r = __msa_nlzc_b(v16i8_a); // CHECK: call <16 x i8> @llvm.mips.nlzc.b(
634 v8i16_r = __msa_nlzc_h(v8i16_a); // CHECK: call <8 x i16> @llvm.mips.nlzc.h(
635 v4i32_r = __msa_nlzc_w(v4i32_a); // CHECK: call <4 x i32> @llvm.mips.nlzc.w(
636 v2i64_r = __msa_nlzc_d(v2i64_a); // CHECK: call <2 x i64> @llvm.mips.nlzc.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]637
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]638 v16i8_r = __msa_nor_v(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.nor.v(
639 v8i16_r = __msa_nor_v(v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.nor.v(
640 v4i32_r = __msa_nor_v(v4i32_a, v4i32_b); // CHECK: call <16 x i8> @llvm.mips.nor.v(
641 v2i64_r = __msa_nor_v(v2i64_a, v2i64_b); // CHECK: call <16 x i8> @llvm.mips.nor.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]642
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]643 v16i8_r = __msa_nori_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
644 v8i16_r = __msa_nori_b(v8i16_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
645 v4i32_r = __msa_nori_b(v4i32_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
646 v2i64_r = __msa_nori_b(v2i64_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]647
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]648 v16u8_r = __msa_nori_b(v16u8_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
649 v8u16_r = __msa_nori_b(v8u16_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
650 v4u32_r = __msa_nori_b(v4u32_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
651 v2u64_r = __msa_nori_b(v2u64_a, 25); // CHECK: call <16 x i8> @llvm.mips.nori.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]652
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]653 v16i8_r = __msa_or_v(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.or.v(
654 v8i16_r = __msa_or_v(v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.or.v(
655 v4i32_r = __msa_or_v(v4i32_a, v4i32_b); // CHECK: call <16 x i8> @llvm.mips.or.v(
656 v2i64_r = __msa_or_v(v2i64_a, v2i64_b); // CHECK: call <16 x i8> @llvm.mips.or.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]657
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]658 v16i8_r = __msa_ori_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
659 v8i16_r = __msa_ori_b(v8i16_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
660 v4i32_r = __msa_ori_b(v4i32_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
661 v2i64_r = __msa_ori_b(v2i64_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]662
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]663 v16u8_r = __msa_ori_b(v16u8_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
664 v8u16_r = __msa_ori_b(v8u16_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
665 v4u32_r = __msa_ori_b(v4u32_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
666 v2u64_r = __msa_ori_b(v2u64_a, 25); // CHECK: call <16 x i8> @llvm.mips.ori.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]667
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]668 v16i8_r = __msa_pckev_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.pckev.b(
669 v8i16_r = __msa_pckev_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.pckev.h(
670 v4i32_r = __msa_pckev_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.pckev.w(
671 v2i64_r = __msa_pckev_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.pckev.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]672
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]673 v16i8_r = __msa_pckod_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.pckod.b(
674 v8i16_r = __msa_pckod_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.pckod.h(
675 v4i32_r = __msa_pckod_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.pckod.w(
676 v2i64_r = __msa_pckod_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.pckod.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]677
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]678 v16i8_r = __msa_pcnt_b(v16i8_a); // CHECK: call <16 x i8> @llvm.mips.pcnt.b(
679 v8i16_r = __msa_pcnt_h(v8i16_a); // CHECK: call <8 x i16> @llvm.mips.pcnt.h(
680 v4i32_r = __msa_pcnt_w(v4i32_a); // CHECK: call <4 x i32> @llvm.mips.pcnt.w(
681 v2i64_r = __msa_pcnt_d(v2i64_a); // CHECK: call <2 x i64> @llvm.mips.pcnt.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]682
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]683 v16i8_r = __msa_sat_s_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.sat.s.b(
684 v8i16_r = __msa_sat_s_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.sat.s.h(
685 v4i32_r = __msa_sat_s_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.sat.s.w(
686 v2i64_r = __msa_sat_s_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.sat.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]687
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]688 v16i8_r = __msa_sat_u_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.sat.u.b(
689 v8i16_r = __msa_sat_u_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.sat.u.h(
690 v4i32_r = __msa_sat_u_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.sat.u.w(
691 v2i64_r = __msa_sat_u_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.sat.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]692
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]693 v16i8_r = __msa_shf_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.shf.b(
694 v8i16_r = __msa_shf_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.shf.h(
695 v4i32_r = __msa_shf_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.shf.w(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]696
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]697 v16i8_r = __msa_sld_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8> @llvm.mips.sld.b(
698 v8i16_r = __msa_sld_h(v8i16_r, v8i16_a, 5); // CHECK: call <8 x i16> @llvm.mips.sld.h(
699 v4i32_r = __msa_sld_w(v4i32_r, v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.sld.w(
700 v2i64_r = __msa_sld_d(v2i64_r, v2i64_a, 1); // CHECK: call <2 x i64> @llvm.mips.sld.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]701
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]702 v16i8_r = __msa_sldi_b(v16i8_r, v16i8_a, 7); // CHECK: call <16 x i8> @llvm.mips.sldi.b(
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]703 v8i16_r = __msa_sldi_h(v8i16_r, v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.sldi.h(
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]704 v4i32_r = __msa_sldi_w(v4i32_r, v4i32_a, 2); // CHECK: call <4 x i32> @llvm.mips.sldi.w(
705 v2i64_r = __msa_sldi_d(v2i64_r, v2i64_a, 1); // CHECK: call <2 x i64> @llvm.mips.sldi.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]706
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]707 v16i8_r = __msa_sll_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.sll.b(
708 v8i16_r = __msa_sll_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.sll.h(
709 v4i32_r = __msa_sll_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.sll.w(
710 v2i64_r = __msa_sll_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.sll.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]711
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]712 v16i8_r = __msa_slli_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.slli.b(
713 v8i16_r = __msa_slli_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.slli.h(
714 v4i32_r = __msa_slli_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.slli.w(
715 v2i64_r = __msa_slli_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.slli.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]716
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]717 v16i8_r = __msa_splat_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.splat.b(
718 v8i16_r = __msa_splat_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.splat.h(
719 v4i32_r = __msa_splat_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.splat.w(
720 v2i64_r = __msa_splat_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.splat.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]721
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]722 v16i8_r = __msa_splati_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.splati.b(
723 v8i16_r = __msa_splati_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.splati.h(
724 v4i32_r = __msa_splati_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.splati.w(
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]725 v2i64_r = __msa_splati_d(v2i64_a, 1); // CHECK: call <2 x i64> @llvm.mips.splati.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]726
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]727 v16i8_r = __msa_sra_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.sra.b(
728 v8i16_r = __msa_sra_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.sra.h(
729 v4i32_r = __msa_sra_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.sra.w(
730 v2i64_r = __msa_sra_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.sra.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]731
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]732 v16i8_r = __msa_srai_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.srai.b(
733 v8i16_r = __msa_srai_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.srai.h(
734 v4i32_r = __msa_srai_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.srai.w(
735 v2i64_r = __msa_srai_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.srai.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]736
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]737 v16i8_r = __msa_srar_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.srar.b(
738 v8i16_r = __msa_srar_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.srar.h(
739 v4i32_r = __msa_srar_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.srar.w(
740 v2i64_r = __msa_srar_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.srar.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]741
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]742 v16i8_r = __msa_srari_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.srari.b(
743 v8i16_r = __msa_srari_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.srari.h(
744 v4i32_r = __msa_srari_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.srari.w(
745 v2i64_r = __msa_srari_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.srari.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]746
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]747 v16i8_r = __msa_srl_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.srl.b(
748 v8i16_r = __msa_srl_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.srl.h(
749 v4i32_r = __msa_srl_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.srl.w(
750 v2i64_r = __msa_srl_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.srl.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]751
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]752 v16i8_r = __msa_srli_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.srli.b(
753 v8i16_r = __msa_srli_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.srli.h(
754 v4i32_r = __msa_srli_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.srli.w(
755 v2i64_r = __msa_srli_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.srli.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]756
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]757 v16i8_r = __msa_srlr_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.srlr.b(
758 v8i16_r = __msa_srlr_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.srlr.h(
759 v4i32_r = __msa_srlr_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.srlr.w(
760 v2i64_r = __msa_srlr_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.srlr.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]761
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]762 v16i8_r = __msa_srlri_b(v16i8_a, 3); // CHECK: call <16 x i8> @llvm.mips.srlri.b(
763 v8i16_r = __msa_srlri_h(v8i16_a, 3); // CHECK: call <8 x i16> @llvm.mips.srlri.h(
764 v4i32_r = __msa_srlri_w(v4i32_a, 3); // CHECK: call <4 x i32> @llvm.mips.srlri.w(
765 v2i64_r = __msa_srlri_d(v2i64_a, 3); // CHECK: call <2 x i64> @llvm.mips.srlri.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]766
Simon Dardis1f90f2d2016-10-19 17:50:52 +0000[diff] [blame]767 __msa_st_b(v16i8_b, &v16i8_a, 16); // CHECK: call void @llvm.mips.st.b(
768 __msa_st_h(v8i16_b, &v8i16_a, 32); // CHECK: call void @llvm.mips.st.h(
769 __msa_st_w(v4i32_b, &v4i32_a, 48); // CHECK: call void @llvm.mips.st.w(
770 __msa_st_d(v2i64_b, &v2i64_a, 96); // CHECK: call void @llvm.mips.st.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]771
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]772 v16i8_r = __msa_subs_s_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.subs.s.b(
773 v8i16_r = __msa_subs_s_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.subs.s.h(
774 v4i32_r = __msa_subs_s_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.subs.s.w(
775 v2i64_r = __msa_subs_s_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.subs.s.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]776
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]777 v16u8_r = __msa_subs_u_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.subs.u.b(
778 v8u16_r = __msa_subs_u_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.subs.u.h(
779 v4u32_r = __msa_subs_u_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.subs.u.w(
780 v2u64_r = __msa_subs_u_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.subs.u.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]781
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]782 v16u8_r = __msa_subsus_u_b(v16u8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.subsus.u.b(
783 v8u16_r = __msa_subsus_u_h(v8u16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.subsus.u.h(
784 v4u32_r = __msa_subsus_u_w(v4u32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.subsus.u.w(
785 v2u64_r = __msa_subsus_u_d(v2u64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.subsus.u.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]786
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]787 v16i8_r = __msa_subsuu_s_b(v16u8_a, v16u8_b); // CHECK: call <16 x i8> @llvm.mips.subsuu.s.b(
788 v8i16_r = __msa_subsuu_s_h(v8u16_a, v8u16_b); // CHECK: call <8 x i16> @llvm.mips.subsuu.s.h(
789 v4i32_r = __msa_subsuu_s_w(v4u32_a, v4u32_b); // CHECK: call <4 x i32> @llvm.mips.subsuu.s.w(
790 v2i64_r = __msa_subsuu_s_d(v2u64_a, v2u64_b); // CHECK: call <2 x i64> @llvm.mips.subsuu.s.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]791
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]792 v16i8_r = __msa_subv_b(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.subv.b(
793 v8i16_r = __msa_subv_h(v8i16_a, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.subv.h(
794 v4i32_r = __msa_subv_w(v4i32_a, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.subv.w(
795 v2i64_r = __msa_subv_d(v2i64_a, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.subv.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]796
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]797 v16i8_r = __msa_subvi_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.subvi.b(
798 v8i16_r = __msa_subvi_h(v8i16_a, 25); // CHECK: call <8 x i16> @llvm.mips.subvi.h(
799 v4i32_r = __msa_subvi_w(v4i32_a, 25); // CHECK: call <4 x i32> @llvm.mips.subvi.w(
800 v2i64_r = __msa_subvi_d(v2i64_a, 25); // CHECK: call <2 x i64> @llvm.mips.subvi.d(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]801
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]802 v16i8_r = __msa_vshf_b(v16i8_a, v16i8_b, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.vshf.b(
803 v8i16_r = __msa_vshf_h(v8i16_a, v8i16_b, v8i16_b); // CHECK: call <8 x i16> @llvm.mips.vshf.h(
804 v4i32_r = __msa_vshf_w(v4i32_a, v4i32_b, v4i32_b); // CHECK: call <4 x i32> @llvm.mips.vshf.w(
805 v2i64_r = __msa_vshf_d(v2i64_a, v2i64_b, v2i64_b); // CHECK: call <2 x i64> @llvm.mips.vshf.d(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]806
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]807 v16i8_r = __msa_xor_v(v16i8_a, v16i8_b); // CHECK: call <16 x i8> @llvm.mips.xor.v(
808 v8i16_r = __msa_xor_v(v8i16_a, v8i16_b); // CHECK: call <16 x i8> @llvm.mips.xor.v(
809 v4i32_r = __msa_xor_v(v4i32_a, v4i32_b); // CHECK: call <16 x i8> @llvm.mips.xor.v(
810 v2i64_r = __msa_xor_v(v2i64_a, v2i64_b); // CHECK: call <16 x i8> @llvm.mips.xor.v(
Daniel Sandersc835a9f2013-10-17 13:57:25 +0000[diff] [blame]811
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]812 v16i8_r = __msa_xori_b(v16i8_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
813 v8i16_r = __msa_xori_b(v8i16_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
814 v4i32_r = __msa_xori_b(v4i32_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
815 v2i64_r = __msa_xori_b(v2i64_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]816
Simon Dardis3d9c7632016-09-20 15:07:36 +0000[diff] [blame]817 v16u8_r = __msa_xori_b(v16u8_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
818 v8u16_r = __msa_xori_b(v8u16_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
819 v4u32_r = __msa_xori_b(v4u32_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
820 v2u64_r = __msa_xori_b(v2u64_a, 25); // CHECK: call <16 x i8> @llvm.mips.xori.b(
Jack Carter77dce2f2013-08-15 14:47:02 +0000[diff] [blame]821
822}