Bill Wendling | a5c536e | 2013-08-01 21:42:05 +0000 | [diff] [blame^] | 1 | ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=NO-REALIGN |
| 2 | ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=REALIGN |
Manman Ren | f563941 | 2012-12-04 00:52:33 +0000 | [diff] [blame] | 3 | |
| 4 | ; rdar://12713765 |
| 5 | ; When realign-stack is set to false, make sure we are not creating stack |
| 6 | ; objects that are assumed to be 64-byte aligned. |
| 7 | @T3_retval = common global <16 x float> zeroinitializer, align 16 |
| 8 | |
Bill Wendling | a5c536e | 2013-08-01 21:42:05 +0000 | [diff] [blame^] | 9 | define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" { |
Manman Ren | f563941 | 2012-12-04 00:52:33 +0000 | [diff] [blame] | 10 | entry: |
Bill Wendling | a5c536e | 2013-08-01 21:42:05 +0000 | [diff] [blame^] | 11 | ; NO-REALIGN: test1 |
Manman Ren | f563941 | 2012-12-04 00:52:33 +0000 | [diff] [blame] | 12 | ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 |
| 13 | ; NO-REALIGN: vst1.64 |
| 14 | ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 |
| 15 | ; NO-REALIGN: vst1.64 |
| 16 | ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 |
| 17 | ; NO-REALIGN: vst1.64 |
| 18 | ; NO-REALIGN: vst1.64 |
| 19 | ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 |
| 20 | ; NO-REALIGN: vst1.64 |
| 21 | ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 |
| 22 | ; NO-REALIGN: vst1.64 |
| 23 | ; NO-REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 |
| 24 | ; NO-REALIGN: vst1.64 |
| 25 | ; NO-REALIGN: vst1.64 |
Bob Wilson | 67bbf3a | 2013-02-08 20:35:15 +0000 | [diff] [blame] | 26 | %retval = alloca <16 x float>, align 16 |
Manman Ren | f563941 | 2012-12-04 00:52:33 +0000 | [diff] [blame] | 27 | %0 = load <16 x float>* @T3_retval, align 16 |
| 28 | store <16 x float> %0, <16 x float>* %retval |
| 29 | %1 = load <16 x float>* %retval |
| 30 | store <16 x float> %1, <16 x float>* %agg.result, align 16 |
| 31 | ret void |
| 32 | } |
Bill Wendling | a5c536e | 2013-08-01 21:42:05 +0000 | [diff] [blame^] | 33 | |
| 34 | define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp { |
| 35 | entry: |
| 36 | ; REALIGN: test2 |
| 37 | ; REALIGN: bic sp, sp, #63 |
| 38 | ; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 |
| 39 | ; REALIGN: vst1.64 |
| 40 | ; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 |
| 41 | ; REALIGN: vst1.64 |
| 42 | ; REALIGN: orr [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 |
| 43 | ; REALIGN: vst1.64 |
| 44 | ; REALIGN: vst1.64 |
| 45 | ; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #48 |
| 46 | ; REALIGN: vst1.64 |
| 47 | ; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #32 |
| 48 | ; REALIGN: vst1.64 |
| 49 | ; REALIGN: add [[R2:r[0-9]+]], [[R1:r[0-9]+]], #16 |
| 50 | ; REALIGN: vst1.64 |
| 51 | ; REALIGN: vst1.64 |
| 52 | %retval = alloca <16 x float>, align 16 |
| 53 | %0 = load <16 x float>* @T3_retval, align 16 |
| 54 | store <16 x float> %0, <16 x float>* %retval |
| 55 | %1 = load <16 x float>* %retval |
| 56 | store <16 x float> %1, <16 x float>* %agg.result, align 16 |
| 57 | ret void |
| 58 | } |