| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 1 | //===-- VOPCInstructions.td - Vector Instruction Defintions ---------------===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | |
| 10 | //===----------------------------------------------------------------------===// |
| 11 | // Encodings |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | class VOPCe <bits<8> op> : Enc32 { |
| 15 | bits<9> src0; |
| 16 | bits<8> src1; |
| 17 | |
| 18 | let Inst{8-0} = src0; |
| 19 | let Inst{16-9} = src1; |
| 20 | let Inst{24-17} = op; |
| 21 | let Inst{31-25} = 0x3e; |
| 22 | } |
| 23 | |
| 24 | //===----------------------------------------------------------------------===// |
| 25 | // VOPC classes |
| 26 | //===----------------------------------------------------------------------===// |
| 27 | |
| 28 | // VOPC instructions are a special case because for the 32-bit |
| 29 | // encoding, we want to display the implicit vcc write as if it were |
| 30 | // an explicit $dst. |
| 31 | class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt0> : |
| 32 | VOPProfile <[i1, vt0, vt1, untyped]> { |
| 33 | let Asm32 = "vcc, $src0, $src1"; |
| 34 | // The destination for 32-bit encoding is implicit. |
| 35 | let HasDst32 = 0; |
| 36 | let Outs64 = (outs VOPDstS64:$sdst); |
| 37 | list<SchedReadWrite> Schedule = sched; |
| 38 | } |
| 39 | |
| 40 | class VOPC_Pseudo <string opName, VOPC_Profile P, list<dag> pattern=[]> : |
| 41 | InstSI<(outs), P.Ins32, "", pattern>, |
| 42 | VOP <opName>, |
| 43 | SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> { |
| 44 | |
| 45 | let isPseudo = 1; |
| 46 | let isCodeGenOnly = 1; |
| 47 | let UseNamedOperandTable = 1; |
| 48 | |
| 49 | string Mnemonic = opName; |
| 50 | string AsmOperands = P.Asm32; |
| 51 | |
| 52 | let Size = 4; |
| 53 | let mayLoad = 0; |
| 54 | let mayStore = 0; |
| 55 | let hasSideEffects = 0; |
| 56 | |
| 57 | let VALU = 1; |
| 58 | let VOPC = 1; |
| 59 | let Uses = [EXEC]; |
| 60 | let Defs = [VCC]; |
| 61 | |
| 62 | let SubtargetPredicate = isGCN; |
| 63 | |
| 64 | VOPProfile Pfl = P; |
| 65 | } |
| 66 | |
| 67 | class VOPC_Real <VOPC_Pseudo ps, int EncodingFamily> : |
| 68 | InstSI <ps.OutOperandList, ps.InOperandList, ps.PseudoInstr # " " # ps.AsmOperands, []>, |
| 69 | SIMCInstr <ps.PseudoInstr, EncodingFamily> { |
| 70 | |
| 71 | let isPseudo = 0; |
| 72 | let isCodeGenOnly = 0; |
| 73 | |
| Sam Kolton | a6792a3 | 2016-12-22 11:30:48 +0000 | [diff] [blame^] | 74 | let Constraints = ps.Constraints; |
| 75 | let DisableEncoding = ps.DisableEncoding; |
| 76 | |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 77 | // copy relevant pseudo op flags |
| 78 | let SubtargetPredicate = ps.SubtargetPredicate; |
| 79 | let AsmMatchConverter = ps.AsmMatchConverter; |
| 80 | let Constraints = ps.Constraints; |
| 81 | let DisableEncoding = ps.DisableEncoding; |
| 82 | let TSFlags = ps.TSFlags; |
| 83 | } |
| 84 | |
| 85 | // This class is used only with VOPC instructions. Use $sdst for out operand |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 86 | class VOPCInstAlias <VOP3_Pseudo ps, Instruction inst, VOPProfile p = ps.Pfl> : |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 87 | InstAlias <ps.OpName#" "#p.Asm32, (inst)>, PredicateControl { |
| 88 | |
| 89 | field bit isCompare; |
| 90 | field bit isCommutable; |
| 91 | |
| 92 | let ResultInst = |
| 93 | !if (p.HasDst32, |
| 94 | !if (!eq(p.NumSrcArgs, 0), |
| 95 | // 1 dst, 0 src |
| 96 | (inst p.DstRC:$sdst), |
| 97 | !if (!eq(p.NumSrcArgs, 1), |
| 98 | // 1 dst, 1 src |
| 99 | (inst p.DstRC:$sdst, p.Src0RC32:$src0), |
| 100 | !if (!eq(p.NumSrcArgs, 2), |
| 101 | // 1 dst, 2 src |
| 102 | (inst p.DstRC:$sdst, p.Src0RC32:$src0, p.Src1RC32:$src1), |
| 103 | // else - unreachable |
| 104 | (inst)))), |
| 105 | // else |
| 106 | !if (!eq(p.NumSrcArgs, 2), |
| 107 | // 0 dst, 2 src |
| 108 | (inst p.Src0RC32:$src0, p.Src1RC32:$src1), |
| 109 | !if (!eq(p.NumSrcArgs, 1), |
| 110 | // 0 dst, 1 src |
| 111 | (inst p.Src0RC32:$src1), |
| 112 | // else |
| 113 | // 0 dst, 0 src |
| 114 | (inst)))); |
| 115 | |
| 116 | let AsmVariantName = AMDGPUAsmVariants.Default; |
| 117 | let SubtargetPredicate = AssemblerPredicate; |
| 118 | } |
| 119 | |
| 120 | multiclass VOPC_Pseudos <string opName, |
| 121 | VOPC_Profile P, |
| 122 | PatLeaf cond = COND_NULL, |
| 123 | string revOp = opName, |
| 124 | bit DefExec = 0> { |
| 125 | |
| 126 | def _e32 : VOPC_Pseudo <opName, P>, |
| 127 | Commutable_REV<revOp#"_e32", !eq(revOp, opName)> { |
| 128 | let Defs = !if(DefExec, [VCC, EXEC], [VCC]); |
| 129 | let SchedRW = P.Schedule; |
| 130 | let isConvergent = DefExec; |
| 131 | let isCompare = 1; |
| 132 | let isCommutable = 1; |
| 133 | } |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 134 | def _e64 : VOP3_Pseudo<opName, P, |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 135 | !if(P.HasModifiers, |
| 136 | [(set i1:$sdst, |
| 137 | (setcc (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, |
| 138 | i1:$clamp, i32:$omod)), |
| 139 | (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)), |
| 140 | cond))], |
| 141 | [(set i1:$sdst, (setcc P.Src0VT:$src0, P.Src1VT:$src1, cond))])>, |
| 142 | Commutable_REV<revOp#"_e64", !eq(revOp, opName)> { |
| 143 | let Defs = !if(DefExec, [EXEC], []); |
| 144 | let SchedRW = P.Schedule; |
| 145 | let isCompare = 1; |
| 146 | let isCommutable = 1; |
| 147 | } |
| 148 | } |
| 149 | |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 150 | def VOPC_I1_F16_F16 : VOPC_Profile<[Write32Bit], f16>; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 151 | def VOPC_I1_F32_F32 : VOPC_Profile<[Write32Bit], f32>; |
| 152 | def VOPC_I1_F64_F64 : VOPC_Profile<[WriteDoubleAdd], f64>; |
| 153 | def VOPC_I1_I32_I32 : VOPC_Profile<[Write32Bit], i32>; |
| 154 | def VOPC_I1_I64_I64 : VOPC_Profile<[Write64Bit], i64>; |
| 155 | |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 156 | multiclass VOPC_F16 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 157 | VOPC_Pseudos <opName, VOPC_I1_F16_F16, cond, revOp, 0>; |
| 158 | |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 159 | multiclass VOPC_F32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 160 | VOPC_Pseudos <opName, VOPC_I1_F32_F32, cond, revOp, 0>; |
| 161 | |
| 162 | multiclass VOPC_F64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 163 | VOPC_Pseudos <opName, VOPC_I1_F64_F64, cond, revOp, 0>; |
| 164 | |
| 165 | multiclass VOPC_I32 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 166 | VOPC_Pseudos <opName, VOPC_I1_I32_I32, cond, revOp, 0>; |
| 167 | |
| 168 | multiclass VOPC_I64 <string opName, PatLeaf cond = COND_NULL, string revOp = opName> : |
| 169 | VOPC_Pseudos <opName, VOPC_I1_I64_I64, cond, revOp, 0>; |
| 170 | |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 171 | multiclass VOPCX_F16 <string opName, string revOp = opName> : |
| 172 | VOPC_Pseudos <opName, VOPC_I1_F16_F16, COND_NULL, revOp, 1>; |
| 173 | |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 174 | multiclass VOPCX_F32 <string opName, string revOp = opName> : |
| 175 | VOPC_Pseudos <opName, VOPC_I1_F32_F32, COND_NULL, revOp, 1>; |
| 176 | |
| 177 | multiclass VOPCX_F64 <string opName, string revOp = opName> : |
| 178 | VOPC_Pseudos <opName, VOPC_I1_F64_F64, COND_NULL, revOp, 1>; |
| 179 | |
| 180 | multiclass VOPCX_I32 <string opName, string revOp = opName> : |
| 181 | VOPC_Pseudos <opName, VOPC_I1_I32_I32, COND_NULL, revOp, 1>; |
| 182 | |
| 183 | multiclass VOPCX_I64 <string opName, string revOp = opName> : |
| 184 | VOPC_Pseudos <opName, VOPC_I1_I64_I64, COND_NULL, revOp, 1>; |
| 185 | |
| 186 | |
| 187 | //===----------------------------------------------------------------------===// |
| 188 | // Compare instructions |
| 189 | //===----------------------------------------------------------------------===// |
| 190 | |
| 191 | defm V_CMP_F_F32 : VOPC_F32 <"v_cmp_f_f32">; |
| 192 | defm V_CMP_LT_F32 : VOPC_F32 <"v_cmp_lt_f32", COND_OLT, "v_cmp_gt_f32">; |
| 193 | defm V_CMP_EQ_F32 : VOPC_F32 <"v_cmp_eq_f32", COND_OEQ>; |
| 194 | defm V_CMP_LE_F32 : VOPC_F32 <"v_cmp_le_f32", COND_OLE, "v_cmp_ge_f32">; |
| 195 | defm V_CMP_GT_F32 : VOPC_F32 <"v_cmp_gt_f32", COND_OGT>; |
| 196 | defm V_CMP_LG_F32 : VOPC_F32 <"v_cmp_lg_f32", COND_ONE>; |
| 197 | defm V_CMP_GE_F32 : VOPC_F32 <"v_cmp_ge_f32", COND_OGE>; |
| 198 | defm V_CMP_O_F32 : VOPC_F32 <"v_cmp_o_f32", COND_O>; |
| 199 | defm V_CMP_U_F32 : VOPC_F32 <"v_cmp_u_f32", COND_UO>; |
| 200 | defm V_CMP_NGE_F32 : VOPC_F32 <"v_cmp_nge_f32", COND_ULT, "v_cmp_nle_f32">; |
| 201 | defm V_CMP_NLG_F32 : VOPC_F32 <"v_cmp_nlg_f32", COND_UEQ>; |
| 202 | defm V_CMP_NGT_F32 : VOPC_F32 <"v_cmp_ngt_f32", COND_ULE, "v_cmp_nlt_f32">; |
| 203 | defm V_CMP_NLE_F32 : VOPC_F32 <"v_cmp_nle_f32", COND_UGT>; |
| 204 | defm V_CMP_NEQ_F32 : VOPC_F32 <"v_cmp_neq_f32", COND_UNE>; |
| 205 | defm V_CMP_NLT_F32 : VOPC_F32 <"v_cmp_nlt_f32", COND_UGE>; |
| 206 | defm V_CMP_TRU_F32 : VOPC_F32 <"v_cmp_tru_f32">; |
| 207 | |
| 208 | defm V_CMPX_F_F32 : VOPCX_F32 <"v_cmpx_f_f32">; |
| 209 | defm V_CMPX_LT_F32 : VOPCX_F32 <"v_cmpx_lt_f32", "v_cmpx_gt_f32">; |
| 210 | defm V_CMPX_EQ_F32 : VOPCX_F32 <"v_cmpx_eq_f32">; |
| 211 | defm V_CMPX_LE_F32 : VOPCX_F32 <"v_cmpx_le_f32", "v_cmpx_ge_f32">; |
| 212 | defm V_CMPX_GT_F32 : VOPCX_F32 <"v_cmpx_gt_f32">; |
| 213 | defm V_CMPX_LG_F32 : VOPCX_F32 <"v_cmpx_lg_f32">; |
| 214 | defm V_CMPX_GE_F32 : VOPCX_F32 <"v_cmpx_ge_f32">; |
| 215 | defm V_CMPX_O_F32 : VOPCX_F32 <"v_cmpx_o_f32">; |
| 216 | defm V_CMPX_U_F32 : VOPCX_F32 <"v_cmpx_u_f32">; |
| Matt Arsenault | 3de76b9 | 2016-12-22 04:39:41 +0000 | [diff] [blame] | 217 | defm V_CMPX_NGE_F32 : VOPCX_F32 <"v_cmpx_nge_f32", "v_cmpx_nle_f32">; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 218 | defm V_CMPX_NLG_F32 : VOPCX_F32 <"v_cmpx_nlg_f32">; |
| Matt Arsenault | 3de76b9 | 2016-12-22 04:39:41 +0000 | [diff] [blame] | 219 | defm V_CMPX_NGT_F32 : VOPCX_F32 <"v_cmpx_ngt_f32", "v_cmpx_nlt_f32">; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 220 | defm V_CMPX_NLE_F32 : VOPCX_F32 <"v_cmpx_nle_f32">; |
| 221 | defm V_CMPX_NEQ_F32 : VOPCX_F32 <"v_cmpx_neq_f32">; |
| 222 | defm V_CMPX_NLT_F32 : VOPCX_F32 <"v_cmpx_nlt_f32">; |
| 223 | defm V_CMPX_TRU_F32 : VOPCX_F32 <"v_cmpx_tru_f32">; |
| 224 | |
| 225 | defm V_CMP_F_F64 : VOPC_F64 <"v_cmp_f_f64">; |
| 226 | defm V_CMP_LT_F64 : VOPC_F64 <"v_cmp_lt_f64", COND_OLT, "v_cmp_gt_f64">; |
| 227 | defm V_CMP_EQ_F64 : VOPC_F64 <"v_cmp_eq_f64", COND_OEQ>; |
| 228 | defm V_CMP_LE_F64 : VOPC_F64 <"v_cmp_le_f64", COND_OLE, "v_cmp_ge_f64">; |
| 229 | defm V_CMP_GT_F64 : VOPC_F64 <"v_cmp_gt_f64", COND_OGT>; |
| 230 | defm V_CMP_LG_F64 : VOPC_F64 <"v_cmp_lg_f64", COND_ONE>; |
| 231 | defm V_CMP_GE_F64 : VOPC_F64 <"v_cmp_ge_f64", COND_OGE>; |
| 232 | defm V_CMP_O_F64 : VOPC_F64 <"v_cmp_o_f64", COND_O>; |
| 233 | defm V_CMP_U_F64 : VOPC_F64 <"v_cmp_u_f64", COND_UO>; |
| 234 | defm V_CMP_NGE_F64 : VOPC_F64 <"v_cmp_nge_f64", COND_ULT, "v_cmp_nle_f64">; |
| 235 | defm V_CMP_NLG_F64 : VOPC_F64 <"v_cmp_nlg_f64", COND_UEQ>; |
| 236 | defm V_CMP_NGT_F64 : VOPC_F64 <"v_cmp_ngt_f64", COND_ULE, "v_cmp_nlt_f64">; |
| 237 | defm V_CMP_NLE_F64 : VOPC_F64 <"v_cmp_nle_f64", COND_UGT>; |
| 238 | defm V_CMP_NEQ_F64 : VOPC_F64 <"v_cmp_neq_f64", COND_UNE>; |
| 239 | defm V_CMP_NLT_F64 : VOPC_F64 <"v_cmp_nlt_f64", COND_UGE>; |
| 240 | defm V_CMP_TRU_F64 : VOPC_F64 <"v_cmp_tru_f64">; |
| 241 | |
| 242 | defm V_CMPX_F_F64 : VOPCX_F64 <"v_cmpx_f_f64">; |
| 243 | defm V_CMPX_LT_F64 : VOPCX_F64 <"v_cmpx_lt_f64", "v_cmpx_gt_f64">; |
| 244 | defm V_CMPX_EQ_F64 : VOPCX_F64 <"v_cmpx_eq_f64">; |
| 245 | defm V_CMPX_LE_F64 : VOPCX_F64 <"v_cmpx_le_f64", "v_cmpx_ge_f64">; |
| 246 | defm V_CMPX_GT_F64 : VOPCX_F64 <"v_cmpx_gt_f64">; |
| 247 | defm V_CMPX_LG_F64 : VOPCX_F64 <"v_cmpx_lg_f64">; |
| 248 | defm V_CMPX_GE_F64 : VOPCX_F64 <"v_cmpx_ge_f64">; |
| 249 | defm V_CMPX_O_F64 : VOPCX_F64 <"v_cmpx_o_f64">; |
| 250 | defm V_CMPX_U_F64 : VOPCX_F64 <"v_cmpx_u_f64">; |
| 251 | defm V_CMPX_NGE_F64 : VOPCX_F64 <"v_cmpx_nge_f64", "v_cmpx_nle_f64">; |
| 252 | defm V_CMPX_NLG_F64 : VOPCX_F64 <"v_cmpx_nlg_f64">; |
| 253 | defm V_CMPX_NGT_F64 : VOPCX_F64 <"v_cmpx_ngt_f64", "v_cmpx_nlt_f64">; |
| 254 | defm V_CMPX_NLE_F64 : VOPCX_F64 <"v_cmpx_nle_f64">; |
| 255 | defm V_CMPX_NEQ_F64 : VOPCX_F64 <"v_cmpx_neq_f64">; |
| 256 | defm V_CMPX_NLT_F64 : VOPCX_F64 <"v_cmpx_nlt_f64">; |
| 257 | defm V_CMPX_TRU_F64 : VOPCX_F64 <"v_cmpx_tru_f64">; |
| 258 | |
| 259 | let SubtargetPredicate = isSICI in { |
| 260 | |
| 261 | defm V_CMPS_F_F32 : VOPC_F32 <"v_cmps_f_f32">; |
| 262 | defm V_CMPS_LT_F32 : VOPC_F32 <"v_cmps_lt_f32", COND_NULL, "v_cmps_gt_f32">; |
| 263 | defm V_CMPS_EQ_F32 : VOPC_F32 <"v_cmps_eq_f32">; |
| 264 | defm V_CMPS_LE_F32 : VOPC_F32 <"v_cmps_le_f32", COND_NULL, "v_cmps_ge_f32">; |
| 265 | defm V_CMPS_GT_F32 : VOPC_F32 <"v_cmps_gt_f32">; |
| 266 | defm V_CMPS_LG_F32 : VOPC_F32 <"v_cmps_lg_f32">; |
| 267 | defm V_CMPS_GE_F32 : VOPC_F32 <"v_cmps_ge_f32">; |
| 268 | defm V_CMPS_O_F32 : VOPC_F32 <"v_cmps_o_f32">; |
| 269 | defm V_CMPS_U_F32 : VOPC_F32 <"v_cmps_u_f32">; |
| 270 | defm V_CMPS_NGE_F32 : VOPC_F32 <"v_cmps_nge_f32", COND_NULL, "v_cmps_nle_f32">; |
| 271 | defm V_CMPS_NLG_F32 : VOPC_F32 <"v_cmps_nlg_f32">; |
| 272 | defm V_CMPS_NGT_F32 : VOPC_F32 <"v_cmps_ngt_f32", COND_NULL, "v_cmps_nlt_f32">; |
| 273 | defm V_CMPS_NLE_F32 : VOPC_F32 <"v_cmps_nle_f32">; |
| 274 | defm V_CMPS_NEQ_F32 : VOPC_F32 <"v_cmps_neq_f32">; |
| 275 | defm V_CMPS_NLT_F32 : VOPC_F32 <"v_cmps_nlt_f32">; |
| 276 | defm V_CMPS_TRU_F32 : VOPC_F32 <"v_cmps_tru_f32">; |
| 277 | |
| 278 | defm V_CMPSX_F_F32 : VOPCX_F32 <"v_cmpsx_f_f32">; |
| 279 | defm V_CMPSX_LT_F32 : VOPCX_F32 <"v_cmpsx_lt_f32", "v_cmpsx_gt_f32">; |
| 280 | defm V_CMPSX_EQ_F32 : VOPCX_F32 <"v_cmpsx_eq_f32">; |
| 281 | defm V_CMPSX_LE_F32 : VOPCX_F32 <"v_cmpsx_le_f32", "v_cmpsx_ge_f32">; |
| 282 | defm V_CMPSX_GT_F32 : VOPCX_F32 <"v_cmpsx_gt_f32">; |
| 283 | defm V_CMPSX_LG_F32 : VOPCX_F32 <"v_cmpsx_lg_f32">; |
| 284 | defm V_CMPSX_GE_F32 : VOPCX_F32 <"v_cmpsx_ge_f32">; |
| 285 | defm V_CMPSX_O_F32 : VOPCX_F32 <"v_cmpsx_o_f32">; |
| 286 | defm V_CMPSX_U_F32 : VOPCX_F32 <"v_cmpsx_u_f32">; |
| 287 | defm V_CMPSX_NGE_F32 : VOPCX_F32 <"v_cmpsx_nge_f32", "v_cmpsx_nle_f32">; |
| 288 | defm V_CMPSX_NLG_F32 : VOPCX_F32 <"v_cmpsx_nlg_f32">; |
| 289 | defm V_CMPSX_NGT_F32 : VOPCX_F32 <"v_cmpsx_ngt_f32", "v_cmpsx_nlt_f32">; |
| 290 | defm V_CMPSX_NLE_F32 : VOPCX_F32 <"v_cmpsx_nle_f32">; |
| 291 | defm V_CMPSX_NEQ_F32 : VOPCX_F32 <"v_cmpsx_neq_f32">; |
| 292 | defm V_CMPSX_NLT_F32 : VOPCX_F32 <"v_cmpsx_nlt_f32">; |
| 293 | defm V_CMPSX_TRU_F32 : VOPCX_F32 <"v_cmpsx_tru_f32">; |
| 294 | |
| 295 | defm V_CMPS_F_F64 : VOPC_F64 <"v_cmps_f_f64">; |
| 296 | defm V_CMPS_LT_F64 : VOPC_F64 <"v_cmps_lt_f64", COND_NULL, "v_cmps_gt_f64">; |
| 297 | defm V_CMPS_EQ_F64 : VOPC_F64 <"v_cmps_eq_f64">; |
| 298 | defm V_CMPS_LE_F64 : VOPC_F64 <"v_cmps_le_f64", COND_NULL, "v_cmps_ge_f64">; |
| 299 | defm V_CMPS_GT_F64 : VOPC_F64 <"v_cmps_gt_f64">; |
| 300 | defm V_CMPS_LG_F64 : VOPC_F64 <"v_cmps_lg_f64">; |
| 301 | defm V_CMPS_GE_F64 : VOPC_F64 <"v_cmps_ge_f64">; |
| 302 | defm V_CMPS_O_F64 : VOPC_F64 <"v_cmps_o_f64">; |
| 303 | defm V_CMPS_U_F64 : VOPC_F64 <"v_cmps_u_f64">; |
| 304 | defm V_CMPS_NGE_F64 : VOPC_F64 <"v_cmps_nge_f64", COND_NULL, "v_cmps_nle_f64">; |
| 305 | defm V_CMPS_NLG_F64 : VOPC_F64 <"v_cmps_nlg_f64">; |
| 306 | defm V_CMPS_NGT_F64 : VOPC_F64 <"v_cmps_ngt_f64", COND_NULL, "v_cmps_nlt_f64">; |
| 307 | defm V_CMPS_NLE_F64 : VOPC_F64 <"v_cmps_nle_f64">; |
| 308 | defm V_CMPS_NEQ_F64 : VOPC_F64 <"v_cmps_neq_f64">; |
| 309 | defm V_CMPS_NLT_F64 : VOPC_F64 <"v_cmps_nlt_f64">; |
| 310 | defm V_CMPS_TRU_F64 : VOPC_F64 <"v_cmps_tru_f64">; |
| 311 | |
| 312 | defm V_CMPSX_F_F64 : VOPCX_F64 <"v_cmpsx_f_f64">; |
| 313 | defm V_CMPSX_LT_F64 : VOPCX_F64 <"v_cmpsx_lt_f64", "v_cmpsx_gt_f64">; |
| 314 | defm V_CMPSX_EQ_F64 : VOPCX_F64 <"v_cmpsx_eq_f64">; |
| 315 | defm V_CMPSX_LE_F64 : VOPCX_F64 <"v_cmpsx_le_f64", "v_cmpsx_ge_f64">; |
| 316 | defm V_CMPSX_GT_F64 : VOPCX_F64 <"v_cmpsx_gt_f64">; |
| 317 | defm V_CMPSX_LG_F64 : VOPCX_F64 <"v_cmpsx_lg_f64">; |
| 318 | defm V_CMPSX_GE_F64 : VOPCX_F64 <"v_cmpsx_ge_f64">; |
| 319 | defm V_CMPSX_O_F64 : VOPCX_F64 <"v_cmpsx_o_f64">; |
| 320 | defm V_CMPSX_U_F64 : VOPCX_F64 <"v_cmpsx_u_f64">; |
| 321 | defm V_CMPSX_NGE_F64 : VOPCX_F64 <"v_cmpsx_nge_f64", "v_cmpsx_nle_f64">; |
| 322 | defm V_CMPSX_NLG_F64 : VOPCX_F64 <"v_cmpsx_nlg_f64">; |
| 323 | defm V_CMPSX_NGT_F64 : VOPCX_F64 <"v_cmpsx_ngt_f64", "v_cmpsx_nlt_f64">; |
| 324 | defm V_CMPSX_NLE_F64 : VOPCX_F64 <"v_cmpsx_nle_f64">; |
| 325 | defm V_CMPSX_NEQ_F64 : VOPCX_F64 <"v_cmpsx_neq_f64">; |
| 326 | defm V_CMPSX_NLT_F64 : VOPCX_F64 <"v_cmpsx_nlt_f64">; |
| 327 | defm V_CMPSX_TRU_F64 : VOPCX_F64 <"v_cmpsx_tru_f64">; |
| 328 | |
| 329 | } // End SubtargetPredicate = isSICI |
| 330 | |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 331 | let SubtargetPredicate = isVI in { |
| 332 | |
| 333 | defm V_CMP_F_F16 : VOPC_F16 <"v_cmp_f_f16">; |
| 334 | defm V_CMP_LT_F16 : VOPC_F16 <"v_cmp_lt_f16", COND_OLT, "v_cmp_gt_f16">; |
| 335 | defm V_CMP_EQ_F16 : VOPC_F16 <"v_cmp_eq_f16", COND_OEQ>; |
| 336 | defm V_CMP_LE_F16 : VOPC_F16 <"v_cmp_le_f16", COND_OLE, "v_cmp_ge_f16">; |
| 337 | defm V_CMP_GT_F16 : VOPC_F16 <"v_cmp_gt_f16", COND_OGT>; |
| 338 | defm V_CMP_LG_F16 : VOPC_F16 <"v_cmp_lg_f16", COND_ONE>; |
| 339 | defm V_CMP_GE_F16 : VOPC_F16 <"v_cmp_ge_f16", COND_OGE>; |
| 340 | defm V_CMP_O_F16 : VOPC_F16 <"v_cmp_o_f16", COND_O>; |
| 341 | defm V_CMP_U_F16 : VOPC_F16 <"v_cmp_u_f16", COND_UO>; |
| 342 | defm V_CMP_NGE_F16 : VOPC_F16 <"v_cmp_nge_f16", COND_ULT, "v_cmp_nle_f16">; |
| 343 | defm V_CMP_NLG_F16 : VOPC_F16 <"v_cmp_nlg_f16", COND_UEQ>; |
| 344 | defm V_CMP_NGT_F16 : VOPC_F16 <"v_cmp_ngt_f16", COND_ULE, "v_cmp_nlt_f16">; |
| 345 | defm V_CMP_NLE_F16 : VOPC_F16 <"v_cmp_nle_f16", COND_UGT>; |
| 346 | defm V_CMP_NEQ_F16 : VOPC_F16 <"v_cmp_neq_f16", COND_UNE>; |
| 347 | defm V_CMP_NLT_F16 : VOPC_F16 <"v_cmp_nlt_f16", COND_UGE>; |
| 348 | defm V_CMP_TRU_F16 : VOPC_F16 <"v_cmp_tru_f16">; |
| 349 | |
| 350 | defm V_CMPX_F_F16 : VOPCX_F16 <"v_cmpx_f_f16">; |
| 351 | defm V_CMPX_LT_F16 : VOPCX_F16 <"v_cmpx_lt_f16", "v_cmpx_gt_f16">; |
| 352 | defm V_CMPX_EQ_F16 : VOPCX_F16 <"v_cmpx_eq_f16">; |
| 353 | defm V_CMPX_LE_F16 : VOPCX_F16 <"v_cmpx_le_f16", "v_cmpx_ge_f16">; |
| 354 | defm V_CMPX_GT_F16 : VOPCX_F16 <"v_cmpx_gt_f16">; |
| 355 | defm V_CMPX_LG_F16 : VOPCX_F16 <"v_cmpx_lg_f16">; |
| 356 | defm V_CMPX_GE_F16 : VOPCX_F16 <"v_cmpx_ge_f16">; |
| 357 | defm V_CMPX_O_F16 : VOPCX_F16 <"v_cmpx_o_f16">; |
| 358 | defm V_CMPX_U_F16 : VOPCX_F16 <"v_cmpx_u_f16">; |
| Matt Arsenault | 3de76b9 | 2016-12-22 04:39:41 +0000 | [diff] [blame] | 359 | defm V_CMPX_NGE_F16 : VOPCX_F16 <"v_cmpx_nge_f16", "v_cmpx_nle_f16">; |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 360 | defm V_CMPX_NLG_F16 : VOPCX_F16 <"v_cmpx_nlg_f16">; |
| Matt Arsenault | 3de76b9 | 2016-12-22 04:39:41 +0000 | [diff] [blame] | 361 | defm V_CMPX_NGT_F16 : VOPCX_F16 <"v_cmpx_ngt_f16", "v_cmpx_nlt_f16">; |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 362 | defm V_CMPX_NLE_F16 : VOPCX_F16 <"v_cmpx_nle_f16">; |
| 363 | defm V_CMPX_NEQ_F16 : VOPCX_F16 <"v_cmpx_neq_f16">; |
| 364 | defm V_CMPX_NLT_F16 : VOPCX_F16 <"v_cmpx_nlt_f16">; |
| 365 | defm V_CMPX_TRU_F16 : VOPCX_F16 <"v_cmpx_tru_f16">; |
| 366 | |
| 367 | } // End SubtargetPredicate = isVI |
| 368 | |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 369 | defm V_CMP_F_I32 : VOPC_I32 <"v_cmp_f_i32">; |
| 370 | defm V_CMP_LT_I32 : VOPC_I32 <"v_cmp_lt_i32", COND_SLT, "v_cmp_gt_i32">; |
| Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 371 | defm V_CMP_EQ_I32 : VOPC_I32 <"v_cmp_eq_i32">; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 372 | defm V_CMP_LE_I32 : VOPC_I32 <"v_cmp_le_i32", COND_SLE, "v_cmp_ge_i32">; |
| 373 | defm V_CMP_GT_I32 : VOPC_I32 <"v_cmp_gt_i32", COND_SGT>; |
| Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 374 | defm V_CMP_NE_I32 : VOPC_I32 <"v_cmp_ne_i32">; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 375 | defm V_CMP_GE_I32 : VOPC_I32 <"v_cmp_ge_i32", COND_SGE>; |
| 376 | defm V_CMP_T_I32 : VOPC_I32 <"v_cmp_t_i32">; |
| 377 | |
| 378 | defm V_CMPX_F_I32 : VOPCX_I32 <"v_cmpx_f_i32">; |
| 379 | defm V_CMPX_LT_I32 : VOPCX_I32 <"v_cmpx_lt_i32", "v_cmpx_gt_i32">; |
| 380 | defm V_CMPX_EQ_I32 : VOPCX_I32 <"v_cmpx_eq_i32">; |
| 381 | defm V_CMPX_LE_I32 : VOPCX_I32 <"v_cmpx_le_i32", "v_cmpx_ge_i32">; |
| 382 | defm V_CMPX_GT_I32 : VOPCX_I32 <"v_cmpx_gt_i32">; |
| 383 | defm V_CMPX_NE_I32 : VOPCX_I32 <"v_cmpx_ne_i32">; |
| 384 | defm V_CMPX_GE_I32 : VOPCX_I32 <"v_cmpx_ge_i32">; |
| 385 | defm V_CMPX_T_I32 : VOPCX_I32 <"v_cmpx_t_i32">; |
| 386 | |
| 387 | defm V_CMP_F_I64 : VOPC_I64 <"v_cmp_f_i64">; |
| 388 | defm V_CMP_LT_I64 : VOPC_I64 <"v_cmp_lt_i64", COND_SLT, "v_cmp_gt_i64">; |
| Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 389 | defm V_CMP_EQ_I64 : VOPC_I64 <"v_cmp_eq_i64">; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 390 | defm V_CMP_LE_I64 : VOPC_I64 <"v_cmp_le_i64", COND_SLE, "v_cmp_ge_i64">; |
| 391 | defm V_CMP_GT_I64 : VOPC_I64 <"v_cmp_gt_i64", COND_SGT>; |
| Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 392 | defm V_CMP_NE_I64 : VOPC_I64 <"v_cmp_ne_i64">; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 393 | defm V_CMP_GE_I64 : VOPC_I64 <"v_cmp_ge_i64", COND_SGE>; |
| 394 | defm V_CMP_T_I64 : VOPC_I64 <"v_cmp_t_i64">; |
| 395 | |
| 396 | defm V_CMPX_F_I64 : VOPCX_I64 <"v_cmpx_f_i64">; |
| 397 | defm V_CMPX_LT_I64 : VOPCX_I64 <"v_cmpx_lt_i64", "v_cmpx_gt_i64">; |
| 398 | defm V_CMPX_EQ_I64 : VOPCX_I64 <"v_cmpx_eq_i64">; |
| 399 | defm V_CMPX_LE_I64 : VOPCX_I64 <"v_cmpx_le_i64", "v_cmpx_ge_i64">; |
| 400 | defm V_CMPX_GT_I64 : VOPCX_I64 <"v_cmpx_gt_i64">; |
| 401 | defm V_CMPX_NE_I64 : VOPCX_I64 <"v_cmpx_ne_i64">; |
| 402 | defm V_CMPX_GE_I64 : VOPCX_I64 <"v_cmpx_ge_i64">; |
| 403 | defm V_CMPX_T_I64 : VOPCX_I64 <"v_cmpx_t_i64">; |
| 404 | |
| 405 | defm V_CMP_F_U32 : VOPC_I32 <"v_cmp_f_u32">; |
| 406 | defm V_CMP_LT_U32 : VOPC_I32 <"v_cmp_lt_u32", COND_ULT, "v_cmp_gt_u32">; |
| 407 | defm V_CMP_EQ_U32 : VOPC_I32 <"v_cmp_eq_u32", COND_EQ>; |
| 408 | defm V_CMP_LE_U32 : VOPC_I32 <"v_cmp_le_u32", COND_ULE, "v_cmp_ge_u32">; |
| 409 | defm V_CMP_GT_U32 : VOPC_I32 <"v_cmp_gt_u32", COND_UGT>; |
| 410 | defm V_CMP_NE_U32 : VOPC_I32 <"v_cmp_ne_u32", COND_NE>; |
| 411 | defm V_CMP_GE_U32 : VOPC_I32 <"v_cmp_ge_u32", COND_UGE>; |
| 412 | defm V_CMP_T_U32 : VOPC_I32 <"v_cmp_t_u32">; |
| 413 | |
| 414 | defm V_CMPX_F_U32 : VOPCX_I32 <"v_cmpx_f_u32">; |
| 415 | defm V_CMPX_LT_U32 : VOPCX_I32 <"v_cmpx_lt_u32", "v_cmpx_gt_u32">; |
| 416 | defm V_CMPX_EQ_U32 : VOPCX_I32 <"v_cmpx_eq_u32">; |
| 417 | defm V_CMPX_LE_U32 : VOPCX_I32 <"v_cmpx_le_u32", "v_cmpx_le_u32">; |
| 418 | defm V_CMPX_GT_U32 : VOPCX_I32 <"v_cmpx_gt_u32">; |
| 419 | defm V_CMPX_NE_U32 : VOPCX_I32 <"v_cmpx_ne_u32">; |
| 420 | defm V_CMPX_GE_U32 : VOPCX_I32 <"v_cmpx_ge_u32">; |
| 421 | defm V_CMPX_T_U32 : VOPCX_I32 <"v_cmpx_t_u32">; |
| 422 | |
| 423 | defm V_CMP_F_U64 : VOPC_I64 <"v_cmp_f_u64">; |
| 424 | defm V_CMP_LT_U64 : VOPC_I64 <"v_cmp_lt_u64", COND_ULT, "v_cmp_gt_u64">; |
| 425 | defm V_CMP_EQ_U64 : VOPC_I64 <"v_cmp_eq_u64", COND_EQ>; |
| 426 | defm V_CMP_LE_U64 : VOPC_I64 <"v_cmp_le_u64", COND_ULE, "v_cmp_ge_u64">; |
| 427 | defm V_CMP_GT_U64 : VOPC_I64 <"v_cmp_gt_u64", COND_UGT>; |
| 428 | defm V_CMP_NE_U64 : VOPC_I64 <"v_cmp_ne_u64", COND_NE>; |
| 429 | defm V_CMP_GE_U64 : VOPC_I64 <"v_cmp_ge_u64", COND_UGE>; |
| 430 | defm V_CMP_T_U64 : VOPC_I64 <"v_cmp_t_u64">; |
| 431 | |
| 432 | defm V_CMPX_F_U64 : VOPCX_I64 <"v_cmpx_f_u64">; |
| 433 | defm V_CMPX_LT_U64 : VOPCX_I64 <"v_cmpx_lt_u64", "v_cmpx_gt_u64">; |
| 434 | defm V_CMPX_EQ_U64 : VOPCX_I64 <"v_cmpx_eq_u64">; |
| 435 | defm V_CMPX_LE_U64 : VOPCX_I64 <"v_cmpx_le_u64", "v_cmpx_ge_u64">; |
| 436 | defm V_CMPX_GT_U64 : VOPCX_I64 <"v_cmpx_gt_u64">; |
| 437 | defm V_CMPX_NE_U64 : VOPCX_I64 <"v_cmpx_ne_u64">; |
| 438 | defm V_CMPX_GE_U64 : VOPCX_I64 <"v_cmpx_ge_u64">; |
| 439 | defm V_CMPX_T_U64 : VOPCX_I64 <"v_cmpx_t_u64">; |
| 440 | |
| 441 | //===----------------------------------------------------------------------===// |
| 442 | // Class instructions |
| 443 | //===----------------------------------------------------------------------===// |
| 444 | |
| 445 | class VOPC_Class_Profile<list<SchedReadWrite> sched, ValueType vt> : |
| 446 | VOPC_Profile<sched, vt, i32> { |
| 447 | let Ins64 = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, Src1RC64:$src1); |
| 448 | let Asm64 = "$sdst, $src0_modifiers, $src1"; |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 449 | let InsSDWA = (ins Src0Mod:$src0_modifiers, Src0RC64:$src0, |
| 450 | Int32InputMods:$src1_modifiers, Src1RC64:$src1, |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 451 | clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel); |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 452 | let AsmSDWA = " vcc, $src0_modifiers, $src1_modifiers$clamp $src0_sel $src1_sel"; |
| 453 | let HasSrc1Mods = 0; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 454 | let HasClamp = 0; |
| 455 | let HasOMod = 0; |
| 456 | } |
| 457 | |
| 458 | class getVOPCClassPat64 <VOPProfile P> { |
| 459 | list<dag> ret = |
| 460 | [(set i1:$sdst, |
| 461 | (AMDGPUfp_class |
| 462 | (P.Src0VT (VOP3Mods0Clamp0OMod P.Src0VT:$src0, i32:$src0_modifiers)), |
| 463 | P.Src1VT:$src1))]; |
| 464 | } |
| 465 | |
| 466 | // Special case for class instructions which only have modifiers on |
| 467 | // the 1st source operand. |
| 468 | multiclass VOPC_Class_Pseudos <string opName, VOPC_Profile p, bit DefExec> { |
| 469 | def _e32 : VOPC_Pseudo <opName, p> { |
| 470 | let Defs = !if(DefExec, [VCC, EXEC], [VCC]); |
| 471 | let SchedRW = p.Schedule; |
| 472 | let isConvergent = DefExec; |
| 473 | } |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 474 | def _e64 : VOP3_Pseudo<opName, p, getVOPCClassPat64<p>.ret> { |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 475 | let Defs = !if(DefExec, [EXEC], []); |
| 476 | let SchedRW = p.Schedule; |
| 477 | } |
| 478 | } |
| 479 | |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 480 | def VOPC_I1_F16_I32 : VOPC_Class_Profile<[Write32Bit], f16>; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 481 | def VOPC_I1_F32_I32 : VOPC_Class_Profile<[Write32Bit], f32>; |
| 482 | def VOPC_I1_F64_I32 : VOPC_Class_Profile<[WriteDoubleAdd], f64>; |
| 483 | |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 484 | multiclass VOPC_CLASS_F16 <string opName> : |
| 485 | VOPC_Class_Pseudos <opName, VOPC_I1_F16_I32, 0>; |
| 486 | |
| 487 | multiclass VOPCX_CLASS_F16 <string opName> : |
| 488 | VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 1>; |
| 489 | |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 490 | multiclass VOPC_CLASS_F32 <string opName> : |
| 491 | VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 0>; |
| 492 | |
| 493 | multiclass VOPCX_CLASS_F32 <string opName> : |
| 494 | VOPC_Class_Pseudos <opName, VOPC_I1_F32_I32, 1>; |
| 495 | |
| 496 | multiclass VOPC_CLASS_F64 <string opName> : |
| 497 | VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 0>; |
| 498 | |
| 499 | multiclass VOPCX_CLASS_F64 <string opName> : |
| 500 | VOPC_Class_Pseudos <opName, VOPC_I1_F64_I32, 1>; |
| 501 | |
| 502 | defm V_CMP_CLASS_F32 : VOPC_CLASS_F32 <"v_cmp_class_f32">; |
| 503 | defm V_CMPX_CLASS_F32 : VOPCX_CLASS_F32 <"v_cmpx_class_f32">; |
| 504 | defm V_CMP_CLASS_F64 : VOPC_CLASS_F64 <"v_cmp_class_f64">; |
| 505 | defm V_CMPX_CLASS_F64 : VOPCX_CLASS_F64 <"v_cmpx_class_f64">; |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 506 | defm V_CMP_CLASS_F16 : VOPC_CLASS_F16 <"v_cmp_class_f16">; |
| 507 | defm V_CMPX_CLASS_F16 : VOPCX_CLASS_F16 <"v_cmpx_class_f16">; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 508 | |
| 509 | //===----------------------------------------------------------------------===// |
| 510 | // V_ICMPIntrinsic Pattern. |
| 511 | //===----------------------------------------------------------------------===// |
| 512 | |
| 513 | let Predicates = [isGCN] in { |
| 514 | |
| 515 | class ICMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat < |
| 516 | (AMDGPUsetcc vt:$src0, vt:$src1, cond), |
| 517 | (inst $src0, $src1) |
| 518 | >; |
| 519 | |
| Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 520 | def : ICMP_Pattern <COND_EQ, V_CMP_EQ_U32_e64, i32>; |
| 521 | def : ICMP_Pattern <COND_NE, V_CMP_NE_U32_e64, i32>; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 522 | def : ICMP_Pattern <COND_UGT, V_CMP_GT_U32_e64, i32>; |
| 523 | def : ICMP_Pattern <COND_UGE, V_CMP_GE_U32_e64, i32>; |
| 524 | def : ICMP_Pattern <COND_ULT, V_CMP_LT_U32_e64, i32>; |
| 525 | def : ICMP_Pattern <COND_ULE, V_CMP_LE_U32_e64, i32>; |
| 526 | def : ICMP_Pattern <COND_SGT, V_CMP_GT_I32_e64, i32>; |
| 527 | def : ICMP_Pattern <COND_SGE, V_CMP_GE_I32_e64, i32>; |
| 528 | def : ICMP_Pattern <COND_SLT, V_CMP_LT_I32_e64, i32>; |
| 529 | def : ICMP_Pattern <COND_SLE, V_CMP_LE_I32_e64, i32>; |
| 530 | |
| Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 531 | def : ICMP_Pattern <COND_EQ, V_CMP_EQ_U64_e64, i64>; |
| 532 | def : ICMP_Pattern <COND_NE, V_CMP_NE_U64_e64, i64>; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 533 | def : ICMP_Pattern <COND_UGT, V_CMP_GT_U64_e64, i64>; |
| 534 | def : ICMP_Pattern <COND_UGE, V_CMP_GE_U64_e64, i64>; |
| 535 | def : ICMP_Pattern <COND_ULT, V_CMP_LT_U64_e64, i64>; |
| 536 | def : ICMP_Pattern <COND_ULE, V_CMP_LE_U64_e64, i64>; |
| 537 | def : ICMP_Pattern <COND_SGT, V_CMP_GT_I64_e64, i64>; |
| 538 | def : ICMP_Pattern <COND_SGE, V_CMP_GE_I64_e64, i64>; |
| 539 | def : ICMP_Pattern <COND_SLT, V_CMP_LT_I64_e64, i64>; |
| 540 | def : ICMP_Pattern <COND_SLE, V_CMP_LE_I64_e64, i64>; |
| 541 | |
| 542 | class FCMP_Pattern <PatLeaf cond, Instruction inst, ValueType vt> : Pat < |
| 543 | (i64 (AMDGPUsetcc (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)), |
| 544 | (vt (VOP3Mods vt:$src1, i32:$src1_modifiers)), cond)), |
| 545 | (inst $src0_modifiers, $src0, $src1_modifiers, $src1, |
| 546 | DSTCLAMP.NONE, DSTOMOD.NONE) |
| 547 | >; |
| 548 | |
| 549 | def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F32_e64, f32>; |
| 550 | def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F32_e64, f32>; |
| 551 | def : FCMP_Pattern <COND_OGT, V_CMP_GT_F32_e64, f32>; |
| 552 | def : FCMP_Pattern <COND_OGE, V_CMP_GE_F32_e64, f32>; |
| 553 | def : FCMP_Pattern <COND_OLT, V_CMP_LT_F32_e64, f32>; |
| 554 | def : FCMP_Pattern <COND_OLE, V_CMP_LE_F32_e64, f32>; |
| 555 | |
| 556 | def : FCMP_Pattern <COND_OEQ, V_CMP_EQ_F64_e64, f64>; |
| 557 | def : FCMP_Pattern <COND_ONE, V_CMP_NEQ_F64_e64, f64>; |
| 558 | def : FCMP_Pattern <COND_OGT, V_CMP_GT_F64_e64, f64>; |
| 559 | def : FCMP_Pattern <COND_OGE, V_CMP_GE_F64_e64, f64>; |
| 560 | def : FCMP_Pattern <COND_OLT, V_CMP_LT_F64_e64, f64>; |
| 561 | def : FCMP_Pattern <COND_OLE, V_CMP_LE_F64_e64, f64>; |
| 562 | |
| 563 | def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F32_e64, f32>; |
| 564 | def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F32_e64, f32>; |
| 565 | def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F32_e64, f32>; |
| 566 | def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F32_e64, f32>; |
| 567 | def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F32_e64, f32>; |
| 568 | def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F32_e64, f32>; |
| 569 | |
| 570 | def : FCMP_Pattern <COND_UEQ, V_CMP_NLG_F64_e64, f64>; |
| 571 | def : FCMP_Pattern <COND_UNE, V_CMP_NEQ_F64_e64, f64>; |
| 572 | def : FCMP_Pattern <COND_UGT, V_CMP_NLE_F64_e64, f64>; |
| 573 | def : FCMP_Pattern <COND_UGE, V_CMP_NLT_F64_e64, f64>; |
| 574 | def : FCMP_Pattern <COND_ULT, V_CMP_NGE_F64_e64, f64>; |
| 575 | def : FCMP_Pattern <COND_ULE, V_CMP_NGT_F64_e64, f64>; |
| 576 | |
| 577 | } // End Predicates = [isGCN] |
| 578 | |
| 579 | //===----------------------------------------------------------------------===// |
| 580 | // Target |
| 581 | //===----------------------------------------------------------------------===// |
| 582 | |
| 583 | //===----------------------------------------------------------------------===// |
| 584 | // SI |
| 585 | //===----------------------------------------------------------------------===// |
| 586 | |
| 587 | multiclass VOPC_Real_si <bits<9> op> { |
| 588 | let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in { |
| 589 | def _e32_si : |
| 590 | VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>, |
| 591 | VOPCe<op{7-0}>; |
| 592 | |
| 593 | def _e64_si : |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 594 | VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>, |
| 595 | VOP3a_si <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 596 | // Encoding used for VOPC instructions encoded as VOP3 |
| 597 | // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst |
| 598 | bits<8> sdst; |
| 599 | let Inst{7-0} = sdst; |
| 600 | } |
| 601 | } |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 602 | def : VOPCInstAlias <!cast<VOP3_Pseudo>(NAME#"_e64"), |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 603 | !cast<Instruction>(NAME#"_e32_si")> { |
| 604 | let AssemblerPredicate = isSICI; |
| 605 | } |
| 606 | } |
| 607 | |
| 608 | defm V_CMP_F_F32 : VOPC_Real_si <0x0>; |
| 609 | defm V_CMP_LT_F32 : VOPC_Real_si <0x1>; |
| 610 | defm V_CMP_EQ_F32 : VOPC_Real_si <0x2>; |
| 611 | defm V_CMP_LE_F32 : VOPC_Real_si <0x3>; |
| 612 | defm V_CMP_GT_F32 : VOPC_Real_si <0x4>; |
| 613 | defm V_CMP_LG_F32 : VOPC_Real_si <0x5>; |
| 614 | defm V_CMP_GE_F32 : VOPC_Real_si <0x6>; |
| 615 | defm V_CMP_O_F32 : VOPC_Real_si <0x7>; |
| 616 | defm V_CMP_U_F32 : VOPC_Real_si <0x8>; |
| 617 | defm V_CMP_NGE_F32 : VOPC_Real_si <0x9>; |
| 618 | defm V_CMP_NLG_F32 : VOPC_Real_si <0xa>; |
| 619 | defm V_CMP_NGT_F32 : VOPC_Real_si <0xb>; |
| 620 | defm V_CMP_NLE_F32 : VOPC_Real_si <0xc>; |
| 621 | defm V_CMP_NEQ_F32 : VOPC_Real_si <0xd>; |
| 622 | defm V_CMP_NLT_F32 : VOPC_Real_si <0xe>; |
| 623 | defm V_CMP_TRU_F32 : VOPC_Real_si <0xf>; |
| 624 | |
| 625 | defm V_CMPX_F_F32 : VOPC_Real_si <0x10>; |
| 626 | defm V_CMPX_LT_F32 : VOPC_Real_si <0x11>; |
| 627 | defm V_CMPX_EQ_F32 : VOPC_Real_si <0x12>; |
| 628 | defm V_CMPX_LE_F32 : VOPC_Real_si <0x13>; |
| 629 | defm V_CMPX_GT_F32 : VOPC_Real_si <0x14>; |
| 630 | defm V_CMPX_LG_F32 : VOPC_Real_si <0x15>; |
| 631 | defm V_CMPX_GE_F32 : VOPC_Real_si <0x16>; |
| 632 | defm V_CMPX_O_F32 : VOPC_Real_si <0x17>; |
| 633 | defm V_CMPX_U_F32 : VOPC_Real_si <0x18>; |
| 634 | defm V_CMPX_NGE_F32 : VOPC_Real_si <0x19>; |
| 635 | defm V_CMPX_NLG_F32 : VOPC_Real_si <0x1a>; |
| 636 | defm V_CMPX_NGT_F32 : VOPC_Real_si <0x1b>; |
| 637 | defm V_CMPX_NLE_F32 : VOPC_Real_si <0x1c>; |
| 638 | defm V_CMPX_NEQ_F32 : VOPC_Real_si <0x1d>; |
| 639 | defm V_CMPX_NLT_F32 : VOPC_Real_si <0x1e>; |
| 640 | defm V_CMPX_TRU_F32 : VOPC_Real_si <0x1f>; |
| 641 | |
| 642 | defm V_CMP_F_F64 : VOPC_Real_si <0x20>; |
| 643 | defm V_CMP_LT_F64 : VOPC_Real_si <0x21>; |
| 644 | defm V_CMP_EQ_F64 : VOPC_Real_si <0x22>; |
| 645 | defm V_CMP_LE_F64 : VOPC_Real_si <0x23>; |
| 646 | defm V_CMP_GT_F64 : VOPC_Real_si <0x24>; |
| 647 | defm V_CMP_LG_F64 : VOPC_Real_si <0x25>; |
| 648 | defm V_CMP_GE_F64 : VOPC_Real_si <0x26>; |
| 649 | defm V_CMP_O_F64 : VOPC_Real_si <0x27>; |
| 650 | defm V_CMP_U_F64 : VOPC_Real_si <0x28>; |
| 651 | defm V_CMP_NGE_F64 : VOPC_Real_si <0x29>; |
| 652 | defm V_CMP_NLG_F64 : VOPC_Real_si <0x2a>; |
| 653 | defm V_CMP_NGT_F64 : VOPC_Real_si <0x2b>; |
| 654 | defm V_CMP_NLE_F64 : VOPC_Real_si <0x2c>; |
| 655 | defm V_CMP_NEQ_F64 : VOPC_Real_si <0x2d>; |
| 656 | defm V_CMP_NLT_F64 : VOPC_Real_si <0x2e>; |
| 657 | defm V_CMP_TRU_F64 : VOPC_Real_si <0x2f>; |
| 658 | |
| 659 | defm V_CMPX_F_F64 : VOPC_Real_si <0x30>; |
| 660 | defm V_CMPX_LT_F64 : VOPC_Real_si <0x31>; |
| 661 | defm V_CMPX_EQ_F64 : VOPC_Real_si <0x32>; |
| 662 | defm V_CMPX_LE_F64 : VOPC_Real_si <0x33>; |
| 663 | defm V_CMPX_GT_F64 : VOPC_Real_si <0x34>; |
| 664 | defm V_CMPX_LG_F64 : VOPC_Real_si <0x35>; |
| 665 | defm V_CMPX_GE_F64 : VOPC_Real_si <0x36>; |
| 666 | defm V_CMPX_O_F64 : VOPC_Real_si <0x37>; |
| 667 | defm V_CMPX_U_F64 : VOPC_Real_si <0x38>; |
| 668 | defm V_CMPX_NGE_F64 : VOPC_Real_si <0x39>; |
| 669 | defm V_CMPX_NLG_F64 : VOPC_Real_si <0x3a>; |
| 670 | defm V_CMPX_NGT_F64 : VOPC_Real_si <0x3b>; |
| 671 | defm V_CMPX_NLE_F64 : VOPC_Real_si <0x3c>; |
| 672 | defm V_CMPX_NEQ_F64 : VOPC_Real_si <0x3d>; |
| 673 | defm V_CMPX_NLT_F64 : VOPC_Real_si <0x3e>; |
| 674 | defm V_CMPX_TRU_F64 : VOPC_Real_si <0x3f>; |
| 675 | |
| 676 | defm V_CMPS_F_F32 : VOPC_Real_si <0x40>; |
| 677 | defm V_CMPS_LT_F32 : VOPC_Real_si <0x41>; |
| 678 | defm V_CMPS_EQ_F32 : VOPC_Real_si <0x42>; |
| 679 | defm V_CMPS_LE_F32 : VOPC_Real_si <0x43>; |
| 680 | defm V_CMPS_GT_F32 : VOPC_Real_si <0x44>; |
| 681 | defm V_CMPS_LG_F32 : VOPC_Real_si <0x45>; |
| 682 | defm V_CMPS_GE_F32 : VOPC_Real_si <0x46>; |
| 683 | defm V_CMPS_O_F32 : VOPC_Real_si <0x47>; |
| 684 | defm V_CMPS_U_F32 : VOPC_Real_si <0x48>; |
| 685 | defm V_CMPS_NGE_F32 : VOPC_Real_si <0x49>; |
| 686 | defm V_CMPS_NLG_F32 : VOPC_Real_si <0x4a>; |
| 687 | defm V_CMPS_NGT_F32 : VOPC_Real_si <0x4b>; |
| 688 | defm V_CMPS_NLE_F32 : VOPC_Real_si <0x4c>; |
| 689 | defm V_CMPS_NEQ_F32 : VOPC_Real_si <0x4d>; |
| 690 | defm V_CMPS_NLT_F32 : VOPC_Real_si <0x4e>; |
| 691 | defm V_CMPS_TRU_F32 : VOPC_Real_si <0x4f>; |
| 692 | |
| 693 | defm V_CMPSX_F_F32 : VOPC_Real_si <0x50>; |
| 694 | defm V_CMPSX_LT_F32 : VOPC_Real_si <0x51>; |
| 695 | defm V_CMPSX_EQ_F32 : VOPC_Real_si <0x52>; |
| 696 | defm V_CMPSX_LE_F32 : VOPC_Real_si <0x53>; |
| 697 | defm V_CMPSX_GT_F32 : VOPC_Real_si <0x54>; |
| 698 | defm V_CMPSX_LG_F32 : VOPC_Real_si <0x55>; |
| 699 | defm V_CMPSX_GE_F32 : VOPC_Real_si <0x56>; |
| 700 | defm V_CMPSX_O_F32 : VOPC_Real_si <0x57>; |
| 701 | defm V_CMPSX_U_F32 : VOPC_Real_si <0x58>; |
| 702 | defm V_CMPSX_NGE_F32 : VOPC_Real_si <0x59>; |
| 703 | defm V_CMPSX_NLG_F32 : VOPC_Real_si <0x5a>; |
| 704 | defm V_CMPSX_NGT_F32 : VOPC_Real_si <0x5b>; |
| 705 | defm V_CMPSX_NLE_F32 : VOPC_Real_si <0x5c>; |
| 706 | defm V_CMPSX_NEQ_F32 : VOPC_Real_si <0x5d>; |
| 707 | defm V_CMPSX_NLT_F32 : VOPC_Real_si <0x5e>; |
| 708 | defm V_CMPSX_TRU_F32 : VOPC_Real_si <0x5f>; |
| 709 | |
| 710 | defm V_CMPS_F_F64 : VOPC_Real_si <0x60>; |
| 711 | defm V_CMPS_LT_F64 : VOPC_Real_si <0x61>; |
| 712 | defm V_CMPS_EQ_F64 : VOPC_Real_si <0x62>; |
| 713 | defm V_CMPS_LE_F64 : VOPC_Real_si <0x63>; |
| 714 | defm V_CMPS_GT_F64 : VOPC_Real_si <0x64>; |
| 715 | defm V_CMPS_LG_F64 : VOPC_Real_si <0x65>; |
| 716 | defm V_CMPS_GE_F64 : VOPC_Real_si <0x66>; |
| 717 | defm V_CMPS_O_F64 : VOPC_Real_si <0x67>; |
| 718 | defm V_CMPS_U_F64 : VOPC_Real_si <0x68>; |
| 719 | defm V_CMPS_NGE_F64 : VOPC_Real_si <0x69>; |
| 720 | defm V_CMPS_NLG_F64 : VOPC_Real_si <0x6a>; |
| 721 | defm V_CMPS_NGT_F64 : VOPC_Real_si <0x6b>; |
| 722 | defm V_CMPS_NLE_F64 : VOPC_Real_si <0x6c>; |
| 723 | defm V_CMPS_NEQ_F64 : VOPC_Real_si <0x6d>; |
| 724 | defm V_CMPS_NLT_F64 : VOPC_Real_si <0x6e>; |
| 725 | defm V_CMPS_TRU_F64 : VOPC_Real_si <0x6f>; |
| 726 | |
| 727 | defm V_CMPSX_F_F64 : VOPC_Real_si <0x70>; |
| 728 | defm V_CMPSX_LT_F64 : VOPC_Real_si <0x71>; |
| 729 | defm V_CMPSX_EQ_F64 : VOPC_Real_si <0x72>; |
| 730 | defm V_CMPSX_LE_F64 : VOPC_Real_si <0x73>; |
| 731 | defm V_CMPSX_GT_F64 : VOPC_Real_si <0x74>; |
| 732 | defm V_CMPSX_LG_F64 : VOPC_Real_si <0x75>; |
| 733 | defm V_CMPSX_GE_F64 : VOPC_Real_si <0x76>; |
| 734 | defm V_CMPSX_O_F64 : VOPC_Real_si <0x77>; |
| 735 | defm V_CMPSX_U_F64 : VOPC_Real_si <0x78>; |
| 736 | defm V_CMPSX_NGE_F64 : VOPC_Real_si <0x79>; |
| 737 | defm V_CMPSX_NLG_F64 : VOPC_Real_si <0x7a>; |
| 738 | defm V_CMPSX_NGT_F64 : VOPC_Real_si <0x7b>; |
| 739 | defm V_CMPSX_NLE_F64 : VOPC_Real_si <0x7c>; |
| 740 | defm V_CMPSX_NEQ_F64 : VOPC_Real_si <0x7d>; |
| 741 | defm V_CMPSX_NLT_F64 : VOPC_Real_si <0x7e>; |
| 742 | defm V_CMPSX_TRU_F64 : VOPC_Real_si <0x7f>; |
| 743 | |
| 744 | defm V_CMP_F_I32 : VOPC_Real_si <0x80>; |
| 745 | defm V_CMP_LT_I32 : VOPC_Real_si <0x81>; |
| 746 | defm V_CMP_EQ_I32 : VOPC_Real_si <0x82>; |
| 747 | defm V_CMP_LE_I32 : VOPC_Real_si <0x83>; |
| 748 | defm V_CMP_GT_I32 : VOPC_Real_si <0x84>; |
| 749 | defm V_CMP_NE_I32 : VOPC_Real_si <0x85>; |
| 750 | defm V_CMP_GE_I32 : VOPC_Real_si <0x86>; |
| 751 | defm V_CMP_T_I32 : VOPC_Real_si <0x87>; |
| 752 | |
| 753 | defm V_CMPX_F_I32 : VOPC_Real_si <0x90>; |
| 754 | defm V_CMPX_LT_I32 : VOPC_Real_si <0x91>; |
| 755 | defm V_CMPX_EQ_I32 : VOPC_Real_si <0x92>; |
| 756 | defm V_CMPX_LE_I32 : VOPC_Real_si <0x93>; |
| 757 | defm V_CMPX_GT_I32 : VOPC_Real_si <0x94>; |
| 758 | defm V_CMPX_NE_I32 : VOPC_Real_si <0x95>; |
| 759 | defm V_CMPX_GE_I32 : VOPC_Real_si <0x96>; |
| 760 | defm V_CMPX_T_I32 : VOPC_Real_si <0x97>; |
| 761 | |
| 762 | defm V_CMP_F_I64 : VOPC_Real_si <0xa0>; |
| 763 | defm V_CMP_LT_I64 : VOPC_Real_si <0xa1>; |
| 764 | defm V_CMP_EQ_I64 : VOPC_Real_si <0xa2>; |
| 765 | defm V_CMP_LE_I64 : VOPC_Real_si <0xa3>; |
| 766 | defm V_CMP_GT_I64 : VOPC_Real_si <0xa4>; |
| 767 | defm V_CMP_NE_I64 : VOPC_Real_si <0xa5>; |
| 768 | defm V_CMP_GE_I64 : VOPC_Real_si <0xa6>; |
| 769 | defm V_CMP_T_I64 : VOPC_Real_si <0xa7>; |
| 770 | |
| 771 | defm V_CMPX_F_I64 : VOPC_Real_si <0xb0>; |
| 772 | defm V_CMPX_LT_I64 : VOPC_Real_si <0xb1>; |
| 773 | defm V_CMPX_EQ_I64 : VOPC_Real_si <0xb2>; |
| 774 | defm V_CMPX_LE_I64 : VOPC_Real_si <0xb3>; |
| 775 | defm V_CMPX_GT_I64 : VOPC_Real_si <0xb4>; |
| 776 | defm V_CMPX_NE_I64 : VOPC_Real_si <0xb5>; |
| 777 | defm V_CMPX_GE_I64 : VOPC_Real_si <0xb6>; |
| 778 | defm V_CMPX_T_I64 : VOPC_Real_si <0xb7>; |
| 779 | |
| 780 | defm V_CMP_F_U32 : VOPC_Real_si <0xc0>; |
| 781 | defm V_CMP_LT_U32 : VOPC_Real_si <0xc1>; |
| 782 | defm V_CMP_EQ_U32 : VOPC_Real_si <0xc2>; |
| 783 | defm V_CMP_LE_U32 : VOPC_Real_si <0xc3>; |
| 784 | defm V_CMP_GT_U32 : VOPC_Real_si <0xc4>; |
| 785 | defm V_CMP_NE_U32 : VOPC_Real_si <0xc5>; |
| 786 | defm V_CMP_GE_U32 : VOPC_Real_si <0xc6>; |
| 787 | defm V_CMP_T_U32 : VOPC_Real_si <0xc7>; |
| 788 | |
| 789 | defm V_CMPX_F_U32 : VOPC_Real_si <0xd0>; |
| 790 | defm V_CMPX_LT_U32 : VOPC_Real_si <0xd1>; |
| 791 | defm V_CMPX_EQ_U32 : VOPC_Real_si <0xd2>; |
| 792 | defm V_CMPX_LE_U32 : VOPC_Real_si <0xd3>; |
| 793 | defm V_CMPX_GT_U32 : VOPC_Real_si <0xd4>; |
| 794 | defm V_CMPX_NE_U32 : VOPC_Real_si <0xd5>; |
| 795 | defm V_CMPX_GE_U32 : VOPC_Real_si <0xd6>; |
| 796 | defm V_CMPX_T_U32 : VOPC_Real_si <0xd7>; |
| 797 | |
| 798 | defm V_CMP_F_U64 : VOPC_Real_si <0xe0>; |
| 799 | defm V_CMP_LT_U64 : VOPC_Real_si <0xe1>; |
| 800 | defm V_CMP_EQ_U64 : VOPC_Real_si <0xe2>; |
| 801 | defm V_CMP_LE_U64 : VOPC_Real_si <0xe3>; |
| 802 | defm V_CMP_GT_U64 : VOPC_Real_si <0xe4>; |
| 803 | defm V_CMP_NE_U64 : VOPC_Real_si <0xe5>; |
| 804 | defm V_CMP_GE_U64 : VOPC_Real_si <0xe6>; |
| 805 | defm V_CMP_T_U64 : VOPC_Real_si <0xe7>; |
| 806 | |
| 807 | defm V_CMPX_F_U64 : VOPC_Real_si <0xf0>; |
| 808 | defm V_CMPX_LT_U64 : VOPC_Real_si <0xf1>; |
| 809 | defm V_CMPX_EQ_U64 : VOPC_Real_si <0xf2>; |
| 810 | defm V_CMPX_LE_U64 : VOPC_Real_si <0xf3>; |
| 811 | defm V_CMPX_GT_U64 : VOPC_Real_si <0xf4>; |
| 812 | defm V_CMPX_NE_U64 : VOPC_Real_si <0xf5>; |
| 813 | defm V_CMPX_GE_U64 : VOPC_Real_si <0xf6>; |
| 814 | defm V_CMPX_T_U64 : VOPC_Real_si <0xf7>; |
| 815 | |
| 816 | defm V_CMP_CLASS_F32 : VOPC_Real_si <0x88>; |
| 817 | defm V_CMPX_CLASS_F32 : VOPC_Real_si <0x98>; |
| 818 | defm V_CMP_CLASS_F64 : VOPC_Real_si <0xa8>; |
| 819 | defm V_CMPX_CLASS_F64 : VOPC_Real_si <0xb8>; |
| 820 | |
| 821 | //===----------------------------------------------------------------------===// |
| 822 | // VI |
| 823 | //===----------------------------------------------------------------------===// |
| 824 | |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 825 | class VOPC_SDWA<bits<8> op, VOPC_Pseudo ps, VOPProfile P = ps.Pfl> : |
| 826 | VOP_SDWA <ps.OpName, P> { |
| 827 | let Defs = ps.Defs; |
| 828 | let hasSideEffects = ps.hasSideEffects; |
| 829 | let AsmMatchConverter = "cvtSdwaVOPC"; |
| 830 | let isCompare = ps.isCompare; |
| 831 | let isCommutable = ps.isCommutable; |
| Sam Kolton | a6792a3 | 2016-12-22 11:30:48 +0000 | [diff] [blame^] | 832 | let Constraints = ps.Constraints; |
| 833 | let DisableEncoding = ps.DisableEncoding; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 834 | |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 835 | bits<8> src1; |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 836 | let Inst{8-0} = 0xf9; // sdwa |
| 837 | let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); |
| 838 | let Inst{24-17} = op; |
| 839 | let Inst{31-25} = 0x3e; // encoding |
| 840 | |
| 841 | // VOPC disallows dst_sel and dst_unused as they have no effect on destination |
| 842 | let Inst{42-40} = SDWA_DWORD; |
| 843 | let Inst{44-43} = SDWA_UNUSED_PRESERVE; |
| 844 | } |
| 845 | |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 846 | multiclass VOPC_Real_vi <bits<10> op> { |
| 847 | let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in { |
| 848 | def _e32_vi : |
| 849 | VOPC_Real<!cast<VOPC_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>, |
| 850 | VOPCe<op{7-0}>; |
| 851 | |
| 852 | def _e64_vi : |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 853 | VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>, |
| 854 | VOP3a_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> { |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 855 | // Encoding used for VOPC instructions encoded as VOP3 |
| 856 | // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst |
| 857 | bits<8> sdst; |
| 858 | let Inst{7-0} = sdst; |
| 859 | } |
| 860 | } |
| 861 | |
| 862 | // for now left sdwa only for asm/dasm |
| 863 | // TODO: add corresponding pseudo |
| 864 | def _sdwa : VOPC_SDWA<op{7-0}, !cast<VOPC_Pseudo>(NAME#"_e32")>; |
| 865 | |
| Valery Pykhtin | 355103f | 2016-09-23 09:08:07 +0000 | [diff] [blame] | 866 | def : VOPCInstAlias <!cast<VOP3_Pseudo>(NAME#"_e64"), |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 867 | !cast<Instruction>(NAME#"_e32_vi")> { |
| 868 | let AssemblerPredicate = isVI; |
| 869 | } |
| 870 | } |
| 871 | |
| Valery Pykhtin | 2828b9b | 2016-09-19 14:39:49 +0000 | [diff] [blame] | 872 | defm V_CMP_CLASS_F32 : VOPC_Real_vi <0x10>; |
| 873 | defm V_CMPX_CLASS_F32 : VOPC_Real_vi <0x11>; |
| 874 | defm V_CMP_CLASS_F64 : VOPC_Real_vi <0x12>; |
| 875 | defm V_CMPX_CLASS_F64 : VOPC_Real_vi <0x13>; |
| Konstantin Zhuravlyov | f86e4b7 | 2016-11-13 07:01:11 +0000 | [diff] [blame] | 876 | defm V_CMP_CLASS_F16 : VOPC_Real_vi <0x14>; |
| 877 | defm V_CMPX_CLASS_F16 : VOPC_Real_vi <0x15>; |
| 878 | |
| 879 | defm V_CMP_F_F16 : VOPC_Real_vi <0x20>; |
| 880 | defm V_CMP_LT_F16 : VOPC_Real_vi <0x21>; |
| 881 | defm V_CMP_EQ_F16 : VOPC_Real_vi <0x22>; |
| 882 | defm V_CMP_LE_F16 : VOPC_Real_vi <0x23>; |
| 883 | defm V_CMP_GT_F16 : VOPC_Real_vi <0x24>; |
| 884 | defm V_CMP_LG_F16 : VOPC_Real_vi <0x25>; |
| 885 | defm V_CMP_GE_F16 : VOPC_Real_vi <0x26>; |
| 886 | defm V_CMP_O_F16 : VOPC_Real_vi <0x27>; |
| 887 | defm V_CMP_U_F16 : VOPC_Real_vi <0x28>; |
| 888 | defm V_CMP_NGE_F16 : VOPC_Real_vi <0x29>; |
| 889 | defm V_CMP_NLG_F16 : VOPC_Real_vi <0x2a>; |
| 890 | defm V_CMP_NGT_F16 : VOPC_Real_vi <0x2b>; |
| 891 | defm V_CMP_NLE_F16 : VOPC_Real_vi <0x2c>; |
| 892 | defm V_CMP_NEQ_F16 : VOPC_Real_vi <0x2d>; |
| 893 | defm V_CMP_NLT_F16 : VOPC_Real_vi <0x2e>; |
| 894 | defm V_CMP_TRU_F16 : VOPC_Real_vi <0x2f>; |
| 895 | |
| 896 | defm V_CMPX_F_F16 : VOPC_Real_vi <0x30>; |
| 897 | defm V_CMPX_LT_F16 : VOPC_Real_vi <0x31>; |
| 898 | defm V_CMPX_EQ_F16 : VOPC_Real_vi <0x32>; |
| 899 | defm V_CMPX_LE_F16 : VOPC_Real_vi <0x33>; |
| 900 | defm V_CMPX_GT_F16 : VOPC_Real_vi <0x34>; |
| 901 | defm V_CMPX_LG_F16 : VOPC_Real_vi <0x35>; |
| 902 | defm V_CMPX_GE_F16 : VOPC_Real_vi <0x36>; |
| 903 | defm V_CMPX_O_F16 : VOPC_Real_vi <0x37>; |
| 904 | defm V_CMPX_U_F16 : VOPC_Real_vi <0x38>; |
| 905 | defm V_CMPX_NGE_F16 : VOPC_Real_vi <0x39>; |
| 906 | defm V_CMPX_NLG_F16 : VOPC_Real_vi <0x3a>; |
| 907 | defm V_CMPX_NGT_F16 : VOPC_Real_vi <0x3b>; |
| 908 | defm V_CMPX_NLE_F16 : VOPC_Real_vi <0x3c>; |
| 909 | defm V_CMPX_NEQ_F16 : VOPC_Real_vi <0x3d>; |
| 910 | defm V_CMPX_NLT_F16 : VOPC_Real_vi <0x3e>; |
| 911 | defm V_CMPX_TRU_F16 : VOPC_Real_vi <0x3f>; |
| 912 | |
| 913 | defm V_CMP_F_F32 : VOPC_Real_vi <0x40>; |
| 914 | defm V_CMP_LT_F32 : VOPC_Real_vi <0x41>; |
| 915 | defm V_CMP_EQ_F32 : VOPC_Real_vi <0x42>; |
| 916 | defm V_CMP_LE_F32 : VOPC_Real_vi <0x43>; |
| 917 | defm V_CMP_GT_F32 : VOPC_Real_vi <0x44>; |
| 918 | defm V_CMP_LG_F32 : VOPC_Real_vi <0x45>; |
| 919 | defm V_CMP_GE_F32 : VOPC_Real_vi <0x46>; |
| 920 | defm V_CMP_O_F32 : VOPC_Real_vi <0x47>; |
| 921 | defm V_CMP_U_F32 : VOPC_Real_vi <0x48>; |
| 922 | defm V_CMP_NGE_F32 : VOPC_Real_vi <0x49>; |
| 923 | defm V_CMP_NLG_F32 : VOPC_Real_vi <0x4a>; |
| 924 | defm V_CMP_NGT_F32 : VOPC_Real_vi <0x4b>; |
| 925 | defm V_CMP_NLE_F32 : VOPC_Real_vi <0x4c>; |
| 926 | defm V_CMP_NEQ_F32 : VOPC_Real_vi <0x4d>; |
| 927 | defm V_CMP_NLT_F32 : VOPC_Real_vi <0x4e>; |
| 928 | defm V_CMP_TRU_F32 : VOPC_Real_vi <0x4f>; |
| 929 | |
| 930 | defm V_CMPX_F_F32 : VOPC_Real_vi <0x50>; |
| 931 | defm V_CMPX_LT_F32 : VOPC_Real_vi <0x51>; |
| 932 | defm V_CMPX_EQ_F32 : VOPC_Real_vi <0x52>; |
| 933 | defm V_CMPX_LE_F32 : VOPC_Real_vi <0x53>; |
| 934 | defm V_CMPX_GT_F32 : VOPC_Real_vi <0x54>; |
| 935 | defm V_CMPX_LG_F32 : VOPC_Real_vi <0x55>; |
| 936 | defm V_CMPX_GE_F32 : VOPC_Real_vi <0x56>; |
| 937 | defm V_CMPX_O_F32 : VOPC_Real_vi <0x57>; |
| 938 | defm V_CMPX_U_F32 : VOPC_Real_vi <0x58>; |
| 939 | defm V_CMPX_NGE_F32 : VOPC_Real_vi <0x59>; |
| 940 | defm V_CMPX_NLG_F32 : VOPC_Real_vi <0x5a>; |
| 941 | defm V_CMPX_NGT_F32 : VOPC_Real_vi <0x5b>; |
| 942 | defm V_CMPX_NLE_F32 : VOPC_Real_vi <0x5c>; |
| 943 | defm V_CMPX_NEQ_F32 : VOPC_Real_vi <0x5d>; |
| 944 | defm V_CMPX_NLT_F32 : VOPC_Real_vi <0x5e>; |
| 945 | defm V_CMPX_TRU_F32 : VOPC_Real_vi <0x5f>; |
| 946 | |
| 947 | defm V_CMP_F_F64 : VOPC_Real_vi <0x60>; |
| 948 | defm V_CMP_LT_F64 : VOPC_Real_vi <0x61>; |
| 949 | defm V_CMP_EQ_F64 : VOPC_Real_vi <0x62>; |
| 950 | defm V_CMP_LE_F64 : VOPC_Real_vi <0x63>; |
| 951 | defm V_CMP_GT_F64 : VOPC_Real_vi <0x64>; |
| 952 | defm V_CMP_LG_F64 : VOPC_Real_vi <0x65>; |
| 953 | defm V_CMP_GE_F64 : VOPC_Real_vi <0x66>; |
| 954 | defm V_CMP_O_F64 : VOPC_Real_vi <0x67>; |
| 955 | defm V_CMP_U_F64 : VOPC_Real_vi <0x68>; |
| 956 | defm V_CMP_NGE_F64 : VOPC_Real_vi <0x69>; |
| 957 | defm V_CMP_NLG_F64 : VOPC_Real_vi <0x6a>; |
| 958 | defm V_CMP_NGT_F64 : VOPC_Real_vi <0x6b>; |
| 959 | defm V_CMP_NLE_F64 : VOPC_Real_vi <0x6c>; |
| 960 | defm V_CMP_NEQ_F64 : VOPC_Real_vi <0x6d>; |
| 961 | defm V_CMP_NLT_F64 : VOPC_Real_vi <0x6e>; |
| 962 | defm V_CMP_TRU_F64 : VOPC_Real_vi <0x6f>; |
| 963 | |
| 964 | defm V_CMPX_F_F64 : VOPC_Real_vi <0x70>; |
| 965 | defm V_CMPX_LT_F64 : VOPC_Real_vi <0x71>; |
| 966 | defm V_CMPX_EQ_F64 : VOPC_Real_vi <0x72>; |
| 967 | defm V_CMPX_LE_F64 : VOPC_Real_vi <0x73>; |
| 968 | defm V_CMPX_GT_F64 : VOPC_Real_vi <0x74>; |
| 969 | defm V_CMPX_LG_F64 : VOPC_Real_vi <0x75>; |
| 970 | defm V_CMPX_GE_F64 : VOPC_Real_vi <0x76>; |
| 971 | defm V_CMPX_O_F64 : VOPC_Real_vi <0x77>; |
| 972 | defm V_CMPX_U_F64 : VOPC_Real_vi <0x78>; |
| 973 | defm V_CMPX_NGE_F64 : VOPC_Real_vi <0x79>; |
| 974 | defm V_CMPX_NLG_F64 : VOPC_Real_vi <0x7a>; |
| 975 | defm V_CMPX_NGT_F64 : VOPC_Real_vi <0x7b>; |
| 976 | defm V_CMPX_NLE_F64 : VOPC_Real_vi <0x7c>; |
| 977 | defm V_CMPX_NEQ_F64 : VOPC_Real_vi <0x7d>; |
| 978 | defm V_CMPX_NLT_F64 : VOPC_Real_vi <0x7e>; |
| 979 | defm V_CMPX_TRU_F64 : VOPC_Real_vi <0x7f>; |
| 980 | |
| 981 | defm V_CMP_F_I32 : VOPC_Real_vi <0xc0>; |
| 982 | defm V_CMP_LT_I32 : VOPC_Real_vi <0xc1>; |
| 983 | defm V_CMP_EQ_I32 : VOPC_Real_vi <0xc2>; |
| 984 | defm V_CMP_LE_I32 : VOPC_Real_vi <0xc3>; |
| 985 | defm V_CMP_GT_I32 : VOPC_Real_vi <0xc4>; |
| 986 | defm V_CMP_NE_I32 : VOPC_Real_vi <0xc5>; |
| 987 | defm V_CMP_GE_I32 : VOPC_Real_vi <0xc6>; |
| 988 | defm V_CMP_T_I32 : VOPC_Real_vi <0xc7>; |
| 989 | |
| 990 | defm V_CMPX_F_I32 : VOPC_Real_vi <0xd0>; |
| 991 | defm V_CMPX_LT_I32 : VOPC_Real_vi <0xd1>; |
| 992 | defm V_CMPX_EQ_I32 : VOPC_Real_vi <0xd2>; |
| 993 | defm V_CMPX_LE_I32 : VOPC_Real_vi <0xd3>; |
| 994 | defm V_CMPX_GT_I32 : VOPC_Real_vi <0xd4>; |
| 995 | defm V_CMPX_NE_I32 : VOPC_Real_vi <0xd5>; |
| 996 | defm V_CMPX_GE_I32 : VOPC_Real_vi <0xd6>; |
| 997 | defm V_CMPX_T_I32 : VOPC_Real_vi <0xd7>; |
| 998 | |
| 999 | defm V_CMP_F_I64 : VOPC_Real_vi <0xe0>; |
| 1000 | defm V_CMP_LT_I64 : VOPC_Real_vi <0xe1>; |
| 1001 | defm V_CMP_EQ_I64 : VOPC_Real_vi <0xe2>; |
| 1002 | defm V_CMP_LE_I64 : VOPC_Real_vi <0xe3>; |
| 1003 | defm V_CMP_GT_I64 : VOPC_Real_vi <0xe4>; |
| 1004 | defm V_CMP_NE_I64 : VOPC_Real_vi <0xe5>; |
| 1005 | defm V_CMP_GE_I64 : VOPC_Real_vi <0xe6>; |
| 1006 | defm V_CMP_T_I64 : VOPC_Real_vi <0xe7>; |
| 1007 | |
| 1008 | defm V_CMPX_F_I64 : VOPC_Real_vi <0xf0>; |
| 1009 | defm V_CMPX_LT_I64 : VOPC_Real_vi <0xf1>; |
| 1010 | defm V_CMPX_EQ_I64 : VOPC_Real_vi <0xf2>; |
| 1011 | defm V_CMPX_LE_I64 : VOPC_Real_vi <0xf3>; |
| 1012 | defm V_CMPX_GT_I64 : VOPC_Real_vi <0xf4>; |
| 1013 | defm V_CMPX_NE_I64 : VOPC_Real_vi <0xf5>; |
| 1014 | defm V_CMPX_GE_I64 : VOPC_Real_vi <0xf6>; |
| 1015 | defm V_CMPX_T_I64 : VOPC_Real_vi <0xf7>; |
| 1016 | |
| 1017 | defm V_CMP_F_U32 : VOPC_Real_vi <0xc8>; |
| 1018 | defm V_CMP_LT_U32 : VOPC_Real_vi <0xc9>; |
| 1019 | defm V_CMP_EQ_U32 : VOPC_Real_vi <0xca>; |
| 1020 | defm V_CMP_LE_U32 : VOPC_Real_vi <0xcb>; |
| 1021 | defm V_CMP_GT_U32 : VOPC_Real_vi <0xcc>; |
| 1022 | defm V_CMP_NE_U32 : VOPC_Real_vi <0xcd>; |
| 1023 | defm V_CMP_GE_U32 : VOPC_Real_vi <0xce>; |
| 1024 | defm V_CMP_T_U32 : VOPC_Real_vi <0xcf>; |
| 1025 | |
| 1026 | defm V_CMPX_F_U32 : VOPC_Real_vi <0xd8>; |
| 1027 | defm V_CMPX_LT_U32 : VOPC_Real_vi <0xd9>; |
| 1028 | defm V_CMPX_EQ_U32 : VOPC_Real_vi <0xda>; |
| 1029 | defm V_CMPX_LE_U32 : VOPC_Real_vi <0xdb>; |
| 1030 | defm V_CMPX_GT_U32 : VOPC_Real_vi <0xdc>; |
| 1031 | defm V_CMPX_NE_U32 : VOPC_Real_vi <0xdd>; |
| 1032 | defm V_CMPX_GE_U32 : VOPC_Real_vi <0xde>; |
| 1033 | defm V_CMPX_T_U32 : VOPC_Real_vi <0xdf>; |
| 1034 | |
| 1035 | defm V_CMP_F_U64 : VOPC_Real_vi <0xe8>; |
| 1036 | defm V_CMP_LT_U64 : VOPC_Real_vi <0xe9>; |
| 1037 | defm V_CMP_EQ_U64 : VOPC_Real_vi <0xea>; |
| 1038 | defm V_CMP_LE_U64 : VOPC_Real_vi <0xeb>; |
| 1039 | defm V_CMP_GT_U64 : VOPC_Real_vi <0xec>; |
| 1040 | defm V_CMP_NE_U64 : VOPC_Real_vi <0xed>; |
| 1041 | defm V_CMP_GE_U64 : VOPC_Real_vi <0xee>; |
| 1042 | defm V_CMP_T_U64 : VOPC_Real_vi <0xef>; |
| 1043 | |
| 1044 | defm V_CMPX_F_U64 : VOPC_Real_vi <0xf8>; |
| 1045 | defm V_CMPX_LT_U64 : VOPC_Real_vi <0xf9>; |
| 1046 | defm V_CMPX_EQ_U64 : VOPC_Real_vi <0xfa>; |
| 1047 | defm V_CMPX_LE_U64 : VOPC_Real_vi <0xfb>; |
| 1048 | defm V_CMPX_GT_U64 : VOPC_Real_vi <0xfc>; |
| 1049 | defm V_CMPX_NE_U64 : VOPC_Real_vi <0xfd>; |
| 1050 | defm V_CMPX_GE_U64 : VOPC_Real_vi <0xfe>; |
| 1051 | defm V_CMPX_T_U64 : VOPC_Real_vi <0xff>; |