| Saleem Abdulrasool | 3bdb7a9 | 2019-07-25 20:59:48 +0000 | [diff] [blame] | 1 | // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -emit-llvm --std=c++17 -fcxx-exceptions -fexceptions -discard-value-names %s -o - | FileCheck %s |
| 2 | |
| 3 | struct Q { Q(); }; |
| 4 | struct R { R(Q); ~R(); }; |
| 5 | struct S { S(Q); ~S(); }; |
| 6 | struct T : R, S {}; |
| 7 | |
| 8 | Q q; |
| 9 | T t { R{q}, S{q} }; |
| 10 | |
| 11 | // CHECK-LABEL: define internal void @__cxx_global_var_init.1() {{.*}} { |
| 12 | // CHECK-NEXT: [[TMP_R:%[a-z0-9.]+]] = alloca %struct.R, align 1 |
| 13 | // CHECK-NEXT: [[TMP_Q1:%[a-z0-9.]+]] = alloca %struct.Q, align 1 |
| 14 | // CHECK-NEXT: [[TMP_S:%[a-z0-9.]+]] = alloca %struct.S, align 1 |
| 15 | // CHECK-NEXT: [[TMP_Q2:%[a-z0-9.]+]] = alloca %struct.Q, align 1 |
| 16 | // CHECK-NEXT: [[XPT:%[a-z0-9.]+]] = alloca i8* |
| 17 | // CHECK-NEXT: [[SLOT:%[a-z0-9.]+]] = alloca i32 |
| 18 | // CHECK-NEXT: [[ACTIVE:%[a-z0-9.]+]] = alloca i1, align 1 |
| 19 | // CHECK-NEXT: call void @_ZN1RC1E1Q(%struct.R* [[TMP_R]]) |
| 20 | // CHECK-NEXT: store i1 true, i1* [[ACTIVE]], align 1 |
| 21 | // CHECK-NEXT: invoke void @_ZN1SC1E1Q(%struct.S* [[TMP_S]]) |
| 22 | // CHECK-NEXT: to label %[[L1:[a-z0-9.]+]] unwind label %[[L2:[a-z0-9.]+]] |
| 23 | // CHECK-EMPTY: |
| 24 | // CHECK-NEXT: [[L1]]: |
| 25 | // CHECK-NEXT: store i1 false, i1* [[ACTIVE]], align 1 |
| 26 | // CHECK-NEXT: call void @_ZN1SD1Ev(%struct.S* |
| 27 | // CHECK-NEXT: call void @_ZN1RD1Ev(%struct.R* |
| 28 | // CHECK-NEXT: [[EXIT:%[a-z0-9.]+]] = call i32 @__cxa_atexit( |
| 29 | // CHECK-NEXT: ret void |
| 30 | // CHECK-EMPTY: |
| 31 | // CHECK-NEXT: [[L2]]: |
| 32 | // CHECK-NEXT: [[LP:%[a-z0-9.]+]] = landingpad { i8*, i32 } |
| 33 | // CHECK-NEXT: cleanup |
| 34 | // CHECK-NEXT: [[X1:%[a-z0-9.]+]] = extractvalue { i8*, i32 } [[LP]], 0 |
| 35 | // CHECK-NEXT: store i8* [[X1]], i8** [[XPT]], align 8 |
| 36 | // CHECK-NEXT: [[X2:%[a-z0-9.]+]] = extractvalue { i8*, i32 } [[LP]], 1 |
| 37 | // CHECK-NEXT: store i32 [[X2]], i32* [[SLOT]], align 4 |
| 38 | // CHECK-NEXT: [[IS_ACT:%[a-z0-9.]+]] = load i1, i1* [[ACTIVE]], align 1 |
| 39 | // CHECK-NEXT: br i1 [[IS_ACT]], label %[[L3:[a-z0-9.]+]], label %[[L4:[a-z0-9.]+]] |
| 40 | // CHECK-EMPTY: |
| 41 | // CHECK-NEXT: [[L3]]: |
| 42 | // CHECK-NEXT: call void @_ZN1RD1Ev(%struct.R* |
| 43 | // CHECK-NEXT: br label %[[L4]] |
| 44 | // CHECK-EMPTY: |
| 45 | // CHECK-NEXT: [[L4]]: |
| 46 | // CHECK-NEXT: call void @_ZN1RD1Ev(%struct.R* [[TMP_R]]) |
| 47 | // CHECK-NEXT: br label %[[L5:[a-z0-9.]+]] |
| 48 | // CHECK-EMPTY: |
| 49 | // CHECK-NEXT: [[L5]]: |
| 50 | // CHECK-NEXT: [[EXN:%[a-z0-9.]+]] = load i8*, i8** [[XPT]], align 8 |
| 51 | // CHECK-NEXT: [[SEL:%[a-z0-9.]+]] = load i32, i32* [[SLOT]], align 4 |
| 52 | // CHECK-NEXT: [[LV1:%[a-z0-9.]+]] = insertvalue { i8*, i32 } undef, i8* [[EXN]], 0 |
| 53 | // CHECK-NEXT: [[LV2:%[a-z0-9.]+]] = insertvalue { i8*, i32 } [[LV1]], i32 [[SEL]], 1 |
| 54 | // CHECK-NEXT: resume { i8*, i32 } [[LV2]] |
| 55 | // CHECK-NEXT: } |