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Chris Lattnerd92fb002002-10-25 22:55:53 +00001//===- X86InstructionInfo.h - X86 Instruction Information ---------*-C++-*-===//
2//
Chris Lattnerf57420e2002-10-29 20:48:56 +00003// This file contains the X86 implementation of the MachineInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +00004//
5//===----------------------------------------------------------------------===//
6
7#ifndef X86INSTRUCTIONINFO_H
8#define X86INSTRUCTIONINFO_H
9
Chris Lattner16cbd412002-10-29 17:43:19 +000010#include "llvm/Target/MachineInstrInfo.h"
Chris Lattnerd92fb002002-10-25 22:55:53 +000011#include "X86RegisterInfo.h"
12
Chris Lattner60c59d52002-10-30 01:09:34 +000013/// X86II - This namespace holds all of the target specific flags that
14/// instruction info tracks.
15///
16namespace X86II {
17 enum {
Chris Lattner0018e8d2002-11-18 05:37:11 +000018 //===------------------------------------------------------------------===//
19 // Instruction types. These are the standard/most common forms for X86
20 // instructions.
21 //
22
23 /// Other - An instruction gets this form if it doesn't fit any of the
24 /// catagories below.
25 OtherFrm = 0,
26
27 /// Raw - This form is for instructions that don't have any operands, so
28 /// they are just a fixed opcode value, like 'leave'.
29 RawFrm = 1,
30
31 /// AddRegFrm - This form is used for instructions like 'push r32' that have
32 /// their one register operand added to their opcode.
33 AddRegFrm = 2,
34
35 /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
36 /// to specify a destination, which in this case is a register.
37 ///
38 MRMDestReg = 3,
39
40 /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
41 /// to specify a destination, which in this case is memory.
42 ///
43 MRMDestMem = 4,
44
45 /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
46 /// to specify a source, which in this case is a register.
47 ///
48 MRMSrcReg = 5,
49
50 /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
51 /// to specify a source, which in this case is memory.
52 ///
53 MRMSrcMem = 6,
54
Chris Lattnera6eb52f2002-11-21 17:08:49 +000055 /// MRMS[0-7][rm] - These forms are used to represent instructions that use
56 /// a Mod/RM byte, and use the middle field to hold extended opcode
57 /// information. In the intel manual these are represented as /0, /1, ...
58 ///
Chris Lattner0018e8d2002-11-18 05:37:11 +000059
Chris Lattnera6eb52f2002-11-21 17:08:49 +000060 // First, instructions that operate on a register r/m operand...
61 MRMS0r = 16, MRMS1r = 17, MRMS2r = 18, MRMS3r = 19, // Format /0 /1 /2 /3
62 MRMS4r = 20, MRMS5r = 21, MRMS6r = 22, MRMS7r = 23, // Format /4 /5 /6 /7
63
64 // Next, instructions that operate on a memory r/m operand...
65 MRMS0m = 24, MRMS1m = 25, MRMS2m = 26, MRMS3m = 27, // Format /0 /1 /2 /3
66 MRMS4m = 28, MRMS5m = 29, MRMS6m = 30, MRMS7m = 31, // Format /4 /5 /6 /7
67
68 FormMask = 31,
Chris Lattner0018e8d2002-11-18 05:37:11 +000069
70 //===------------------------------------------------------------------===//
71 // Actual flags...
72
Chris Lattnerf2e00c62002-11-18 01:59:28 +000073 /// Void - Set if this instruction produces no value
Chris Lattnera6eb52f2002-11-21 17:08:49 +000074 Void = 1 << 5,
Chris Lattnerf2e00c62002-11-18 01:59:28 +000075
76 // TB - TwoByte - Set if this instruction has a two byte opcode, which
77 // starts with a 0x0F byte before the real opcode.
Chris Lattnera6eb52f2002-11-21 17:08:49 +000078 TB = 1 << 6,
Chris Lattnerc48d0fa2002-11-21 01:32:55 +000079
80 // OpSize - Set if this instruction requires an operand size prefix (0x66),
81 // which most often indicates that the instruction operates on 16 bit data
82 // instead of 32 bit data.
Chris Lattnera6eb52f2002-11-21 17:08:49 +000083 OpSize = 1 << 7,
Chris Lattner60c59d52002-10-30 01:09:34 +000084 };
85}
86
Chris Lattner27d24792002-10-29 21:05:24 +000087class X86InstrInfo : public MachineInstrInfo {
Chris Lattnerd92fb002002-10-25 22:55:53 +000088 const X86RegisterInfo RI;
89public:
Chris Lattner27d24792002-10-29 21:05:24 +000090 X86InstrInfo();
Chris Lattnerd92fb002002-10-25 22:55:53 +000091
Chris Lattnerf57420e2002-10-29 20:48:56 +000092 /// getRegisterInfo - MachineInstrInfo is a superset of MRegister info. As
Chris Lattnerd92fb002002-10-25 22:55:53 +000093 /// such, whenever a client has an instance of instruction info, it should
94 /// always be able to get register info as well (through this method).
95 ///
96 virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
97
Chris Lattner9289d7d2002-11-17 22:53:13 +000098 /// print - Print out an x86 instruction in intel syntax
Chris Lattnerd92fb002002-10-25 22:55:53 +000099 ///
Chris Lattner5fd53042002-11-17 23:20:37 +0000100 virtual void print(const MachineInstr *MI, std::ostream &O,
101 const TargetMachine &TM) const;
Chris Lattner16cbd412002-10-29 17:43:19 +0000102
Chris Lattnercf72e522002-11-18 06:56:24 +0000103 // getBaseOpcodeFor - This function returns the "base" X86 opcode for the
104 // specified opcode number.
105 //
106 unsigned char getBaseOpcodeFor(unsigned Opcode) const;
107
108
Chris Lattner16cbd412002-10-29 17:43:19 +0000109
110 //===--------------------------------------------------------------------===//
111 //
112 // These are stubs for pure virtual methods that should be factored out of
113 // MachineInstrInfo. We never call them, we don't want them, but we need
114 // stubs so that we can instatiate our class.
115 //
116 MachineOpCode getNOPOpCode() const { abort(); }
117 void CreateCodeToLoadConst(const TargetMachine& target, Function* F,
118 Value *V, Instruction *I,
119 std::vector<MachineInstr*>& mvec,
120 MachineCodeForInstruction& mcfi) const { abort(); }
121 void CreateCodeToCopyIntToFloat(const TargetMachine& target,
122 Function* F, Value* val, Instruction* dest,
123 std::vector<MachineInstr*>& mvec,
124 MachineCodeForInstruction& mcfi) const {
125 abort();
126 }
127 void CreateCodeToCopyFloatToInt(const TargetMachine& target, Function* F,
128 Value* val, Instruction* dest,
129 std::vector<MachineInstr*>& mvec,
130 MachineCodeForInstruction& mcfi)const {
131 abort();
132 }
133 void CreateCopyInstructionsByType(const TargetMachine& target,
134 Function* F, Value* src,
135 Instruction* dest,
136 std::vector<MachineInstr*>& mvec,
137 MachineCodeForInstruction& mcfi)const {
138 abort();
139 }
140
141 void CreateSignExtensionInstructions(const TargetMachine& target,
142 Function* F, Value* srcVal,
143 Value* destVal, unsigned numLowBits,
144 std::vector<MachineInstr*>& mvec,
145 MachineCodeForInstruction& mcfi) const {
146 abort();
147 }
148
149 void CreateZeroExtensionInstructions(const TargetMachine& target,
150 Function* F, Value* srcVal,
151 Value* destVal, unsigned srcSizeInBits,
152 std::vector<MachineInstr*>& mvec,
153 MachineCodeForInstruction& mcfi) const {
154 abort();
155 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000156};
157
158
159#endif