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gerrit-public.fairphone.software / toolchain / llvm-project / a72fad980cb18a09dbd6ea95d3b5684d3280894a / . / llvm / lib / Target / Hexagon / HexagonIntrinsicsV60.td
blob: f438b3e0368fd7baccadff8c3d09a4b20a537d87 [file] [log] [blame]
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]1//=- HexagonIntrinsicsV60.td - Target Description for Hexagon -*- tablegen *-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Hexagon V60 Compiler Intrinsics in TableGen format.
11//
12//===----------------------------------------------------------------------===//
13
Krzysztof Parzyszek040bb352016-04-22 18:05:55 +0000[diff] [blame]14
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]15let AddedComplexity = 100 in {
16def : Pat < (v16i32 (int_hexagon_V6_lo (v32i32 VecDblRegs:$src1))),
Krzysztof Parzyszeka5409972016-11-09 16:19:08 +0000[diff] [blame]17 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_lo)) >,
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]18 Requires<[UseHVXSgl]>;
19
20def : Pat < (v16i32 (int_hexagon_V6_hi (v32i32 VecDblRegs:$src1))),
Krzysztof Parzyszeka5409972016-11-09 16:19:08 +0000[diff] [blame]21 (v16i32 (EXTRACT_SUBREG (v32i32 VecDblRegs:$src1), vsub_hi)) >,
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]22 Requires<[UseHVXSgl]>;
23
24def : Pat < (v32i32 (int_hexagon_V6_lo_128B (v64i32 VecDblRegs128B:$src1))),
Krzysztof Parzyszeka5409972016-11-09 16:19:08 +0000[diff] [blame]25 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_lo)) >,
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]26 Requires<[UseHVXDbl]>;
27
28def : Pat < (v32i32 (int_hexagon_V6_hi_128B (v64i32 VecDblRegs128B:$src1))),
Krzysztof Parzyszeka5409972016-11-09 16:19:08 +0000[diff] [blame]29 (v32i32 (EXTRACT_SUBREG (v64i32 VecDblRegs128B:$src1), vsub_hi)) >,
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]30 Requires<[UseHVXDbl]>;
31}
32
33def : Pat <(v512i1 (bitconvert (v16i32 VectorRegs:$src1))),
34 (v512i1 (V6_vandvrt(v16i32 VectorRegs:$src1),
35 (A2_tfrsi 0x01010101)))>,
36 Requires<[UseHVXSgl]>;
37
38def : Pat <(v512i1 (bitconvert (v32i16 VectorRegs:$src1))),
39 (v512i1 (V6_vandvrt(v32i16 VectorRegs:$src1),
40 (A2_tfrsi 0x01010101)))>,
41 Requires<[UseHVXSgl]>;
42
43def : Pat <(v512i1 (bitconvert (v64i8 VectorRegs:$src1))),
44 (v512i1 (V6_vandvrt(v64i8 VectorRegs:$src1),
45 (A2_tfrsi 0x01010101)))>,
46 Requires<[UseHVXSgl]>;
47
48def : Pat <(v512i1 (bitconvert (v8i64 VectorRegs:$src1))),
49 (v512i1 (V6_vandvrt(v8i64 VectorRegs:$src1),
50 (A2_tfrsi 0x01010101)))>,
51 Requires<[UseHVXSgl]>;
52
53def : Pat <(v16i32 (bitconvert (v512i1 VecPredRegs:$src1))),
54 (v16i32 (V6_vandqrt(v512i1 VecPredRegs:$src1),
55 (A2_tfrsi 0x01010101)))>,
56 Requires<[UseHVXSgl]>;
57
58def : Pat <(v32i16 (bitconvert (v512i1 VecPredRegs:$src1))),
59 (v32i16 (V6_vandqrt(v512i1 VecPredRegs:$src1),
60 (A2_tfrsi 0x01010101)))>,
61 Requires<[UseHVXSgl]>;
62
63def : Pat <(v64i8 (bitconvert (v512i1 VecPredRegs:$src1))),
64 (v64i8 (V6_vandqrt(v512i1 VecPredRegs:$src1),
65 (A2_tfrsi 0x01010101)))>,
66 Requires<[UseHVXSgl]>;
67
68def : Pat <(v8i64 (bitconvert (v512i1 VecPredRegs:$src1))),
69 (v8i64 (V6_vandqrt(v512i1 VecPredRegs:$src1),
70 (A2_tfrsi 0x01010101)))>,
71 Requires<[UseHVXSgl]>;
72
73def : Pat <(v1024i1 (bitconvert (v32i32 VectorRegs128B:$src1))),
74 (v1024i1 (V6_vandvrt_128B(v32i32 VectorRegs128B:$src1),
75 (A2_tfrsi 0x01010101)))>,
76 Requires<[UseHVXDbl]>;
77
78def : Pat <(v1024i1 (bitconvert (v64i16 VectorRegs128B:$src1))),
79 (v1024i1 (V6_vandvrt_128B(v64i16 VectorRegs128B:$src1),
80 (A2_tfrsi 0x01010101)))>,
81 Requires<[UseHVXDbl]>;
82
83def : Pat <(v1024i1 (bitconvert (v128i8 VectorRegs128B:$src1))),
84 (v1024i1 (V6_vandvrt_128B(v128i8 VectorRegs128B:$src1),
85 (A2_tfrsi 0x01010101)))>,
86 Requires<[UseHVXDbl]>;
87
88def : Pat <(v1024i1 (bitconvert (v16i64 VectorRegs128B:$src1))),
89 (v1024i1 (V6_vandvrt_128B(v16i64 VectorRegs128B:$src1),
90 (A2_tfrsi 0x01010101)))>,
91 Requires<[UseHVXDbl]>;
92
93def : Pat <(v32i32 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
94 (v32i32 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
95 (A2_tfrsi 0x01010101)))>,
96 Requires<[UseHVXDbl]>;
97
98def : Pat <(v64i16 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
99 (v64i16 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
100 (A2_tfrsi 0x01010101)))>,
101 Requires<[UseHVXDbl]>;
102
103def : Pat <(v128i8 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
104 (v128i8 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
105 (A2_tfrsi 0x01010101)))>,
106 Requires<[UseHVXDbl]>;
107
108def : Pat <(v16i64 (bitconvert (v1024i1 VecPredRegs128B:$src1))),
109 (v16i64 (V6_vandqrt_128B(v1024i1 VecPredRegs128B:$src1),
110 (A2_tfrsi 0x01010101)))>,
111 Requires<[UseHVXDbl]>;
112
113let AddedComplexity = 140 in {
114def : Pat <(store (v512i1 VecPredRegs:$src1), (i32 IntRegs:$addr)),
115 (V6_vS32b_ai IntRegs:$addr, 0,
116 (v16i32 (V6_vandqrt (v512i1 VecPredRegs:$src1),
117 (A2_tfrsi 0x01010101))))>,
118 Requires<[UseHVXSgl]>;
119
120def : Pat <(v512i1 (load (i32 IntRegs:$addr))),
121 (v512i1 (V6_vandvrt
122 (v16i32 (V6_vL32b_ai IntRegs:$addr, 0)), (A2_tfrsi 0x01010101)))>,
123 Requires<[UseHVXSgl]>;
124
125def : Pat <(store (v1024i1 VecPredRegs128B:$src1), (i32 IntRegs:$addr)),
126 (V6_vS32b_ai_128B IntRegs:$addr, 0,
127 (v32i32 (V6_vandqrt_128B (v1024i1 VecPredRegs128B:$src1),
128 (A2_tfrsi 0x01010101))))>,
129 Requires<[UseHVXDbl]>;
130
131def : Pat <(v1024i1 (load (i32 IntRegs:$addr))),
132 (v1024i1 (V6_vandvrt_128B
133 (v32i32 (V6_vL32b_ai_128B IntRegs:$addr, 0)),
134 (A2_tfrsi 0x01010101)))>,
135 Requires<[UseHVXDbl]>;
136}
137
138multiclass T_R_pat <InstHexagon MI, Intrinsic IntID> {
139 def: Pat<(IntID IntRegs:$src1), (MI IntRegs:$src1)>,
140 Requires<[UseHVXSgl]>;
141 def: Pat<(!cast<Intrinsic>(IntID#"_128B") IntRegs:$src1),
142 (!cast<InstHexagon>(MI#"_128B") IntRegs:$src1)>,
143 Requires<[UseHVXDbl]>;
144}
145
146multiclass T_V_pat <InstHexagon MI, Intrinsic IntID> {
147 def: Pat<(IntID VectorRegs:$src1),
148 (MI VectorRegs:$src1)>,
149 Requires<[UseHVXSgl]>;
150
151 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1),
152 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1)>,
153 Requires<[UseHVXDbl]>;
154}
155
Krzysztof Parzyszekeabc0d02016-08-16 17:14:44 +0000[diff] [blame]156multiclass T_W_pat <InstHexagon MI, Intrinsic IntID> {
157 def: Pat<(IntID VecDblRegs:$src1),
158 (MI VecDblRegs:$src1)>,
159 Requires<[UseHVXSgl]>;
160
161 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1),
162 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1)>,
163 Requires<[UseHVXDbl]>;
164}
165
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]166multiclass T_Q_pat <InstHexagon MI, Intrinsic IntID> {
167 def: Pat<(IntID VecPredRegs:$src1),
168 (MI VecPredRegs:$src1)>,
169 Requires<[UseHVXSgl]>;
170
171 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1),
172 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1)>,
173 Requires<[UseHVXDbl]>;
174}
175
176multiclass T_WR_pat <InstHexagon MI, Intrinsic IntID> {
177 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2),
178 (MI VecDblRegs:$src1, IntRegs:$src2)>,
179 Requires<[UseHVXSgl]>;
180
181 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VecDblRegs128B:$src1, IntRegs:$src2),
182 (!cast<InstHexagon>(MI#"_128B")VecDblRegs128B:$src1, IntRegs:$src2)>,
183 Requires<[UseHVXDbl]>;
184}
185
186multiclass T_VR_pat <InstHexagon MI, Intrinsic IntID> {
187 def: Pat<(IntID VectorRegs:$src1, IntRegs:$src2),
188 (MI VectorRegs:$src1, IntRegs:$src2)>,
189 Requires<[UseHVXSgl]>;
190
191 def: Pat<(!cast<Intrinsic>(IntID#"_128B")VectorRegs128B:$src1, IntRegs:$src2),
192 (!cast<InstHexagon>(MI#"_128B")VectorRegs128B:$src1, IntRegs:$src2)>,
193 Requires<[UseHVXDbl]>;
194}
195
196multiclass T_WV_pat <InstHexagon MI, Intrinsic IntID> {
197 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2),
198 (MI VecDblRegs:$src1, VectorRegs:$src2)>,
199 Requires<[UseHVXSgl]>;
200
201 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
202 VectorRegs128B:$src2),
203 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
204 VectorRegs128B:$src2)>,
205 Requires<[UseHVXDbl]>;
206}
207
208multiclass T_WW_pat <InstHexagon MI, Intrinsic IntID> {
209 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2),
210 (MI VecDblRegs:$src1, VecDblRegs:$src2)>,
211 Requires<[UseHVXSgl]>;
212
213 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
214 VecDblRegs128B:$src2),
215 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
216 VecDblRegs128B:$src2)>,
217 Requires<[UseHVXDbl]>;
218}
219
220multiclass T_VV_pat <InstHexagon MI, Intrinsic IntID> {
221 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2),
222 (MI VectorRegs:$src1, VectorRegs:$src2)>,
223 Requires<[UseHVXSgl]>;
224
225 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
226 VectorRegs128B:$src2),
227 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
228 VectorRegs128B:$src2)>,
229 Requires<[UseHVXDbl]>;
230}
231
232multiclass T_QR_pat <InstHexagon MI, Intrinsic IntID> {
233 def: Pat<(IntID VecPredRegs:$src1, IntRegs:$src2),
234 (MI VecPredRegs:$src1, IntRegs:$src2)>,
235 Requires<[UseHVXSgl]>;
236
237 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
238 IntRegs:$src2),
239 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
240 IntRegs:$src2)>,
241 Requires<[UseHVXDbl]>;
242}
243
244multiclass T_QQ_pat <InstHexagon MI, Intrinsic IntID> {
245 def: Pat<(IntID VecPredRegs:$src1, VecPredRegs:$src2),
246 (MI VecPredRegs:$src1, VecPredRegs:$src2)>,
247 Requires<[UseHVXSgl]>;
248
249 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
250 VecPredRegs128B:$src2),
251 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
252 VecPredRegs128B:$src2)>,
253 Requires<[UseHVXDbl]>;
254}
255
256multiclass T_WWR_pat <InstHexagon MI, Intrinsic IntID> {
257 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
258 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
259 Requires<[UseHVXSgl]>;
260
261 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
262 VecDblRegs128B:$src2,
263 IntRegs:$src3),
264 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
265 VecDblRegs128B:$src2,
266 IntRegs:$src3)>,
267 Requires<[UseHVXDbl]>;
268}
269
270multiclass T_VVR_pat <InstHexagon MI, Intrinsic IntID> {
271 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
272 (MI VectorRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
273 Requires<[UseHVXSgl]>;
274
275 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
276 VectorRegs128B:$src2,
277 IntRegs:$src3),
278 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
279 VectorRegs128B:$src2,
280 IntRegs:$src3)>,
281 Requires<[UseHVXDbl]>;
282}
283
284multiclass T_WVR_pat <InstHexagon MI, Intrinsic IntID> {
285 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
286 (MI VecDblRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
287 Requires<[UseHVXSgl]>;
288
289 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
290 VectorRegs128B:$src2,
291 IntRegs:$src3),
292 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
293 VectorRegs128B:$src2,
294 IntRegs:$src3)>,
295 Requires<[UseHVXDbl]>;
296}
297
298multiclass T_VWR_pat <InstHexagon MI, Intrinsic IntID> {
299 def: Pat<(IntID VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3),
300 (MI VectorRegs:$src1, VecDblRegs:$src2, IntRegs:$src3)>,
301 Requires<[UseHVXSgl]>;
302
303 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
304 VecDblRegs128B:$src2,
305 IntRegs:$src3),
306 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
307 VecDblRegs128B:$src2,
308 IntRegs:$src3)>,
309 Requires<[UseHVXDbl]>;
310}
311
312multiclass T_VVV_pat <InstHexagon MI, Intrinsic IntID> {
313 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
314 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
315 Requires<[UseHVXSgl]>;
316
317 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
318 VectorRegs128B:$src2,
319 VectorRegs128B:$src3),
320 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
321 VectorRegs128B:$src2,
322 VectorRegs128B:$src3)>,
323 Requires<[UseHVXDbl]>;
324}
325
326multiclass T_WVV_pat <InstHexagon MI, Intrinsic IntID> {
327 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
328 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
329 Requires<[UseHVXSgl]>;
330
331 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
332 VectorRegs128B:$src2,
333 VectorRegs128B:$src3),
334 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
335 VectorRegs128B:$src2,
336 VectorRegs128B:$src3)>,
337 Requires<[UseHVXDbl]>;
338}
339
340multiclass T_QVV_pat <InstHexagon MI, Intrinsic IntID> {
341 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3),
342 (MI VecPredRegs:$src1, VectorRegs:$src2, VectorRegs:$src3)>,
343 Requires<[UseHVXSgl]>;
344
345 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
346 VectorRegs128B:$src2,
347 VectorRegs128B:$src3),
348 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
349 VectorRegs128B:$src2,
350 VectorRegs128B:$src3)>,
351 Requires<[UseHVXDbl]>;
352}
353
354multiclass T_VQR_pat <InstHexagon MI, Intrinsic IntID> {
355 def: Pat<(IntID VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3),
356 (MI VectorRegs:$src1, VecPredRegs:$src2, IntRegs:$src3)>,
357 Requires<[UseHVXSgl]>;
358
359 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
360 VecPredRegs128B:$src2,
361 IntRegs:$src3),
362 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
363 VecPredRegs128B:$src2,
364 IntRegs:$src3)>,
365 Requires<[UseHVXDbl]>;
366}
367
368
369multiclass T_QVR_pat <InstHexagon MI, Intrinsic IntID> {
370 def: Pat<(IntID VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3),
371 (MI VecPredRegs:$src1, VectorRegs:$src2, IntRegs:$src3)>,
372 Requires<[UseHVXSgl]>;
373
374 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecPredRegs128B:$src1,
375 VectorRegs128B:$src2,
376 IntRegs:$src3),
377 (!cast<InstHexagon>(MI#"_128B") VecPredRegs128B:$src1,
378 VectorRegs128B:$src2,
379 IntRegs:$src3)>,
380 Requires<[UseHVXDbl]>;
381}
382
383multiclass T_VVI_pat <InstHexagon MI, Intrinsic IntID> {
384 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, imm:$src3),
385 (MI VectorRegs:$src1, VectorRegs:$src2, imm:$src3)>,
386 Requires<[UseHVXSgl]>;
387
388 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
389 VectorRegs128B:$src2, imm:$src3),
390 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
391 VectorRegs128B:$src2, imm:$src3)>,
392 Requires<[UseHVXDbl]>;
393}
394
395multiclass T_WRI_pat <InstHexagon MI, Intrinsic IntID> {
396 def: Pat<(IntID VecDblRegs:$src1, IntRegs:$src2, imm:$src3),
397 (MI VecDblRegs:$src1, IntRegs:$src2, imm:$src3)>,
398 Requires<[UseHVXSgl]>;
399
400 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
401 IntRegs:$src2, imm:$src3),
402 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
403 IntRegs:$src2, imm:$src3)>,
404 Requires<[UseHVXDbl]>;
405}
406
407multiclass T_WWRI_pat <InstHexagon MI, Intrinsic IntID> {
408 def: Pat<(IntID VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4),
409 (MI VecDblRegs:$src1, VecDblRegs:$src2, IntRegs:$src3, imm:$src4)>,
410 Requires<[UseHVXSgl]>;
411
412 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
413 VecDblRegs128B:$src2,
414 IntRegs:$src3, imm:$src4),
415 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
416 VecDblRegs128B:$src2,
417 IntRegs:$src3, imm:$src4)>,
418 Requires<[UseHVXDbl]>;
419}
420
421multiclass T_VVVR_pat <InstHexagon MI, Intrinsic IntID> {
422 def: Pat<(IntID VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
423 IntRegs:$src4),
424 (MI VectorRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
425 IntRegs:$src4)>,
426 Requires<[UseHVXSgl]>;
427
428 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VectorRegs128B:$src1,
429 VectorRegs128B:$src2,
430 VectorRegs128B:$src3,
431 IntRegs:$src4),
432 (!cast<InstHexagon>(MI#"_128B") VectorRegs128B:$src1,
433 VectorRegs128B:$src2,
434 VectorRegs128B:$src3,
435 IntRegs:$src4)>,
436 Requires<[UseHVXDbl]>;
437}
438
439multiclass T_WVVR_pat <InstHexagon MI, Intrinsic IntID> {
440 def: Pat<(IntID VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
441 IntRegs:$src4),
442 (MI VecDblRegs:$src1, VectorRegs:$src2, VectorRegs:$src3,
443 IntRegs:$src4)>,
444 Requires<[UseHVXSgl]>;
445
446 def: Pat<(!cast<Intrinsic>(IntID#"_128B") VecDblRegs128B:$src1,
447 VectorRegs128B:$src2,
448 VectorRegs128B:$src3,
449 IntRegs:$src4),
450 (!cast<InstHexagon>(MI#"_128B") VecDblRegs128B:$src1,
451 VectorRegs128B:$src2,
452 VectorRegs128B:$src3,
453 IntRegs:$src4)>,
454 Requires<[UseHVXDbl]>;
455}
456
Krzysztof Parzyszekeabc0d02016-08-16 17:14:44 +0000[diff] [blame]457defm : T_WR_pat <V6_vtmpyb, int_hexagon_V6_vtmpyb>;
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]458defm : T_WR_pat <V6_vtmpybus, int_hexagon_V6_vtmpybus>;
459defm : T_VR_pat <V6_vdmpyhb, int_hexagon_V6_vdmpyhb>;
460defm : T_VR_pat <V6_vrmpyub, int_hexagon_V6_vrmpyub>;
461defm : T_VR_pat <V6_vrmpybus, int_hexagon_V6_vrmpybus>;
462defm : T_WR_pat <V6_vdsaduh, int_hexagon_V6_vdsaduh>;
463defm : T_VR_pat <V6_vdmpybus, int_hexagon_V6_vdmpybus>;
464defm : T_WR_pat <V6_vdmpybus_dv, int_hexagon_V6_vdmpybus_dv>;
465defm : T_VR_pat <V6_vdmpyhsusat, int_hexagon_V6_vdmpyhsusat>;
466defm : T_WR_pat <V6_vdmpyhsuisat, int_hexagon_V6_vdmpyhsuisat>;
467defm : T_VR_pat <V6_vdmpyhsat, int_hexagon_V6_vdmpyhsat>;
468defm : T_WR_pat <V6_vdmpyhisat, int_hexagon_V6_vdmpyhisat>;
469defm : T_WR_pat <V6_vdmpyhb_dv, int_hexagon_V6_vdmpyhb_dv>;
470defm : T_VR_pat <V6_vmpybus, int_hexagon_V6_vmpybus>;
471defm : T_WR_pat <V6_vmpabus, int_hexagon_V6_vmpabus>;
472defm : T_WR_pat <V6_vmpahb, int_hexagon_V6_vmpahb>;
473defm : T_VR_pat <V6_vmpyh, int_hexagon_V6_vmpyh>;
474defm : T_VR_pat <V6_vmpyhss, int_hexagon_V6_vmpyhss>;
475defm : T_VR_pat <V6_vmpyhsrs, int_hexagon_V6_vmpyhsrs>;
476defm : T_VR_pat <V6_vmpyuh, int_hexagon_V6_vmpyuh>;
477defm : T_VR_pat <V6_vmpyihb, int_hexagon_V6_vmpyihb>;
478defm : T_VR_pat <V6_vror, int_hexagon_V6_vror>;
479defm : T_VR_pat <V6_vasrw, int_hexagon_V6_vasrw>;
480defm : T_VR_pat <V6_vasrh, int_hexagon_V6_vasrh>;
481defm : T_VR_pat <V6_vaslw, int_hexagon_V6_vaslw>;
482defm : T_VR_pat <V6_vaslh, int_hexagon_V6_vaslh>;
483defm : T_VR_pat <V6_vlsrw, int_hexagon_V6_vlsrw>;
484defm : T_VR_pat <V6_vlsrh, int_hexagon_V6_vlsrh>;
485defm : T_VR_pat <V6_vmpyiwh, int_hexagon_V6_vmpyiwh>;
486defm : T_VR_pat <V6_vmpyiwb, int_hexagon_V6_vmpyiwb>;
487defm : T_WR_pat <V6_vtmpyhb, int_hexagon_V6_vtmpyhb>;
488defm : T_VR_pat <V6_vmpyub, int_hexagon_V6_vmpyub>;
489
490defm : T_VV_pat <V6_vrmpyubv, int_hexagon_V6_vrmpyubv>;
491defm : T_VV_pat <V6_vrmpybv, int_hexagon_V6_vrmpybv>;
492defm : T_VV_pat <V6_vrmpybusv, int_hexagon_V6_vrmpybusv>;
493defm : T_VV_pat <V6_vdmpyhvsat, int_hexagon_V6_vdmpyhvsat>;
494defm : T_VV_pat <V6_vmpybv, int_hexagon_V6_vmpybv>;
495defm : T_VV_pat <V6_vmpyubv, int_hexagon_V6_vmpyubv>;
496defm : T_VV_pat <V6_vmpybusv, int_hexagon_V6_vmpybusv>;
497defm : T_VV_pat <V6_vmpyhv, int_hexagon_V6_vmpyhv>;
498defm : T_VV_pat <V6_vmpyuhv, int_hexagon_V6_vmpyuhv>;
499defm : T_VV_pat <V6_vmpyhvsrs, int_hexagon_V6_vmpyhvsrs>;
500defm : T_VV_pat <V6_vmpyhus, int_hexagon_V6_vmpyhus>;
501defm : T_WW_pat <V6_vmpabusv, int_hexagon_V6_vmpabusv>;
502defm : T_VV_pat <V6_vmpyih, int_hexagon_V6_vmpyih>;
503defm : T_VV_pat <V6_vand, int_hexagon_V6_vand>;
504defm : T_VV_pat <V6_vor, int_hexagon_V6_vor>;
505defm : T_VV_pat <V6_vxor, int_hexagon_V6_vxor>;
506defm : T_VV_pat <V6_vaddw, int_hexagon_V6_vaddw>;
507defm : T_VV_pat <V6_vaddubsat, int_hexagon_V6_vaddubsat>;
508defm : T_VV_pat <V6_vadduhsat, int_hexagon_V6_vadduhsat>;
509defm : T_VV_pat <V6_vaddhsat, int_hexagon_V6_vaddhsat>;
510defm : T_VV_pat <V6_vaddwsat, int_hexagon_V6_vaddwsat>;
511defm : T_VV_pat <V6_vsubb, int_hexagon_V6_vsubb>;
512defm : T_VV_pat <V6_vsubh, int_hexagon_V6_vsubh>;
513defm : T_VV_pat <V6_vsubw, int_hexagon_V6_vsubw>;
514defm : T_VV_pat <V6_vsububsat, int_hexagon_V6_vsububsat>;
515defm : T_VV_pat <V6_vsubuhsat, int_hexagon_V6_vsubuhsat>;
516defm : T_VV_pat <V6_vsubhsat, int_hexagon_V6_vsubhsat>;
517defm : T_VV_pat <V6_vsubwsat, int_hexagon_V6_vsubwsat>;
518defm : T_WW_pat <V6_vaddb_dv, int_hexagon_V6_vaddb_dv>;
519defm : T_WW_pat <V6_vaddh_dv, int_hexagon_V6_vaddh_dv>;
520defm : T_WW_pat <V6_vaddw_dv, int_hexagon_V6_vaddw_dv>;
521defm : T_WW_pat <V6_vaddubsat_dv, int_hexagon_V6_vaddubsat_dv>;
522defm : T_WW_pat <V6_vadduhsat_dv, int_hexagon_V6_vadduhsat_dv>;
523defm : T_WW_pat <V6_vaddhsat_dv, int_hexagon_V6_vaddhsat_dv>;
524defm : T_WW_pat <V6_vaddwsat_dv, int_hexagon_V6_vaddwsat_dv>;
525defm : T_WW_pat <V6_vsubb_dv, int_hexagon_V6_vsubb_dv>;
526defm : T_WW_pat <V6_vsubh_dv, int_hexagon_V6_vsubh_dv>;
527defm : T_WW_pat <V6_vsubw_dv, int_hexagon_V6_vsubw_dv>;
528defm : T_WW_pat <V6_vsububsat_dv, int_hexagon_V6_vsububsat_dv>;
529defm : T_WW_pat <V6_vsubuhsat_dv, int_hexagon_V6_vsubuhsat_dv>;
530defm : T_WW_pat <V6_vsubhsat_dv, int_hexagon_V6_vsubhsat_dv>;
531defm : T_WW_pat <V6_vsubwsat_dv, int_hexagon_V6_vsubwsat_dv>;
532defm : T_VV_pat <V6_vaddubh, int_hexagon_V6_vaddubh>;
533defm : T_VV_pat <V6_vadduhw, int_hexagon_V6_vadduhw>;
534defm : T_VV_pat <V6_vaddhw, int_hexagon_V6_vaddhw>;
535defm : T_VV_pat <V6_vsububh, int_hexagon_V6_vsububh>;
536defm : T_VV_pat <V6_vsubuhw, int_hexagon_V6_vsubuhw>;
537defm : T_VV_pat <V6_vsubhw, int_hexagon_V6_vsubhw>;
538defm : T_VV_pat <V6_vabsdiffub, int_hexagon_V6_vabsdiffub>;
539defm : T_VV_pat <V6_vabsdiffh, int_hexagon_V6_vabsdiffh>;
540defm : T_VV_pat <V6_vabsdiffuh, int_hexagon_V6_vabsdiffuh>;
541defm : T_VV_pat <V6_vabsdiffw, int_hexagon_V6_vabsdiffw>;
542defm : T_VV_pat <V6_vavgub, int_hexagon_V6_vavgub>;
543defm : T_VV_pat <V6_vavguh, int_hexagon_V6_vavguh>;
544defm : T_VV_pat <V6_vavgh, int_hexagon_V6_vavgh>;
545defm : T_VV_pat <V6_vavgw, int_hexagon_V6_vavgw>;
546defm : T_VV_pat <V6_vnavgub, int_hexagon_V6_vnavgub>;
547defm : T_VV_pat <V6_vnavgh, int_hexagon_V6_vnavgh>;
548defm : T_VV_pat <V6_vnavgw, int_hexagon_V6_vnavgw>;
549defm : T_VV_pat <V6_vavgubrnd, int_hexagon_V6_vavgubrnd>;
550defm : T_VV_pat <V6_vavguhrnd, int_hexagon_V6_vavguhrnd>;
551defm : T_VV_pat <V6_vavghrnd, int_hexagon_V6_vavghrnd>;
552defm : T_VV_pat <V6_vavgwrnd, int_hexagon_V6_vavgwrnd>;
553defm : T_WW_pat <V6_vmpabuuv, int_hexagon_V6_vmpabuuv>;
554
555defm : T_VVR_pat <V6_vdmpyhb_acc, int_hexagon_V6_vdmpyhb_acc>;
556defm : T_VVR_pat <V6_vrmpyub_acc, int_hexagon_V6_vrmpyub_acc>;
557defm : T_VVR_pat <V6_vrmpybus_acc, int_hexagon_V6_vrmpybus_acc>;
558defm : T_VVR_pat <V6_vdmpybus_acc, int_hexagon_V6_vdmpybus_acc>;
559defm : T_VVR_pat <V6_vdmpyhsusat_acc, int_hexagon_V6_vdmpyhsusat_acc>;
560defm : T_VVR_pat <V6_vdmpyhsat_acc, int_hexagon_V6_vdmpyhsat_acc>;
561defm : T_VVR_pat <V6_vmpyiwb_acc, int_hexagon_V6_vmpyiwb_acc>;
562defm : T_VVR_pat <V6_vmpyiwh_acc, int_hexagon_V6_vmpyiwh_acc>;
563defm : T_VVR_pat <V6_vmpyihb_acc, int_hexagon_V6_vmpyihb_acc>;
564defm : T_VVR_pat <V6_vaslw_acc, int_hexagon_V6_vaslw_acc>;
565defm : T_VVR_pat <V6_vasrw_acc, int_hexagon_V6_vasrw_acc>;
566
567defm : T_VWR_pat <V6_vdmpyhsuisat_acc, int_hexagon_V6_vdmpyhsuisat_acc>;
568defm : T_VWR_pat <V6_vdmpyhisat_acc, int_hexagon_V6_vdmpyhisat_acc>;
569
570defm : T_WVR_pat <V6_vmpybus_acc, int_hexagon_V6_vmpybus_acc>;
571defm : T_WVR_pat <V6_vmpyhsat_acc, int_hexagon_V6_vmpyhsat_acc>;
572defm : T_WVR_pat <V6_vmpyuh_acc, int_hexagon_V6_vmpyuh_acc>;
573defm : T_WVR_pat <V6_vmpyub_acc, int_hexagon_V6_vmpyub_acc>;
574
575defm : T_WWR_pat <V6_vtmpyb_acc, int_hexagon_V6_vtmpyb_acc>;
576defm : T_WWR_pat <V6_vtmpybus_acc, int_hexagon_V6_vtmpybus_acc>;
577defm : T_WWR_pat <V6_vtmpyhb_acc, int_hexagon_V6_vtmpyhb_acc>;
578defm : T_WWR_pat <V6_vdmpybus_dv_acc, int_hexagon_V6_vdmpybus_dv_acc>;
579defm : T_WWR_pat <V6_vdmpyhb_dv_acc, int_hexagon_V6_vdmpyhb_dv_acc>;
580defm : T_WWR_pat <V6_vmpabus_acc, int_hexagon_V6_vmpabus_acc>;
581defm : T_WWR_pat <V6_vmpahb_acc, int_hexagon_V6_vmpahb_acc>;
582defm : T_WWR_pat <V6_vdsaduh_acc, int_hexagon_V6_vdsaduh_acc>;
583
584defm : T_VVV_pat <V6_vdmpyhvsat_acc, int_hexagon_V6_vdmpyhvsat_acc>;
585defm : T_WVV_pat <V6_vmpybusv_acc, int_hexagon_V6_vmpybusv_acc>;
586defm : T_WVV_pat <V6_vmpybv_acc, int_hexagon_V6_vmpybv_acc>;
587defm : T_WVV_pat <V6_vmpyhus_acc, int_hexagon_V6_vmpyhus_acc>;
588defm : T_WVV_pat <V6_vmpyhv_acc, int_hexagon_V6_vmpyhv_acc>;
589defm : T_VVV_pat <V6_vmpyiewh_acc, int_hexagon_V6_vmpyiewh_acc>;
590defm : T_VVV_pat <V6_vmpyiewuh_acc, int_hexagon_V6_vmpyiewuh_acc>;
591defm : T_VVV_pat <V6_vmpyih_acc, int_hexagon_V6_vmpyih_acc>;
592defm : T_VVV_pat <V6_vmpyowh_rnd_sacc, int_hexagon_V6_vmpyowh_rnd_sacc>;
593defm : T_VVV_pat <V6_vmpyowh_sacc, int_hexagon_V6_vmpyowh_sacc>;
594defm : T_WVV_pat <V6_vmpyubv_acc, int_hexagon_V6_vmpyubv_acc>;
595defm : T_WVV_pat <V6_vmpyuhv_acc, int_hexagon_V6_vmpyuhv_acc>;
596defm : T_VVV_pat <V6_vrmpybusv_acc, int_hexagon_V6_vrmpybusv_acc>;
597defm : T_VVV_pat <V6_vrmpybv_acc, int_hexagon_V6_vrmpybv_acc>;
598defm : T_VVV_pat <V6_vrmpyubv_acc, int_hexagon_V6_vrmpyubv_acc>;
599
600// Compare instructions
601defm : T_QVV_pat <V6_veqb_and, int_hexagon_V6_veqb_and>;
602defm : T_QVV_pat <V6_veqh_and, int_hexagon_V6_veqh_and>;
603defm : T_QVV_pat <V6_veqw_and, int_hexagon_V6_veqw_and>;
604defm : T_QVV_pat <V6_vgtb_and, int_hexagon_V6_vgtb_and>;
605defm : T_QVV_pat <V6_vgth_and, int_hexagon_V6_vgth_and>;
606defm : T_QVV_pat <V6_vgtw_and, int_hexagon_V6_vgtw_and>;
607defm : T_QVV_pat <V6_vgtub_and, int_hexagon_V6_vgtub_and>;
608defm : T_QVV_pat <V6_vgtuh_and, int_hexagon_V6_vgtuh_and>;
609defm : T_QVV_pat <V6_vgtuw_and, int_hexagon_V6_vgtuw_and>;
610defm : T_QVV_pat <V6_veqb_or, int_hexagon_V6_veqb_or>;
611defm : T_QVV_pat <V6_veqh_or, int_hexagon_V6_veqh_or>;
612defm : T_QVV_pat <V6_veqw_or, int_hexagon_V6_veqw_or>;
613defm : T_QVV_pat <V6_vgtb_or, int_hexagon_V6_vgtb_or>;
614defm : T_QVV_pat <V6_vgth_or, int_hexagon_V6_vgth_or>;
615defm : T_QVV_pat <V6_vgtw_or, int_hexagon_V6_vgtw_or>;
616defm : T_QVV_pat <V6_vgtub_or, int_hexagon_V6_vgtub_or>;
617defm : T_QVV_pat <V6_vgtuh_or, int_hexagon_V6_vgtuh_or>;
618defm : T_QVV_pat <V6_vgtuw_or, int_hexagon_V6_vgtuw_or>;
619defm : T_QVV_pat <V6_veqb_xor, int_hexagon_V6_veqb_xor>;
620defm : T_QVV_pat <V6_veqh_xor, int_hexagon_V6_veqh_xor>;
621defm : T_QVV_pat <V6_veqw_xor, int_hexagon_V6_veqw_xor>;
622defm : T_QVV_pat <V6_vgtb_xor, int_hexagon_V6_vgtb_xor>;
623defm : T_QVV_pat <V6_vgth_xor, int_hexagon_V6_vgth_xor>;
624defm : T_QVV_pat <V6_vgtw_xor, int_hexagon_V6_vgtw_xor>;
625defm : T_QVV_pat <V6_vgtub_xor, int_hexagon_V6_vgtub_xor>;
626defm : T_QVV_pat <V6_vgtuh_xor, int_hexagon_V6_vgtuh_xor>;
627defm : T_QVV_pat <V6_vgtuw_xor, int_hexagon_V6_vgtuw_xor>;
628
629defm : T_VV_pat <V6_vminub, int_hexagon_V6_vminub>;
630defm : T_VV_pat <V6_vminuh, int_hexagon_V6_vminuh>;
631defm : T_VV_pat <V6_vminh, int_hexagon_V6_vminh>;
632defm : T_VV_pat <V6_vminw, int_hexagon_V6_vminw>;
633defm : T_VV_pat <V6_vmaxub, int_hexagon_V6_vmaxub>;
634defm : T_VV_pat <V6_vmaxuh, int_hexagon_V6_vmaxuh>;
635defm : T_VV_pat <V6_vmaxh, int_hexagon_V6_vmaxh>;
636defm : T_VV_pat <V6_vmaxw, int_hexagon_V6_vmaxw>;
637defm : T_VV_pat <V6_vdelta, int_hexagon_V6_vdelta>;
638defm : T_VV_pat <V6_vrdelta, int_hexagon_V6_vrdelta>;
639defm : T_VV_pat <V6_vdealb4w, int_hexagon_V6_vdealb4w>;
640defm : T_VV_pat <V6_vmpyowh_rnd, int_hexagon_V6_vmpyowh_rnd>;
641defm : T_VV_pat <V6_vshuffeb, int_hexagon_V6_vshuffeb>;
642defm : T_VV_pat <V6_vshuffob, int_hexagon_V6_vshuffob>;
643defm : T_VV_pat <V6_vshufeh, int_hexagon_V6_vshufeh>;
644defm : T_VV_pat <V6_vshufoh, int_hexagon_V6_vshufoh>;
645defm : T_VV_pat <V6_vshufoeh, int_hexagon_V6_vshufoeh>;
646defm : T_VV_pat <V6_vshufoeb, int_hexagon_V6_vshufoeb>;
647defm : T_VV_pat <V6_vcombine, int_hexagon_V6_vcombine>;
648defm : T_VV_pat <V6_vmpyieoh, int_hexagon_V6_vmpyieoh>;
649defm : T_VV_pat <V6_vsathub, int_hexagon_V6_vsathub>;
650defm : T_VV_pat <V6_vsatwh, int_hexagon_V6_vsatwh>;
651defm : T_VV_pat <V6_vroundwh, int_hexagon_V6_vroundwh>;
652defm : T_VV_pat <V6_vroundwuh, int_hexagon_V6_vroundwuh>;
653defm : T_VV_pat <V6_vroundhb, int_hexagon_V6_vroundhb>;
654defm : T_VV_pat <V6_vroundhub, int_hexagon_V6_vroundhub>;
655defm : T_VV_pat <V6_vasrwv, int_hexagon_V6_vasrwv>;
656defm : T_VV_pat <V6_vlsrwv, int_hexagon_V6_vlsrwv>;
657defm : T_VV_pat <V6_vlsrhv, int_hexagon_V6_vlsrhv>;
658defm : T_VV_pat <V6_vasrhv, int_hexagon_V6_vasrhv>;
659defm : T_VV_pat <V6_vaslwv, int_hexagon_V6_vaslwv>;
660defm : T_VV_pat <V6_vaslhv, int_hexagon_V6_vaslhv>;
661defm : T_VV_pat <V6_vaddb, int_hexagon_V6_vaddb>;
662defm : T_VV_pat <V6_vaddh, int_hexagon_V6_vaddh>;
663defm : T_VV_pat <V6_vmpyiewuh, int_hexagon_V6_vmpyiewuh>;
664defm : T_VV_pat <V6_vmpyiowh, int_hexagon_V6_vmpyiowh>;
665defm : T_VV_pat <V6_vpackeb, int_hexagon_V6_vpackeb>;
666defm : T_VV_pat <V6_vpackeh, int_hexagon_V6_vpackeh>;
667defm : T_VV_pat <V6_vpackhub_sat, int_hexagon_V6_vpackhub_sat>;
668defm : T_VV_pat <V6_vpackhb_sat, int_hexagon_V6_vpackhb_sat>;
669defm : T_VV_pat <V6_vpackwuh_sat, int_hexagon_V6_vpackwuh_sat>;
670defm : T_VV_pat <V6_vpackwh_sat, int_hexagon_V6_vpackwh_sat>;
671defm : T_VV_pat <V6_vpackob, int_hexagon_V6_vpackob>;
672defm : T_VV_pat <V6_vpackoh, int_hexagon_V6_vpackoh>;
673defm : T_VV_pat <V6_vmpyewuh, int_hexagon_V6_vmpyewuh>;
674defm : T_VV_pat <V6_vmpyowh, int_hexagon_V6_vmpyowh>;
675
676defm : T_QVV_pat <V6_vaddbq, int_hexagon_V6_vaddbq>;
677defm : T_QVV_pat <V6_vaddhq, int_hexagon_V6_vaddhq>;
678defm : T_QVV_pat <V6_vaddwq, int_hexagon_V6_vaddwq>;
679defm : T_QVV_pat <V6_vaddbnq, int_hexagon_V6_vaddbnq>;
680defm : T_QVV_pat <V6_vaddhnq, int_hexagon_V6_vaddhnq>;
681defm : T_QVV_pat <V6_vaddwnq, int_hexagon_V6_vaddwnq>;
682defm : T_QVV_pat <V6_vsubbq, int_hexagon_V6_vsubbq>;
683defm : T_QVV_pat <V6_vsubhq, int_hexagon_V6_vsubhq>;
684defm : T_QVV_pat <V6_vsubwq, int_hexagon_V6_vsubwq>;
685defm : T_QVV_pat <V6_vsubbnq, int_hexagon_V6_vsubbnq>;
686defm : T_QVV_pat <V6_vsubhnq, int_hexagon_V6_vsubhnq>;
687defm : T_QVV_pat <V6_vsubwnq, int_hexagon_V6_vsubwnq>;
688
689defm : T_V_pat <V6_vabsh, int_hexagon_V6_vabsh>;
690defm : T_V_pat <V6_vabsw, int_hexagon_V6_vabsw>;
691defm : T_V_pat <V6_vabsw_sat, int_hexagon_V6_vabsw_sat>;
692defm : T_V_pat <V6_vabsh_sat, int_hexagon_V6_vabsh_sat>;
693defm : T_V_pat <V6_vnot, int_hexagon_V6_vnot>;
694defm : T_V_pat <V6_vassign, int_hexagon_V6_vassign>;
695defm : T_V_pat <V6_vzb, int_hexagon_V6_vzb>;
696defm : T_V_pat <V6_vzh, int_hexagon_V6_vzh>;
697defm : T_V_pat <V6_vsb, int_hexagon_V6_vsb>;
698defm : T_V_pat <V6_vsh, int_hexagon_V6_vsh>;
699defm : T_V_pat <V6_vdealh, int_hexagon_V6_vdealh>;
700defm : T_V_pat <V6_vdealb, int_hexagon_V6_vdealb>;
701defm : T_V_pat <V6_vunpackub, int_hexagon_V6_vunpackub>;
702defm : T_V_pat <V6_vunpackuh, int_hexagon_V6_vunpackuh>;
703defm : T_V_pat <V6_vunpackb, int_hexagon_V6_vunpackb>;
704defm : T_V_pat <V6_vunpackh, int_hexagon_V6_vunpackh>;
705defm : T_V_pat <V6_vshuffh, int_hexagon_V6_vshuffh>;
706defm : T_V_pat <V6_vshuffb, int_hexagon_V6_vshuffb>;
707defm : T_V_pat <V6_vcl0w, int_hexagon_V6_vcl0w>;
708defm : T_V_pat <V6_vpopcounth, int_hexagon_V6_vpopcounth>;
709defm : T_V_pat <V6_vcl0h, int_hexagon_V6_vcl0h>;
710defm : T_V_pat <V6_vnormamtw, int_hexagon_V6_vnormamtw>;
711defm : T_V_pat <V6_vnormamth, int_hexagon_V6_vnormamth>;
712
Krzysztof Parzyszekeabc0d02016-08-16 17:14:44 +0000[diff] [blame]713defm : T_W_pat <V6_lo, int_hexagon_V6_lo>;
714defm : T_W_pat <V6_hi, int_hexagon_V6_hi>;
715defm : T_W_pat <V6_vassignp, int_hexagon_V6_vassignp>;
716
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]717defm : T_WRI_pat <V6_vrmpybusi, int_hexagon_V6_vrmpybusi>;
718defm : T_WRI_pat <V6_vrsadubi, int_hexagon_V6_vrsadubi>;
719defm : T_WRI_pat <V6_vrmpyubi, int_hexagon_V6_vrmpyubi>;
720
721defm : T_WWRI_pat <V6_vrmpybusi_acc, int_hexagon_V6_vrmpybusi_acc>;
722defm : T_WWRI_pat <V6_vrsadubi_acc, int_hexagon_V6_vrsadubi_acc>;
723defm : T_WWRI_pat <V6_vrmpyubi_acc, int_hexagon_V6_vrmpyubi_acc>;
724
725// assembler mapped.
726//defm : T_V_pat <V6_vtran2x2, int_hexagon_V6_vtran2x2>;
727// not present earlier.. need to add intrinsic
728defm : T_VVR_pat <V6_valignb, int_hexagon_V6_valignb>;
729defm : T_VVR_pat <V6_vlalignb, int_hexagon_V6_vlalignb>;
730defm : T_VVR_pat <V6_vasrwh, int_hexagon_V6_vasrwh>;
731defm : T_VVR_pat <V6_vasrwhsat, int_hexagon_V6_vasrwhsat>;
732defm : T_VVR_pat <V6_vasrwhrndsat, int_hexagon_V6_vasrwhrndsat>;
733defm : T_VVR_pat <V6_vasrwuhsat, int_hexagon_V6_vasrwuhsat>;
734defm : T_VVR_pat <V6_vasrhubsat, int_hexagon_V6_vasrhubsat>;
735defm : T_VVR_pat <V6_vasrhubrndsat, int_hexagon_V6_vasrhubrndsat>;
736defm : T_VVR_pat <V6_vasrhbrndsat, int_hexagon_V6_vasrhbrndsat>;
737
738defm : T_VVR_pat <V6_vshuffvdd, int_hexagon_V6_vshuffvdd>;
739defm : T_VVR_pat <V6_vdealvdd, int_hexagon_V6_vdealvdd>;
740
741defm : T_WV_pat <V6_vunpackob, int_hexagon_V6_vunpackob>;
742defm : T_WV_pat <V6_vunpackoh, int_hexagon_V6_vunpackoh>;
743defm : T_VVI_pat <V6_valignbi, int_hexagon_V6_valignbi>;
744defm : T_VVI_pat <V6_vlalignbi, int_hexagon_V6_vlalignbi>;
745
746defm : T_QVV_pat <V6_vswap, int_hexagon_V6_vswap>;
747defm : T_QVV_pat <V6_vmux, int_hexagon_V6_vmux>;
748defm : T_QQ_pat <V6_pred_and, int_hexagon_V6_pred_and>;
749defm : T_QQ_pat <V6_pred_or, int_hexagon_V6_pred_or>;
750defm : T_Q_pat <V6_pred_not, int_hexagon_V6_pred_not>;
751defm : T_QQ_pat <V6_pred_xor, int_hexagon_V6_pred_xor>;
752defm : T_QQ_pat <V6_pred_or_n, int_hexagon_V6_pred_or_n>;
753defm : T_QQ_pat <V6_pred_and_n, int_hexagon_V6_pred_and_n>;
754defm : T_VV_pat <V6_veqb, int_hexagon_V6_veqb>;
755defm : T_VV_pat <V6_veqh, int_hexagon_V6_veqh>;
756defm : T_VV_pat <V6_veqw, int_hexagon_V6_veqw>;
757defm : T_VV_pat <V6_vgtb, int_hexagon_V6_vgtb>;
758defm : T_VV_pat <V6_vgth, int_hexagon_V6_vgth>;
759defm : T_VV_pat <V6_vgtw, int_hexagon_V6_vgtw>;
760defm : T_VV_pat <V6_vgtub, int_hexagon_V6_vgtub>;
761defm : T_VV_pat <V6_vgtuh, int_hexagon_V6_vgtuh>;
762defm : T_VV_pat <V6_vgtuw, int_hexagon_V6_vgtuw>;
763
764defm : T_VQR_pat <V6_vandqrt_acc, int_hexagon_V6_vandqrt_acc>;
765defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
766defm : T_QR_pat <V6_vandqrt, int_hexagon_V6_vandqrt>;
767defm : T_R_pat <V6_lvsplatw, int_hexagon_V6_lvsplatw>;
Krzysztof Parzyszek040bb352016-04-22 18:05:55 +0000[diff] [blame]768defm : T_R_pat <V6_pred_scalar2, int_hexagon_V6_pred_scalar2>;
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]769defm : T_VR_pat <V6_vandvrt, int_hexagon_V6_vandvrt>;
770
771defm : T_VVR_pat <V6_vlutvvb, int_hexagon_V6_vlutvvb>;
772defm : T_VVR_pat <V6_vlutvwh, int_hexagon_V6_vlutvwh>;
773defm : T_VVVR_pat <V6_vlutvvb_oracc, int_hexagon_V6_vlutvvb_oracc>;
774defm : T_WVVR_pat <V6_vlutvwh_oracc, int_hexagon_V6_vlutvwh_oracc>;
775
776defm : T_QVR_pat <V6_vandvrt_acc, int_hexagon_V6_vandvrt_acc>;
777def : T_PI_pat <S6_rol_i_p, int_hexagon_S6_rol_i_p>;
778def : T_RI_pat <S6_rol_i_r, int_hexagon_S6_rol_i_r>;
779def : T_PPI_pat <S6_rol_i_p_nac, int_hexagon_S6_rol_i_p_nac>;
780def : T_PPI_pat <S6_rol_i_p_acc, int_hexagon_S6_rol_i_p_acc>;
781def : T_PPI_pat <S6_rol_i_p_and, int_hexagon_S6_rol_i_p_and>;
782def : T_PPI_pat <S6_rol_i_p_or, int_hexagon_S6_rol_i_p_or>;
783def : T_PPI_pat <S6_rol_i_p_xacc, int_hexagon_S6_rol_i_p_xacc>;
784def : T_RRI_pat <S6_rol_i_r_nac, int_hexagon_S6_rol_i_r_nac>;
785def : T_RRI_pat <S6_rol_i_r_acc, int_hexagon_S6_rol_i_r_acc>;
786def : T_RRI_pat <S6_rol_i_r_and, int_hexagon_S6_rol_i_r_and>;
787def : T_RRI_pat <S6_rol_i_r_or, int_hexagon_S6_rol_i_r_or>;
788def : T_RRI_pat <S6_rol_i_r_xacc, int_hexagon_S6_rol_i_r_xacc>;
789
790defm : T_VR_pat <V6_extractw, int_hexagon_V6_extractw>;
791defm : T_VR_pat <V6_vinsertwr, int_hexagon_V6_vinsertwr>;
792
Krzysztof Parzyszeka72fad92017-02-10 15:33:13 +0000[diff] [blame^]793//def : T_PPQ_pat <S2_cabacencbin, int_hexagon_S2_cabacencbin>;
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]794
795def: Pat<(v64i16 (trunc v64i32:$Vdd)),
796 (v64i16 (V6_vpackwh_sat_128B
Krzysztof Parzyszekeabc0d02016-08-16 17:14:44 +0000[diff] [blame]797 (v32i32 (V6_hi_128B VecDblRegs128B:$Vdd)),
798 (v32i32 (V6_lo_128B VecDblRegs128B:$Vdd))))>,
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]799 Requires<[UseHVXDbl]>;
800
Krzysztof Parzyszekeabc0d02016-08-16 17:14:44 +0000[diff] [blame]801def: Pat<(int_hexagon_V6_vd0), (V6_vd0)>;
802def: Pat<(int_hexagon_V6_vd0_128B), (V6_vd0_128B)>;
Krzysztof Parzyszek4eb6d4d2015-11-26 16:54:33 +0000[diff] [blame]803