| Tony Jiang | 3b49dc5 | 2017-12-11 20:42:37 +0000 | [diff] [blame] | 1 | target datalayout = "e-m:e-i64:64-n32:64" |
| 2 | target triple = "powerpc64le-unknown-linux-gnu" |
| 3 | ; This file mainly tests the case that the two input registers of the ISEL instruction are the same register. |
| 4 | ; The foldable ISEL in this test case is introduced at simple register coalescing stage. |
| 5 | |
| 6 | ; Before that stage we have: |
| 7 | ; %vreg18<def> = ISEL8 %vreg5, %vreg2, %vreg15<undef>; |
| 8 | |
| 9 | ; At simple register coalescing stage, the register coalescer figures out it could remove the copy |
| 10 | ; from %vreg2 to %vreg5, put the original value %X3 into %vreg5 directly |
| 11 | ; erased: 336r %vreg5<def> = COPY %vreg2 |
| 12 | ; updated: 288B %vreg5<def> = COPY %X3; |
| 13 | |
| 14 | ; After that we have: |
| 15 | ; updated: 416B %vreg18<def> = ISEL8 %vreg5, %vreg5, %vreg15<undef>; |
| 16 | |
| 17 | ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=true < %s | FileCheck %s --check-prefix=CHECK-GEN-ISEL-TRUE |
| 18 | ; RUN: llc -verify-machineinstrs -O2 -ppc-asm-full-reg-names -mcpu=pwr7 -ppc-gen-isel=false < %s | FileCheck %s --implicit-check-not isel |
| 19 | %"struct.pov::ot_block_struct" = type { %"struct.pov::ot_block_struct"*, [3 x double], [3 x double], float, float, float, float, float, float, float, float, float, [3 x float], float, float, [3 x double], i16 } |
| 20 | %"struct.pov::ot_node_struct" = type { %"struct.pov::ot_id_struct", %"struct.pov::ot_block_struct"*, [8 x %"struct.pov::ot_node_struct"*] } |
| 21 | %"struct.pov::ot_id_struct" = type { i32, i32, i32, i32 } |
| 22 | |
| 23 | define void @_ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE(%"struct.pov::ot_block_struct"* %new_block) { |
| 24 | ; CHECK-GEN-ISEL-TRUE-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE: |
| 25 | ; Note: the following line fold the original isel (isel r4, r3, r3) |
| 26 | ; CHECK-GEN-ISEL-TRUE: mr r4, r3 |
| 27 | ; CHECK-GEN-ISEL-TRUE: isel r29, r5, r6, 4*cr5+lt |
| 28 | ; CHECK-GEN-ISEL-TRUE: blr |
| 29 | ; |
| 30 | ; CHECK-LABEL: _ZN3pov6ot_insEPPNS_14ot_node_structEPNS_15ot_block_structEPNS_12ot_id_structE: |
| 31 | ; CHECK: mr r4, r3 |
| 32 | ; CHECK: bc 12, 4*cr5+lt, .LBB0_3 |
| 33 | ; CHECK: # %bb.2: |
| 34 | ; CHECK: ori r29, r6, 0 |
| 35 | ; CHECK: b .LBB0_4 |
| 36 | ; CHECK: .LBB0_3: |
| 37 | ; CHECK: addi r29, r5, 0 |
| 38 | ; CHECK: .LBB0_4: |
| 39 | ; CHECK: blr |
| 40 | entry: |
| 41 | br label %while.cond11 |
| 42 | |
| 43 | while.cond11: |
| 44 | %this_node.0250 = phi %"struct.pov::ot_node_struct"* [ undef, %entry ], [ %1, %cond.false21.i156 ], [ %1, %cond.true18.i153 ] |
| 45 | %temp_id.sroa.21.1 = phi i32 [ undef, %entry ], [ %shr2039.i152, %cond.true18.i153 ], [ %div24.i155, %cond.false21.i156 ] |
| 46 | %0 = load i32, i32* undef, align 4 |
| 47 | %cmp17 = icmp eq i32 0, %0 |
| 48 | br i1 %cmp17, label %lor.rhs, label %while.body21 |
| 49 | |
| 50 | lor.rhs: |
| 51 | %Values = getelementptr inbounds %"struct.pov::ot_node_struct", %"struct.pov::ot_node_struct"* %this_node.0250, i64 0, i32 1 |
| 52 | store %"struct.pov::ot_block_struct"* %new_block, %"struct.pov::ot_block_struct"** %Values, align 8 |
| 53 | ret void |
| 54 | |
| 55 | while.body21: |
| 56 | %call.i84 = tail call i8* @ZN3pov10pov_callocEmmPKciS1_pov() |
| 57 | store i8* %call.i84, i8** undef, align 8 |
| 58 | %1 = bitcast i8* %call.i84 to %"struct.pov::ot_node_struct"* |
| 59 | br i1 undef, label %cond.true18.i153, label %cond.false21.i156 |
| 60 | |
| 61 | cond.true18.i153: |
| 62 | %shr2039.i152 = lshr i32 %temp_id.sroa.21.1, 1 |
| 63 | br label %while.cond11 |
| 64 | |
| 65 | cond.false21.i156: |
| 66 | %add23.i154 = add nsw i32 %temp_id.sroa.21.1, 1 |
| 67 | %div24.i155 = sdiv i32 %add23.i154, 2 |
| 68 | br label %while.cond11 |
| 69 | } |
| 70 | |
| 71 | declare i8* @ZN3pov10pov_callocEmmPKciS1_pov() |