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gerrit-public.fairphone.software / toolchain / llvm-project / aa9ca691cde9d650ec92049ca851a311baf6d15c / . / llvm / test / CodeGen / PowerPC / vec-abi-align.ll
blob: ba687d3f0b8792d88ff95355a028dadb18932c40 [file] [log] [blame]
Ehsan Amiria538b0f2016-08-03 18:17:35 +0000[diff] [blame]1; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s
2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]3target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
4target triple = "powerpc64-unknown-linux-gnu"
5
6%struct.s2 = type { i64, <4 x float> }
7
8@ve = external global <4 x float>
9@n = external global i64
10
11; Function Attrs: nounwind
12define void @test1(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, <4 x float> inreg %vs.coerce) #0 {
13entry:
Hal Finkela5ebe422013-09-12 23:23:12 +0000[diff] [blame]14 store <4 x float> %vs.coerce, <4 x float>* @ve, align 16
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]15 ret void
16
17; CHECK-LABEL: @test1
18; CHECK: stvx 2,
19; CHECK: blr
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]20
21; CHECK-VSX-LABEL: @test1
22; CHECK-VSX: stxvw4x 34,
23; CHECK-VSX: blr
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]24}
25
26; Function Attrs: nounwind
27define void @test2(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, %struct.s2* byval nocapture readonly %vs) #0 {
28entry:
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]29 %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]30 %0 = load i64, i64* %m, align 8
Hal Finkela5ebe422013-09-12 23:23:12 +0000[diff] [blame]31 store i64 %0, i64* @n, align 8
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]32 %v = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 1
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]33 %1 = load <4 x float>, <4 x float>* %v, align 16
Hal Finkela5ebe422013-09-12 23:23:12 +0000[diff] [blame]34 store <4 x float> %1, <4 x float>* @ve, align 16
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]35 ret void
36
37; CHECK-LABEL: @test2
Hal Finkelcf599212015-02-25 21:36:59 +0000[diff] [blame]38; CHECK-DAG: ld {{[0-9]+}}, 112(1)
39; CHECK-DAG: li [[REG16:[0-9]+]], 16
40; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 112
41; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]42; CHECK: blr
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]43
44; CHECK-VSX-LABEL: @test2
Hal Finkelcf599212015-02-25 21:36:59 +0000[diff] [blame]45; CHECK-VSX-DAG: ld {{[0-9]+}}, 112(1)
46; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
47; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 112
48; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]49; CHECK-VSX: blr
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]50}
51
52; Function Attrs: nounwind
53define void @test3(i64 %d1, i64 %d2, i64 %d3, i64 %d4, i64 %d5, i64 %d6, i64 %d7, i64 %d8, i64 %d9, %struct.s2* byval nocapture readonly %vs) #0 {
54entry:
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]55 %m = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 0
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]56 %0 = load i64, i64* %m, align 8
Hal Finkela5ebe422013-09-12 23:23:12 +0000[diff] [blame]57 store i64 %0, i64* @n, align 8
David Blaikie79e6c742015-02-27 19:29:02 +0000[diff] [blame]58 %v = getelementptr inbounds %struct.s2, %struct.s2* %vs, i64 0, i32 1
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]59 %1 = load <4 x float>, <4 x float>* %v, align 16
Hal Finkela5ebe422013-09-12 23:23:12 +0000[diff] [blame]60 store <4 x float> %1, <4 x float>* @ve, align 16
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]61 ret void
62
63; CHECK-LABEL: @test3
Hal Finkelcf599212015-02-25 21:36:59 +0000[diff] [blame]64; CHECK-DAG: ld {{[0-9]+}}, 128(1)
65; CHECK-DAG: li [[REG16:[0-9]+]], 16
66; CHECK-DAG: addi [[REGB:[0-9]+]], 1, 128
67; CHECK-DAG: lvx 2, [[REGB]], [[REG16]]
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]68; CHECK: blr
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]69
70; CHECK-VSX-LABEL: @test3
Hal Finkelcf599212015-02-25 21:36:59 +0000[diff] [blame]71; CHECK-VSX-DAG: ld {{[0-9]+}}, 128(1)
72; CHECK-VSX-DAG: li [[REG16:[0-9]+]], 16
73; CHECK-VSX-DAG: addi [[REGB:[0-9]+]], 1, 128
74; CHECK-VSX-DAG: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]]
Bill Schmidt2d1128a2014-10-17 15:13:38 +0000[diff] [blame]75; CHECK-VSX: blr
Hal Finkel262a2242013-09-12 23:20:06 +0000[diff] [blame]76}
77
78attributes #0 = { nounwind }
79