Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / ab04ad6af760a203eda7624e97fcb7bbca9fceab / . / llvm / lib / Target / AMDGPU / AMDGPUInstructionSelector.h
blob: dfb1e3c081f0cc14ca48234e82524c22c222d4e7 [file] [log] [blame]
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]1//===- AMDGPUInstructionSelector --------------------------------*- C++ -*-==//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +0000[diff] [blame]3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]6//
7//===----------------------------------------------------------------------===//
8/// \file
9/// This file declares the targeting of the InstructionSelector class for
10/// AMDGPU.
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
15
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000[diff] [blame]16#include "AMDGPU.h"
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]17#include "AMDGPUArgumentUsageInfo.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]18#include "llvm/ADT/ArrayRef.h"
19#include "llvm/ADT/SmallVector.h"
Matt Arsenault2ab25f92019-07-01 16:06:02 +0000[diff] [blame]20#include "llvm/CodeGen/Register.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
Matt Arsenault3b7668a2019-07-01 13:34:26 +0000[diff] [blame]22#include "llvm/IR/InstrTypes.h"
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]23
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]24namespace {
25#define GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]26#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]27#include "AMDGPUGenGlobalISel.inc"
28#undef GET_GLOBALISEL_PREDICATE_BITSET
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]29#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]30}
31
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]32namespace llvm {
33
34class AMDGPUInstrInfo;
35class AMDGPURegisterBankInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]36class GCNSubtarget;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]37class MachineInstr;
38class MachineOperand;
39class MachineRegisterInfo;
40class SIInstrInfo;
Matt Arsenaultb1cc4f52018-06-25 16:17:48 +0000[diff] [blame]41class SIMachineFunctionInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]42class SIRegisterInfo;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]43
44class AMDGPUInstructionSelector : public InstructionSelector {
45public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]46 AMDGPUInstructionSelector(const GCNSubtarget &STI,
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]47 const AMDGPURegisterBankInfo &RBI,
48 const AMDGPUTargetMachine &TM);
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]49
Daniel Sandersf76f3152017-11-16 00:46:35 +0000[diff] [blame]50 bool select(MachineInstr &I, CodeGenCoverage &CoverageInfo) const override;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]51 static const char *getName();
Daniel Sandersf76f3152017-11-16 00:46:35 +0000[diff] [blame]52
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]53private:
54 struct GEPInfo {
55 const MachineInstr &GEP;
56 SmallVector<unsigned, 2> SgprParts;
57 SmallVector<unsigned, 2> VgprParts;
58 int64_t Imm;
59 GEPInfo(const MachineInstr &GEP) : GEP(GEP), Imm(0) { }
60 };
61
Tom Stellard79b5c382019-02-20 21:02:37 +0000[diff] [blame]62 bool isInstrUniform(const MachineInstr &MI) const;
Matt Arsenault2ab25f92019-07-01 16:06:02 +0000[diff] [blame]63 bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
64
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]65 /// tblgen-erated 'select' implementation.
66 bool selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
67
Matt Arsenault0a52e9d2019-07-01 16:34:48 +0000[diff] [blame]68 MachineOperand getSubOperand64(MachineOperand &MO,
69 const TargetRegisterClass &SubRC,
70 unsigned SubIdx) const;
Tom Stellard1e0edad2018-05-10 21:20:10 +0000[diff] [blame]71 bool selectCOPY(MachineInstr &I) const;
Matt Arsenaulte1006252019-07-01 16:32:47 +0000[diff] [blame]72 bool selectPHI(MachineInstr &I) const;
Matt Arsenaultdbb6c032019-06-24 18:02:18 +0000[diff] [blame]73 bool selectG_TRUNC(MachineInstr &I) const;
Matt Arsenaultd7ffa2a2019-06-25 13:18:11 +0000[diff] [blame]74 bool selectG_SZA_EXT(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]75 bool selectG_CONSTANT(MachineInstr &I) const;
Matt Arsenaultc8291c92019-07-15 19:50:07 +0000[diff] [blame]76 bool selectG_AND_OR_XOR(MachineInstr &I) const;
Matt Arsenaulte6d10f92019-07-09 14:05:11 +0000[diff] [blame]77 bool selectG_ADD_SUB(MachineInstr &I) const;
Tom Stellard41f32192019-02-28 23:37:48 +0000[diff] [blame]78 bool selectG_EXTRACT(MachineInstr &I) const;
Matt Arsenault9b7ffc42019-07-09 14:02:20 +0000[diff] [blame]79 bool selectG_MERGE_VALUES(MachineInstr &I) const;
Matt Arsenault872f38b2019-07-09 14:02:26 +0000[diff] [blame]80 bool selectG_UNMERGE_VALUES(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]81 bool selectG_GEP(MachineInstr &I) const;
Tom Stellard3f1c6fe2018-06-21 23:38:20 +0000[diff] [blame]82 bool selectG_IMPLICIT_DEF(MachineInstr &I) const;
Tom Stellard33634d1b2019-03-01 00:50:26 +0000[diff] [blame]83 bool selectG_INSERT(MachineInstr &I) const;
Tom Stellarda9284732018-06-14 19:26:37 +0000[diff] [blame]84 bool selectG_INTRINSIC(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
Tom Stellard390a5f42018-07-13 21:05:14 +0000[diff] [blame]85 bool selectG_INTRINSIC_W_SIDE_EFFECTS(MachineInstr &I,
86 CodeGenCoverage &CoverageInfo) const;
Matt Arsenault3b7668a2019-07-01 13:34:26 +0000[diff] [blame]87 int getS_CMPOpcode(CmpInst::Predicate P, unsigned Size) const;
Tom Stellard8b1c53b2019-06-17 16:27:43 +0000[diff] [blame]88 bool selectG_ICMP(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]89 bool hasVgprParts(ArrayRef<GEPInfo> AddrInfo) const;
90 void getAddrModeInfo(const MachineInstr &Load, const MachineRegisterInfo &MRI,
91 SmallVectorImpl<GEPInfo> &AddrInfo) const;
92 bool selectSMRD(MachineInstr &I, ArrayRef<GEPInfo> AddrInfo) const;
Matt Arsenault3baf4d32019-08-01 03:09:15 +0000[diff] [blame]93
94 void initM0(MachineInstr &I) const;
Matt Arsenaultda5b9bf2019-08-01 03:29:01 +0000[diff] [blame]95 bool selectG_LOAD_ATOMICRMW(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
Matt Arsenault3baf4d32019-08-01 03:09:15 +0000[diff] [blame]96 bool selectG_STORE(MachineInstr &I, CodeGenCoverage &CoverageInfo) const;
Tom Stellard8b1c53b2019-06-17 16:27:43 +0000[diff] [blame]97 bool selectG_SELECT(MachineInstr &I) const;
Matt Arsenault64642802019-07-01 15:39:27 +0000[diff] [blame]98 bool selectG_BRCOND(MachineInstr &I) const;
Matt Arsenaultcda82f02019-07-01 15:48:18 +0000[diff] [blame]99 bool selectG_FRAME_INDEX(MachineInstr &I) const;
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]100
Matt Arsenault4f64ade2019-07-01 15:18:56 +0000[diff] [blame]101 std::pair<Register, unsigned>
102 selectVOP3ModsImpl(Register Src, const MachineRegisterInfo &MRI) const;
103
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]104 InstructionSelector::ComplexRendererFns
Tom Stellard26fac0f2018-06-22 02:54:57 +0000[diff] [blame]105 selectVCSRC(MachineOperand &Root) const;
106
107 InstructionSelector::ComplexRendererFns
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]108 selectVSRC0(MachineOperand &Root) const;
109
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]110 InstructionSelector::ComplexRendererFns
111 selectVOP3Mods0(MachineOperand &Root) const;
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]112 InstructionSelector::ComplexRendererFns
Tom Stellard9a653572018-06-22 02:34:29 +0000[diff] [blame]113 selectVOP3OMods(MachineOperand &Root) const;
114 InstructionSelector::ComplexRendererFns
Tom Stellard46bbbc32018-06-13 22:30:47 +0000[diff] [blame]115 selectVOP3Mods(MachineOperand &Root) const;
Tom Stellarddcc95e92018-05-11 05:44:16 +0000[diff] [blame]116
Tom Stellard79b5c382019-02-20 21:02:37 +0000[diff] [blame]117 InstructionSelector::ComplexRendererFns
118 selectSmrdImm(MachineOperand &Root) const;
119 InstructionSelector::ComplexRendererFns
120 selectSmrdImm32(MachineOperand &Root) const;
121 InstructionSelector::ComplexRendererFns
122 selectSmrdSgpr(MachineOperand &Root) const;
123
Matt Arsenault35c96592019-07-16 18:05:29 +0000[diff] [blame]124 template <bool Signed>
125 InstructionSelector::ComplexRendererFns
126 selectFlatOffsetImpl(MachineOperand &Root) const;
127 InstructionSelector::ComplexRendererFns
128 selectFlatOffset(MachineOperand &Root) const;
129
130 InstructionSelector::ComplexRendererFns
131 selectFlatOffsetSigned(MachineOperand &Root) const;
132
Matt Arsenault7161fb02019-07-16 19:22:21 +0000[diff] [blame]133 InstructionSelector::ComplexRendererFns
134 selectMUBUFScratchOffen(MachineOperand &Root) const;
135 InstructionSelector::ComplexRendererFns
136 selectMUBUFScratchOffset(MachineOperand &Root) const;
137
Matt Arsenault35940112019-08-01 00:53:38 +0000[diff] [blame]138 bool isDSOffsetLegal(const MachineRegisterInfo &MRI,
139 const MachineOperand &Base,
140 int64_t Offset, unsigned OffsetBits) const;
141
142 InstructionSelector::ComplexRendererFns
143 selectDS1Addr1Offset(MachineOperand &Root) const;
144
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]145 const SIInstrInfo &TII;
146 const SIRegisterInfo &TRI;
147 const AMDGPURegisterBankInfo &RBI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]148 const AMDGPUTargetMachine &TM;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]149 const GCNSubtarget &STI;
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]150 bool EnableLateStructurizeCFG;
151#define GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]152#define AMDGPUSubtarget GCNSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]153#include "AMDGPUGenGlobalISel.inc"
154#undef GET_GLOBALISEL_PREDICATES_DECL
Tom Stellard5bfbae52018-07-11 20:59:01 +0000[diff] [blame]155#undef AMDGPUSubtarget
Tom Stellard1dc90202018-05-10 20:53:06 +0000[diff] [blame]156
157#define GET_GLOBALISEL_TEMPORARIES_DECL
158#include "AMDGPUGenGlobalISel.inc"
159#undef GET_GLOBALISEL_TEMPORARIES_DECL
Tom Stellardca166212017-01-30 21:56:46 +0000[diff] [blame]160};
161
162} // End llvm namespace.
163#endif