Michael Kuperstein | 9201fb9 | 2014-02-26 12:06:36 +0000 | [diff] [blame] | 1 | ; RUN: llvm-dis < %s.bc| FileCheck %s
|
| 2 |
|
| 3 | ; BinaryIntOperation.3.2.ll.bc was generated by passing this file to llvm-as-3.2.
|
| 4 | ; The test checks that LLVM does not misread binary integer instructions from
|
| 5 | ; older bitcode files.
|
| 6 |
|
| 7 | define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
|
| 8 | entry:
|
| 9 | ; CHECK: %res1 = add i1 %x1, %x1
|
| 10 | %res1 = add i1 %x1, %x1
|
| 11 |
|
| 12 | ; CHECK-NEXT: %res2 = add i8 %x2, %x2
|
| 13 | %res2 = add i8 %x2, %x2
|
| 14 |
|
| 15 | ; CHECK-NEXT: %res3 = add i16 %x3, %x3
|
| 16 | %res3 = add i16 %x3, %x3
|
| 17 |
|
| 18 | ; CHECK-NEXT: %res4 = add i32 %x4, %x4
|
| 19 | %res4 = add i32 %x4, %x4
|
| 20 |
|
| 21 | ; CHECK-NEXT: %res5 = add i64 %x5, %x5
|
| 22 | %res5 = add i64 %x5, %x5
|
| 23 |
|
| 24 | ; CHECK: %res6 = add nuw i1 %x1, %x1
|
| 25 | %res6 = add nuw i1 %x1, %x1
|
| 26 |
|
| 27 | ; CHECK: %res7 = add nsw i1 %x1, %x1
|
| 28 | %res7 = add nsw i1 %x1, %x1
|
| 29 |
|
| 30 | ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
|
| 31 | %res8 = add nuw nsw i1 %x1, %x1
|
| 32 |
|
| 33 | ret void
|
| 34 | }
|
| 35 |
|
| 36 | define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
|
| 37 | entry:
|
| 38 | ; CHECK: %res1 = add nuw nsw <2 x i8> %x1, %x1
|
| 39 | %res1 = add nuw nsw <2 x i8> %x1, %x1
|
| 40 |
|
| 41 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i8> %x2, %x2
|
| 42 | %res2 = add nuw nsw <3 x i8> %x2, %x2
|
| 43 |
|
| 44 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i8> %x3, %x3
|
| 45 | %res3 = add nuw nsw <4 x i8> %x3, %x3
|
| 46 |
|
| 47 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i8> %x4, %x4
|
| 48 | %res4 = add nuw nsw <8 x i8> %x4, %x4
|
| 49 |
|
| 50 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i8> %x5, %x5
|
| 51 | %res5 = add nuw nsw <16 x i8> %x5, %x5
|
| 52 |
|
| 53 | ret void
|
| 54 | }
|
| 55 |
|
| 56 | define void @addvec16NuwNsw(<2 x i16> %x1, <3 x i16> %x2 ,<4 x i16> %x3, <8 x i16> %x4, <16 x i16> %x5){
|
| 57 | entry:
|
| 58 | ; CHECK: %res1 = add nuw nsw <2 x i16> %x1, %x1
|
| 59 | %res1 = add nuw nsw <2 x i16> %x1, %x1
|
| 60 |
|
| 61 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i16> %x2, %x2
|
| 62 | %res2 = add nuw nsw <3 x i16> %x2, %x2
|
| 63 |
|
| 64 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i16> %x3, %x3
|
| 65 | %res3 = add nuw nsw <4 x i16> %x3, %x3
|
| 66 |
|
| 67 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i16> %x4, %x4
|
| 68 | %res4 = add nuw nsw <8 x i16> %x4, %x4
|
| 69 |
|
| 70 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i16> %x5, %x5
|
| 71 | %res5 = add nuw nsw <16 x i16> %x5, %x5
|
| 72 |
|
| 73 | ret void
|
| 74 | }
|
| 75 |
|
| 76 | define void @addvec32NuwNsw(<2 x i32> %x1, <3 x i32> %x2 ,<4 x i32> %x3, <8 x i32> %x4, <16 x i32> %x5){
|
| 77 | entry:
|
| 78 | ; CHECK: %res1 = add nuw nsw <2 x i32> %x1, %x1
|
| 79 | %res1 = add nuw nsw <2 x i32> %x1, %x1
|
| 80 |
|
| 81 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i32> %x2, %x2
|
| 82 | %res2 = add nuw nsw <3 x i32> %x2, %x2
|
| 83 |
|
| 84 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i32> %x3, %x3
|
| 85 | %res3 = add nuw nsw <4 x i32> %x3, %x3
|
| 86 |
|
| 87 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i32> %x4, %x4
|
| 88 | %res4 = add nuw nsw <8 x i32> %x4, %x4
|
| 89 |
|
| 90 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i32> %x5, %x5
|
| 91 | %res5 = add nuw nsw <16 x i32> %x5, %x5
|
| 92 |
|
| 93 | ret void
|
| 94 | }
|
| 95 |
|
| 96 | define void @addvec64NuwNsw(<2 x i64> %x1, <3 x i64> %x2 ,<4 x i64> %x3, <8 x i64> %x4, <16 x i64> %x5){
|
| 97 | entry:
|
| 98 | ; CHECK: %res1 = add nuw nsw <2 x i64> %x1, %x1
|
| 99 | %res1 = add nuw nsw <2 x i64> %x1, %x1
|
| 100 |
|
| 101 | ; CHECK-NEXT: %res2 = add nuw nsw <3 x i64> %x2, %x2
|
| 102 | %res2 = add nuw nsw <3 x i64> %x2, %x2
|
| 103 |
|
| 104 | ; CHECK-NEXT: %res3 = add nuw nsw <4 x i64> %x3, %x3
|
| 105 | %res3 = add nuw nsw <4 x i64> %x3, %x3
|
| 106 |
|
| 107 | ; CHECK-NEXT: %res4 = add nuw nsw <8 x i64> %x4, %x4
|
| 108 | %res4 = add nuw nsw <8 x i64> %x4, %x4
|
| 109 |
|
| 110 | ; CHECK-NEXT: %res5 = add nuw nsw <16 x i64> %x5, %x5
|
| 111 | %res5 = add nuw nsw <16 x i64> %x5, %x5
|
| 112 |
|
| 113 | ret void
|
| 114 | }
|
| 115 |
|
| 116 | define void @sub(i8 %x1){
|
| 117 | entry:
|
| 118 | ; CHECK: %res1 = sub i8 %x1, %x1
|
| 119 | %res1 = sub i8 %x1, %x1
|
| 120 |
|
| 121 | ; CHECK: %res2 = sub nuw i8 %x1, %x1
|
| 122 | %res2 = sub nuw i8 %x1, %x1
|
| 123 |
|
| 124 | ; CHECK: %res3 = sub nsw i8 %x1, %x1
|
| 125 | %res3 = sub nsw i8 %x1, %x1
|
| 126 |
|
| 127 | ; CHECK: %res4 = sub nuw nsw i8 %x1, %x1
|
| 128 | %res4 = sub nuw nsw i8 %x1, %x1
|
| 129 |
|
| 130 | ret void
|
| 131 | }
|
| 132 |
|
| 133 | define void @mul(i8 %x1){
|
| 134 | entry:
|
| 135 | ; CHECK: %res1 = mul i8 %x1, %x1
|
| 136 | %res1 = mul i8 %x1, %x1
|
| 137 |
|
| 138 | ret void
|
| 139 | }
|
| 140 |
|
| 141 | define void @udiv(i8 %x1){
|
| 142 | entry:
|
| 143 | ; CHECK: %res1 = udiv i8 %x1, %x1
|
| 144 | %res1 = udiv i8 %x1, %x1
|
| 145 |
|
| 146 | ; CHECK-NEXT: %res2 = udiv exact i8 %x1, %x1
|
| 147 | %res2 = udiv exact i8 %x1, %x1
|
| 148 |
|
| 149 | ret void
|
| 150 | }
|
| 151 |
|
| 152 | define void @sdiv(i8 %x1){
|
| 153 | entry:
|
| 154 | ; CHECK: %res1 = sdiv i8 %x1, %x1
|
| 155 | %res1 = sdiv i8 %x1, %x1
|
| 156 |
|
| 157 | ; CHECK-NEXT: %res2 = sdiv exact i8 %x1, %x1
|
| 158 | %res2 = sdiv exact i8 %x1, %x1
|
| 159 |
|
| 160 | ret void
|
| 161 | }
|
| 162 |
|
| 163 | define void @urem(i32 %x1){
|
| 164 | entry:
|
| 165 | ; CHECK: %res1 = urem i32 %x1, %x1
|
| 166 | %res1 = urem i32 %x1, %x1
|
| 167 |
|
| 168 | ret void
|
| 169 | }
|
| 170 |
|
| 171 | define void @srem(i32 %x1){
|
| 172 | entry:
|
| 173 | ; CHECK: %res1 = srem i32 %x1, %x1
|
| 174 | %res1 = srem i32 %x1, %x1
|
| 175 |
|
| 176 | ret void
|
| 177 | }
|