Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===// |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 10 | /// \file This file implements the LegalizerHelper class to legalize individual |
| 11 | /// instructions and the LegalizePass wrapper pass for the primary |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 12 | /// legalization. |
| 13 | // |
| 14 | //===----------------------------------------------------------------------===// |
| 15 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 16 | #include "llvm/CodeGen/GlobalISel/Legalizer.h" |
| 17 | #include "llvm/CodeGen/GlobalISel/LegalizerHelper.h" |
| 18 | #include "llvm/CodeGen/GlobalISel/Legalizer.h" |
Ahmed Bougacha | ae9dade | 2017-02-23 21:05:42 +0000 | [diff] [blame^] | 19 | #include "llvm/CodeGen/GlobalISel/Utils.h" |
| 20 | #include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h" |
Quentin Colombet | 5e60bcd | 2016-08-27 02:38:21 +0000 | [diff] [blame] | 21 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
| 22 | #include "llvm/CodeGen/TargetPassConfig.h" |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 23 | #include "llvm/Support/Debug.h" |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 24 | #include "llvm/Target/TargetInstrInfo.h" |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 25 | #include "llvm/Target/TargetSubtargetInfo.h" |
| 26 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 27 | #define DEBUG_TYPE "legalizer" |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 28 | |
| 29 | using namespace llvm; |
| 30 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 31 | char Legalizer::ID = 0; |
| 32 | INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE, |
Quentin Colombet | 5e60bcd | 2016-08-27 02:38:21 +0000 | [diff] [blame] | 33 | "Legalize the Machine IR a function's Machine IR", false, |
| 34 | false) |
| 35 | INITIALIZE_PASS_DEPENDENCY(TargetPassConfig) |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 36 | INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE, |
Quentin Colombet | 5e60bcd | 2016-08-27 02:38:21 +0000 | [diff] [blame] | 37 | "Legalize the Machine IR a function's Machine IR", false, |
| 38 | false) |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 39 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 40 | Legalizer::Legalizer() : MachineFunctionPass(ID) { |
| 41 | initializeLegalizerPass(*PassRegistry::getPassRegistry()); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 42 | } |
| 43 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 44 | void Legalizer::getAnalysisUsage(AnalysisUsage &AU) const { |
Quentin Colombet | 5e60bcd | 2016-08-27 02:38:21 +0000 | [diff] [blame] | 45 | AU.addRequired<TargetPassConfig>(); |
| 46 | MachineFunctionPass::getAnalysisUsage(AU); |
| 47 | } |
| 48 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 49 | void Legalizer::init(MachineFunction &MF) { |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 50 | } |
| 51 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 52 | bool Legalizer::combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI, |
| 53 | const TargetInstrInfo &TII) { |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 54 | bool Changed = false; |
| 55 | if (MI.getOpcode() != TargetOpcode::G_EXTRACT) |
| 56 | return Changed; |
| 57 | |
| 58 | unsigned NumDefs = (MI.getNumOperands() - 1) / 2; |
| 59 | unsigned SrcReg = MI.getOperand(NumDefs).getReg(); |
| 60 | MachineInstr &SeqI = *MRI.def_instr_begin(SrcReg); |
| 61 | if (SeqI.getOpcode() != TargetOpcode::G_SEQUENCE) |
| 62 | return Changed; |
| 63 | |
| 64 | unsigned NumSeqSrcs = (SeqI.getNumOperands() - 1) / 2; |
| 65 | bool AllDefsReplaced = true; |
| 66 | |
| 67 | // Try to match each register extracted with a corresponding insertion formed |
| 68 | // by the G_SEQUENCE. |
| 69 | for (unsigned Idx = 0, SeqIdx = 0; Idx < NumDefs; ++Idx) { |
| 70 | MachineOperand &ExtractMO = MI.getOperand(Idx); |
| 71 | assert(ExtractMO.isReg() && ExtractMO.isDef() && |
| 72 | "unexpected extract operand"); |
| 73 | |
| 74 | unsigned ExtractReg = ExtractMO.getReg(); |
| 75 | unsigned ExtractPos = MI.getOperand(NumDefs + Idx + 1).getImm(); |
| 76 | |
| 77 | while (SeqIdx < NumSeqSrcs && |
| 78 | SeqI.getOperand(2 * SeqIdx + 2).getImm() < ExtractPos) |
| 79 | ++SeqIdx; |
| 80 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 81 | if (SeqIdx == NumSeqSrcs) { |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 82 | AllDefsReplaced = false; |
| 83 | continue; |
| 84 | } |
| 85 | |
| 86 | unsigned OrigReg = SeqI.getOperand(2 * SeqIdx + 1).getReg(); |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 87 | if (SeqI.getOperand(2 * SeqIdx + 2).getImm() != ExtractPos || |
| 88 | MRI.getType(OrigReg) != MRI.getType(ExtractReg)) { |
| 89 | AllDefsReplaced = false; |
| 90 | continue; |
| 91 | } |
| 92 | |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 93 | assert(!TargetRegisterInfo::isPhysicalRegister(OrigReg) && |
| 94 | "unexpected physical register in G_SEQUENCE"); |
| 95 | |
| 96 | // Finally we can replace the uses. |
| 97 | for (auto &Use : MRI.use_operands(ExtractReg)) { |
| 98 | Changed = true; |
| 99 | Use.setReg(OrigReg); |
| 100 | } |
| 101 | } |
| 102 | |
| 103 | if (AllDefsReplaced) { |
| 104 | // If SeqI was the next instruction in the BB and we removed it, we'd break |
| 105 | // the outer iteration. |
| 106 | assert(std::next(MachineBasicBlock::iterator(MI)) != SeqI && |
| 107 | "G_SEQUENCE does not dominate G_EXTRACT"); |
| 108 | |
| 109 | MI.eraseFromParent(); |
| 110 | |
| 111 | if (MRI.use_empty(SrcReg)) |
| 112 | SeqI.eraseFromParent(); |
| 113 | Changed = true; |
| 114 | } |
| 115 | |
| 116 | return Changed; |
| 117 | } |
| 118 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 119 | bool Legalizer::runOnMachineFunction(MachineFunction &MF) { |
Quentin Colombet | 6049524 | 2016-08-27 00:18:24 +0000 | [diff] [blame] | 120 | // If the ISel pipeline failed, do not bother running that pass. |
| 121 | if (MF.getProperties().hasProperty( |
| 122 | MachineFunctionProperties::Property::FailedISel)) |
| 123 | return false; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 124 | DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n'); |
| 125 | init(MF); |
Quentin Colombet | 5e60bcd | 2016-08-27 02:38:21 +0000 | [diff] [blame] | 126 | const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>(); |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 127 | const LegalizerInfo &LegalizerInfo = *MF.getSubtarget().getLegalizerInfo(); |
Ahmed Bougacha | ae9dade | 2017-02-23 21:05:42 +0000 | [diff] [blame^] | 128 | MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr); |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 129 | LegalizerHelper Helper(MF); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 130 | |
| 131 | // FIXME: an instruction may need more than one pass before it is legal. For |
| 132 | // example on most architectures <3 x i3> is doubly-illegal. It would |
| 133 | // typically proceed along a path like: <3 x i3> -> <3 x i8> -> <8 x i8>. We |
| 134 | // probably want a worklist of instructions rather than naive iterate until |
| 135 | // convergence for performance reasons. |
| 136 | bool Changed = false; |
| 137 | MachineBasicBlock::iterator NextMI; |
| 138 | for (auto &MBB : MF) |
| 139 | for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) { |
| 140 | // Get the next Instruction before we try to legalize, because there's a |
| 141 | // good chance MI will be deleted. |
| 142 | NextMI = std::next(MI); |
Ahmed Bougacha | faf8e9f | 2016-08-02 11:41:09 +0000 | [diff] [blame] | 143 | |
| 144 | // Only legalize pre-isel generic instructions: others don't have types |
| 145 | // and are assumed to be legal. |
| 146 | if (!isPreISelGenericOpcode(MI->getOpcode())) |
| 147 | continue; |
| 148 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 149 | auto Res = Helper.legalizeInstr(*MI, LegalizerInfo); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 150 | |
| 151 | // Error out if we couldn't legalize this instruction. We may want to fall |
| 152 | // back to DAG ISel instead in the future. |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 153 | if (Res == LegalizerHelper::UnableToLegalize) { |
Ahmed Bougacha | ae9dade | 2017-02-23 21:05:42 +0000 | [diff] [blame^] | 154 | reportGISelFailure(MF, TPC, MORE, "gisel-legalize", |
| 155 | "unable to legalize instruction", *MI); |
| 156 | return false; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 157 | } |
| 158 | |
Tim Northover | 69fa84a | 2016-10-14 22:18:18 +0000 | [diff] [blame] | 159 | Changed |= Res == LegalizerHelper::Legalized; |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 160 | } |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 161 | |
| 162 | |
| 163 | MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 164 | const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo(); |
| 165 | for (auto &MBB : MF) { |
| 166 | for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) { |
| 167 | // Get the next Instruction before we try to legalize, because there's a |
| 168 | // good chance MI will be deleted. |
| 169 | NextMI = std::next(MI); |
| 170 | |
| 171 | Changed |= combineExtracts(*MI, MRI, TII); |
| 172 | } |
| 173 | } |
| 174 | |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 175 | return Changed; |
| 176 | } |