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Tim Northover69fa84a2016-10-14 22:18:18 +00001//===-- llvm/CodeGen/GlobalISel/Legalizer.cpp -----------------------------===//
Tim Northover33b07d62016-07-22 20:03:43 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Tim Northover69fa84a2016-10-14 22:18:18 +000010/// \file This file implements the LegalizerHelper class to legalize individual
11/// instructions and the LegalizePass wrapper pass for the primary
Tim Northover33b07d62016-07-22 20:03:43 +000012/// legalization.
13//
14//===----------------------------------------------------------------------===//
15
Tim Northover69fa84a2016-10-14 22:18:18 +000016#include "llvm/CodeGen/GlobalISel/Legalizer.h"
17#include "llvm/CodeGen/GlobalISel/LegalizerHelper.h"
18#include "llvm/CodeGen/GlobalISel/Legalizer.h"
Ahmed Bougachaae9dade2017-02-23 21:05:42 +000019#include "llvm/CodeGen/GlobalISel/Utils.h"
20#include "llvm/CodeGen/MachineOptimizationRemarkEmitter.h"
Quentin Colombet5e60bcd2016-08-27 02:38:21 +000021#include "llvm/CodeGen/MachineRegisterInfo.h"
22#include "llvm/CodeGen/TargetPassConfig.h"
Tim Northover33b07d62016-07-22 20:03:43 +000023#include "llvm/Support/Debug.h"
Tim Northover991b12b2016-08-30 20:51:25 +000024#include "llvm/Target/TargetInstrInfo.h"
Tim Northover33b07d62016-07-22 20:03:43 +000025#include "llvm/Target/TargetSubtargetInfo.h"
26
Tim Northover69fa84a2016-10-14 22:18:18 +000027#define DEBUG_TYPE "legalizer"
Tim Northover33b07d62016-07-22 20:03:43 +000028
29using namespace llvm;
30
Tim Northover69fa84a2016-10-14 22:18:18 +000031char Legalizer::ID = 0;
32INITIALIZE_PASS_BEGIN(Legalizer, DEBUG_TYPE,
Quentin Colombet5e60bcd2016-08-27 02:38:21 +000033 "Legalize the Machine IR a function's Machine IR", false,
34 false)
35INITIALIZE_PASS_DEPENDENCY(TargetPassConfig)
Tim Northover69fa84a2016-10-14 22:18:18 +000036INITIALIZE_PASS_END(Legalizer, DEBUG_TYPE,
Quentin Colombet5e60bcd2016-08-27 02:38:21 +000037 "Legalize the Machine IR a function's Machine IR", false,
38 false)
Tim Northover33b07d62016-07-22 20:03:43 +000039
Tim Northover69fa84a2016-10-14 22:18:18 +000040Legalizer::Legalizer() : MachineFunctionPass(ID) {
41 initializeLegalizerPass(*PassRegistry::getPassRegistry());
Tim Northover33b07d62016-07-22 20:03:43 +000042}
43
Tim Northover69fa84a2016-10-14 22:18:18 +000044void Legalizer::getAnalysisUsage(AnalysisUsage &AU) const {
Quentin Colombet5e60bcd2016-08-27 02:38:21 +000045 AU.addRequired<TargetPassConfig>();
46 MachineFunctionPass::getAnalysisUsage(AU);
47}
48
Tim Northover69fa84a2016-10-14 22:18:18 +000049void Legalizer::init(MachineFunction &MF) {
Tim Northover33b07d62016-07-22 20:03:43 +000050}
51
Tim Northover69fa84a2016-10-14 22:18:18 +000052bool Legalizer::combineExtracts(MachineInstr &MI, MachineRegisterInfo &MRI,
53 const TargetInstrInfo &TII) {
Tim Northover991b12b2016-08-30 20:51:25 +000054 bool Changed = false;
55 if (MI.getOpcode() != TargetOpcode::G_EXTRACT)
56 return Changed;
57
58 unsigned NumDefs = (MI.getNumOperands() - 1) / 2;
59 unsigned SrcReg = MI.getOperand(NumDefs).getReg();
60 MachineInstr &SeqI = *MRI.def_instr_begin(SrcReg);
61 if (SeqI.getOpcode() != TargetOpcode::G_SEQUENCE)
62 return Changed;
63
64 unsigned NumSeqSrcs = (SeqI.getNumOperands() - 1) / 2;
65 bool AllDefsReplaced = true;
66
67 // Try to match each register extracted with a corresponding insertion formed
68 // by the G_SEQUENCE.
69 for (unsigned Idx = 0, SeqIdx = 0; Idx < NumDefs; ++Idx) {
70 MachineOperand &ExtractMO = MI.getOperand(Idx);
71 assert(ExtractMO.isReg() && ExtractMO.isDef() &&
72 "unexpected extract operand");
73
74 unsigned ExtractReg = ExtractMO.getReg();
75 unsigned ExtractPos = MI.getOperand(NumDefs + Idx + 1).getImm();
76
77 while (SeqIdx < NumSeqSrcs &&
78 SeqI.getOperand(2 * SeqIdx + 2).getImm() < ExtractPos)
79 ++SeqIdx;
80
Tim Northover0f140c72016-09-09 11:46:34 +000081 if (SeqIdx == NumSeqSrcs) {
Tim Northover991b12b2016-08-30 20:51:25 +000082 AllDefsReplaced = false;
83 continue;
84 }
85
86 unsigned OrigReg = SeqI.getOperand(2 * SeqIdx + 1).getReg();
Tim Northover0f140c72016-09-09 11:46:34 +000087 if (SeqI.getOperand(2 * SeqIdx + 2).getImm() != ExtractPos ||
88 MRI.getType(OrigReg) != MRI.getType(ExtractReg)) {
89 AllDefsReplaced = false;
90 continue;
91 }
92
Tim Northover991b12b2016-08-30 20:51:25 +000093 assert(!TargetRegisterInfo::isPhysicalRegister(OrigReg) &&
94 "unexpected physical register in G_SEQUENCE");
95
96 // Finally we can replace the uses.
97 for (auto &Use : MRI.use_operands(ExtractReg)) {
98 Changed = true;
99 Use.setReg(OrigReg);
100 }
101 }
102
103 if (AllDefsReplaced) {
104 // If SeqI was the next instruction in the BB and we removed it, we'd break
105 // the outer iteration.
106 assert(std::next(MachineBasicBlock::iterator(MI)) != SeqI &&
107 "G_SEQUENCE does not dominate G_EXTRACT");
108
109 MI.eraseFromParent();
110
111 if (MRI.use_empty(SrcReg))
112 SeqI.eraseFromParent();
113 Changed = true;
114 }
115
116 return Changed;
117}
118
Tim Northover69fa84a2016-10-14 22:18:18 +0000119bool Legalizer::runOnMachineFunction(MachineFunction &MF) {
Quentin Colombet60495242016-08-27 00:18:24 +0000120 // If the ISel pipeline failed, do not bother running that pass.
121 if (MF.getProperties().hasProperty(
122 MachineFunctionProperties::Property::FailedISel))
123 return false;
Tim Northover33b07d62016-07-22 20:03:43 +0000124 DEBUG(dbgs() << "Legalize Machine IR for: " << MF.getName() << '\n');
125 init(MF);
Quentin Colombet5e60bcd2016-08-27 02:38:21 +0000126 const TargetPassConfig &TPC = getAnalysis<TargetPassConfig>();
Tim Northover69fa84a2016-10-14 22:18:18 +0000127 const LegalizerInfo &LegalizerInfo = *MF.getSubtarget().getLegalizerInfo();
Ahmed Bougachaae9dade2017-02-23 21:05:42 +0000128 MachineOptimizationRemarkEmitter MORE(MF, /*MBFI=*/nullptr);
Tim Northover69fa84a2016-10-14 22:18:18 +0000129 LegalizerHelper Helper(MF);
Tim Northover33b07d62016-07-22 20:03:43 +0000130
131 // FIXME: an instruction may need more than one pass before it is legal. For
132 // example on most architectures <3 x i3> is doubly-illegal. It would
133 // typically proceed along a path like: <3 x i3> -> <3 x i8> -> <8 x i8>. We
134 // probably want a worklist of instructions rather than naive iterate until
135 // convergence for performance reasons.
136 bool Changed = false;
137 MachineBasicBlock::iterator NextMI;
138 for (auto &MBB : MF)
139 for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
140 // Get the next Instruction before we try to legalize, because there's a
141 // good chance MI will be deleted.
142 NextMI = std::next(MI);
Ahmed Bougachafaf8e9f2016-08-02 11:41:09 +0000143
144 // Only legalize pre-isel generic instructions: others don't have types
145 // and are assumed to be legal.
146 if (!isPreISelGenericOpcode(MI->getOpcode()))
147 continue;
148
Tim Northover69fa84a2016-10-14 22:18:18 +0000149 auto Res = Helper.legalizeInstr(*MI, LegalizerInfo);
Tim Northover33b07d62016-07-22 20:03:43 +0000150
151 // Error out if we couldn't legalize this instruction. We may want to fall
152 // back to DAG ISel instead in the future.
Tim Northover69fa84a2016-10-14 22:18:18 +0000153 if (Res == LegalizerHelper::UnableToLegalize) {
Ahmed Bougachaae9dade2017-02-23 21:05:42 +0000154 reportGISelFailure(MF, TPC, MORE, "gisel-legalize",
155 "unable to legalize instruction", *MI);
156 return false;
Tim Northover33b07d62016-07-22 20:03:43 +0000157 }
158
Tim Northover69fa84a2016-10-14 22:18:18 +0000159 Changed |= Res == LegalizerHelper::Legalized;
Tim Northover33b07d62016-07-22 20:03:43 +0000160 }
Tim Northover991b12b2016-08-30 20:51:25 +0000161
162
163 MachineRegisterInfo &MRI = MF.getRegInfo();
164 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
165 for (auto &MBB : MF) {
166 for (auto MI = MBB.begin(); MI != MBB.end(); MI = NextMI) {
167 // Get the next Instruction before we try to legalize, because there's a
168 // good chance MI will be deleted.
169 NextMI = std::next(MI);
170
171 Changed |= combineExtracts(*MI, MRI, TII);
172 }
173 }
174
Tim Northover33b07d62016-07-22 20:03:43 +0000175 return Changed;
176}