Jia Liu | b22310f | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 1 | //===-- X86InstrArithmetic.td - Integer Arithmetic Instrs --*- tablegen -*-===// |
| 2 | // |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
Jia Liu | b22310f | 2012-02-18 12:03:15 +0000 | [diff] [blame] | 7 | // |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // This file describes the integer arithmetic instructions in the X86 |
| 11 | // architecture. |
| 12 | // |
| 13 | //===----------------------------------------------------------------------===// |
| 14 | |
| 15 | //===----------------------------------------------------------------------===// |
| 16 | // LEA - Load Effective Address |
| 17 | |
| 18 | let neverHasSideEffects = 1 in |
| 19 | def LEA16r : I<0x8D, MRMSrcMem, |
| 20 | (outs GR16:$dst), (ins i32mem:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 21 | "lea{w}\t{$src|$dst}, {$dst|$src}", [], IIC_LEA_16>, OpSize; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 22 | let isReMaterializable = 1 in |
| 23 | def LEA32r : I<0x8D, MRMSrcMem, |
| 24 | (outs GR32:$dst), (ins i32mem:$src), |
| 25 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 26 | [(set GR32:$dst, lea32addr:$src)], IIC_LEA>, |
| 27 | Requires<[In32BitMode]>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 28 | |
| 29 | def LEA64_32r : I<0x8D, MRMSrcMem, |
| 30 | (outs GR32:$dst), (ins lea64_32mem:$src), |
| 31 | "lea{l}\t{$src|$dst}, {$dst|$src}", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 32 | [(set GR32:$dst, lea32addr:$src)], IIC_LEA>, |
| 33 | Requires<[In64BitMode]>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 34 | |
| 35 | let isReMaterializable = 1 in |
| 36 | def LEA64r : RI<0x8D, MRMSrcMem, (outs GR64:$dst), (ins i64mem:$src), |
| 37 | "lea{q}\t{$src|$dst}, {$dst|$src}", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 38 | [(set GR64:$dst, lea64addr:$src)], IIC_LEA>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 39 | |
| 40 | |
| 41 | |
| 42 | //===----------------------------------------------------------------------===// |
| 43 | // Fixed-Register Multiplication and Division Instructions. |
| 44 | // |
| 45 | |
| 46 | // Extra precision multiplication |
| 47 | |
| 48 | // AL is really implied by AX, but the registers in Defs must match the |
| 49 | // SDNode results (i8, i32). |
| 50 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
| 51 | def MUL8r : I<0xF6, MRM4r, (outs), (ins GR8:$src), "mul{b}\t$src", |
| 52 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 53 | // This probably ought to be moved to a def : Pat<> if the |
| 54 | // syntax can be accepted. |
| 55 | [(set AL, (mul AL, GR8:$src)), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 56 | (implicit EFLAGS)], IIC_MUL8>; // AL,AH = AL*GR8 |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 57 | |
| 58 | let Defs = [AX,DX,EFLAGS], Uses = [AX], neverHasSideEffects = 1 in |
| 59 | def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 60 | "mul{w}\t$src", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 61 | [], IIC_MUL16_REG>, OpSize; // AX,DX = AX*GR16 |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 62 | |
| 63 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], neverHasSideEffects = 1 in |
| 64 | def MUL32r : I<0xF7, MRM4r, (outs), (ins GR32:$src), |
Chris Lattner | 364bb0a | 2010-12-05 07:30:36 +0000 | [diff] [blame] | 65 | "mul{l}\t$src", // EAX,EDX = EAX*GR32 |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 66 | [/*(set EAX, EDX, EFLAGS, (X86umul_flag EAX, GR32:$src))*/], |
| 67 | IIC_MUL32_REG>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 68 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], neverHasSideEffects = 1 in |
| 69 | def MUL64r : RI<0xF7, MRM4r, (outs), (ins GR64:$src), |
Chris Lattner | 364bb0a | 2010-12-05 07:30:36 +0000 | [diff] [blame] | 70 | "mul{q}\t$src", // RAX,RDX = RAX*GR64 |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 71 | [/*(set RAX, RDX, EFLAGS, (X86umul_flag RAX, GR64:$src))*/], |
| 72 | IIC_MUL64>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 73 | |
| 74 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
| 75 | def MUL8m : I<0xF6, MRM4m, (outs), (ins i8mem :$src), |
| 76 | "mul{b}\t$src", |
| 77 | // FIXME: Used for 8-bit mul, ignore result upper 8 bits. |
| 78 | // This probably ought to be moved to a def : Pat<> if the |
| 79 | // syntax can be accepted. |
| 80 | [(set AL, (mul AL, (loadi8 addr:$src))), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 81 | (implicit EFLAGS)], IIC_MUL8>; // AL,AH = AL*[mem8] |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 82 | |
| 83 | let mayLoad = 1, neverHasSideEffects = 1 in { |
| 84 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
| 85 | def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src), |
| 86 | "mul{w}\t$src", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 87 | [], IIC_MUL16_MEM>, OpSize; // AX,DX = AX*[mem16] |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 88 | |
| 89 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
| 90 | def MUL32m : I<0xF7, MRM4m, (outs), (ins i32mem:$src), |
| 91 | "mul{l}\t$src", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 92 | [], IIC_MUL32_MEM>; // EAX,EDX = EAX*[mem32] |
Craig Topper | 7412aa9 | 2011-10-22 23:13:53 +0000 | [diff] [blame] | 93 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 94 | def MUL64m : RI<0xF7, MRM4m, (outs), (ins i64mem:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 95 | "mul{q}\t$src", [], IIC_MUL64>; // RAX,RDX = RAX*[mem64] |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 96 | } |
| 97 | |
| 98 | let neverHasSideEffects = 1 in { |
| 99 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 100 | def IMUL8r : I<0xF6, MRM5r, (outs), (ins GR8:$src), "imul{b}\t$src", [], |
| 101 | IIC_IMUL8>; // AL,AH = AL*GR8 |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 102 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 103 | def IMUL16r : I<0xF7, MRM5r, (outs), (ins GR16:$src), "imul{w}\t$src", [], |
| 104 | IIC_IMUL16_RR>, OpSize; // AX,DX = AX*GR16 |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 105 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 106 | def IMUL32r : I<0xF7, MRM5r, (outs), (ins GR32:$src), "imul{l}\t$src", [], |
| 107 | IIC_IMUL32_RR>; // EAX,EDX = EAX*GR32 |
Craig Topper | 7412aa9 | 2011-10-22 23:13:53 +0000 | [diff] [blame] | 108 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 109 | def IMUL64r : RI<0xF7, MRM5r, (outs), (ins GR64:$src), "imul{q}\t$src", [], |
| 110 | IIC_IMUL64_RR>; // RAX,RDX = RAX*GR64 |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 111 | |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 112 | let mayLoad = 1 in { |
| 113 | let Defs = [AL,EFLAGS,AX], Uses = [AL] in |
| 114 | def IMUL8m : I<0xF6, MRM5m, (outs), (ins i8mem :$src), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 115 | "imul{b}\t$src", [], IIC_IMUL8>; // AL,AH = AL*[mem8] |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 116 | let Defs = [AX,DX,EFLAGS], Uses = [AX] in |
| 117 | def IMUL16m : I<0xF7, MRM5m, (outs), (ins i16mem:$src), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 118 | "imul{w}\t$src", [], IIC_IMUL16_MEM>, OpSize; |
| 119 | // AX,DX = AX*[mem16] |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 120 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX] in |
| 121 | def IMUL32m : I<0xF7, MRM5m, (outs), (ins i32mem:$src), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 122 | "imul{l}\t$src", [], IIC_IMUL32_MEM>; // EAX,EDX = EAX*[mem32] |
Craig Topper | 7412aa9 | 2011-10-22 23:13:53 +0000 | [diff] [blame] | 123 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX] in |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 124 | def IMUL64m : RI<0xF7, MRM5m, (outs), (ins i64mem:$src), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 125 | "imul{q}\t$src", [], IIC_IMUL64>; // RAX,RDX = RAX*[mem64] |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 126 | } |
| 127 | } // neverHasSideEffects |
| 128 | |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 129 | |
| 130 | let Defs = [EFLAGS] in { |
| 131 | let Constraints = "$src1 = $dst" in { |
| 132 | |
| 133 | let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y |
| 134 | // Register-Register Signed Integer Multiply |
| 135 | def IMUL16rr : I<0xAF, MRMSrcReg, (outs GR16:$dst), (ins GR16:$src1,GR16:$src2), |
| 136 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
| 137 | [(set GR16:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 138 | (X86smul_flag GR16:$src1, GR16:$src2))], IIC_IMUL16_RR>, |
| 139 | TB, OpSize; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 140 | def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2), |
| 141 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
| 142 | [(set GR32:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 143 | (X86smul_flag GR32:$src1, GR32:$src2))], IIC_IMUL32_RR>, |
| 144 | TB; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 145 | def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst), |
| 146 | (ins GR64:$src1, GR64:$src2), |
| 147 | "imul{q}\t{$src2, $dst|$dst, $src2}", |
| 148 | [(set GR64:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 149 | (X86smul_flag GR64:$src1, GR64:$src2))], IIC_IMUL64_RR>, |
| 150 | TB; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | // Register-Memory Signed Integer Multiply |
| 154 | def IMUL16rm : I<0xAF, MRMSrcMem, (outs GR16:$dst), |
| 155 | (ins GR16:$src1, i16mem:$src2), |
| 156 | "imul{w}\t{$src2, $dst|$dst, $src2}", |
| 157 | [(set GR16:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 158 | (X86smul_flag GR16:$src1, (load addr:$src2)))], |
| 159 | IIC_IMUL16_RM>, |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 160 | TB, OpSize; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 161 | def IMUL32rm : I<0xAF, MRMSrcMem, (outs GR32:$dst), |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 162 | (ins GR32:$src1, i32mem:$src2), |
| 163 | "imul{l}\t{$src2, $dst|$dst, $src2}", |
| 164 | [(set GR32:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 165 | (X86smul_flag GR32:$src1, (load addr:$src2)))], |
| 166 | IIC_IMUL32_RM>, |
| 167 | TB; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 168 | def IMUL64rm : RI<0xAF, MRMSrcMem, (outs GR64:$dst), |
| 169 | (ins GR64:$src1, i64mem:$src2), |
| 170 | "imul{q}\t{$src2, $dst|$dst, $src2}", |
| 171 | [(set GR64:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 172 | (X86smul_flag GR64:$src1, (load addr:$src2)))], |
| 173 | IIC_IMUL64_RM>, |
| 174 | TB; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 175 | } // Constraints = "$src1 = $dst" |
| 176 | |
| 177 | } // Defs = [EFLAGS] |
| 178 | |
Chris Lattner | 0ab5e2c | 2011-04-15 05:18:47 +0000 | [diff] [blame] | 179 | // Surprisingly enough, these are not two address instructions! |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 180 | let Defs = [EFLAGS] in { |
| 181 | // Register-Integer Signed Integer Multiply |
| 182 | def IMUL16rri : Ii16<0x69, MRMSrcReg, // GR16 = GR16*I16 |
| 183 | (outs GR16:$dst), (ins GR16:$src1, i16imm:$src2), |
| 184 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 185 | [(set GR16:$dst, EFLAGS, |
| 186 | (X86smul_flag GR16:$src1, imm:$src2))], |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 187 | IIC_IMUL16_RRI>, OpSize; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 188 | def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // GR16 = GR16*I8 |
| 189 | (outs GR16:$dst), (ins GR16:$src1, i16i8imm:$src2), |
| 190 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 191 | [(set GR16:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 192 | (X86smul_flag GR16:$src1, i16immSExt8:$src2))], |
| 193 | IIC_IMUL16_RRI>, |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 194 | OpSize; |
| 195 | def IMUL32rri : Ii32<0x69, MRMSrcReg, // GR32 = GR32*I32 |
| 196 | (outs GR32:$dst), (ins GR32:$src1, i32imm:$src2), |
| 197 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 198 | [(set GR32:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 199 | (X86smul_flag GR32:$src1, imm:$src2))], |
| 200 | IIC_IMUL32_RRI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 201 | def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // GR32 = GR32*I8 |
| 202 | (outs GR32:$dst), (ins GR32:$src1, i32i8imm:$src2), |
| 203 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 204 | [(set GR32:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 205 | (X86smul_flag GR32:$src1, i32immSExt8:$src2))], |
| 206 | IIC_IMUL32_RRI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 207 | def IMUL64rri32 : RIi32<0x69, MRMSrcReg, // GR64 = GR64*I32 |
| 208 | (outs GR64:$dst), (ins GR64:$src1, i64i32imm:$src2), |
| 209 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 210 | [(set GR64:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 211 | (X86smul_flag GR64:$src1, i64immSExt32:$src2))], |
| 212 | IIC_IMUL64_RRI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 213 | def IMUL64rri8 : RIi8<0x6B, MRMSrcReg, // GR64 = GR64*I8 |
| 214 | (outs GR64:$dst), (ins GR64:$src1, i64i8imm:$src2), |
| 215 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 216 | [(set GR64:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 217 | (X86smul_flag GR64:$src1, i64immSExt8:$src2))], |
| 218 | IIC_IMUL64_RRI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 219 | |
| 220 | |
| 221 | // Memory-Integer Signed Integer Multiply |
| 222 | def IMUL16rmi : Ii16<0x69, MRMSrcMem, // GR16 = [mem16]*I16 |
| 223 | (outs GR16:$dst), (ins i16mem:$src1, i16imm:$src2), |
| 224 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 225 | [(set GR16:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 226 | (X86smul_flag (load addr:$src1), imm:$src2))], |
| 227 | IIC_IMUL16_RMI>, |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 228 | OpSize; |
| 229 | def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // GR16 = [mem16]*I8 |
| 230 | (outs GR16:$dst), (ins i16mem:$src1, i16i8imm :$src2), |
| 231 | "imul{w}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 232 | [(set GR16:$dst, EFLAGS, |
| 233 | (X86smul_flag (load addr:$src1), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 234 | i16immSExt8:$src2))], IIC_IMUL16_RMI>, |
| 235 | OpSize; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 236 | def IMUL32rmi : Ii32<0x69, MRMSrcMem, // GR32 = [mem32]*I32 |
| 237 | (outs GR32:$dst), (ins i32mem:$src1, i32imm:$src2), |
| 238 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 239 | [(set GR32:$dst, EFLAGS, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 240 | (X86smul_flag (load addr:$src1), imm:$src2))], |
| 241 | IIC_IMUL32_RMI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 242 | def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // GR32 = [mem32]*I8 |
| 243 | (outs GR32:$dst), (ins i32mem:$src1, i32i8imm: $src2), |
| 244 | "imul{l}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 245 | [(set GR32:$dst, EFLAGS, |
| 246 | (X86smul_flag (load addr:$src1), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 247 | i32immSExt8:$src2))], |
| 248 | IIC_IMUL32_RMI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 249 | def IMUL64rmi32 : RIi32<0x69, MRMSrcMem, // GR64 = [mem64]*I32 |
| 250 | (outs GR64:$dst), (ins i64mem:$src1, i64i32imm:$src2), |
| 251 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 252 | [(set GR64:$dst, EFLAGS, |
| 253 | (X86smul_flag (load addr:$src1), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 254 | i64immSExt32:$src2))], |
| 255 | IIC_IMUL64_RMI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 256 | def IMUL64rmi8 : RIi8<0x6B, MRMSrcMem, // GR64 = [mem64]*I8 |
| 257 | (outs GR64:$dst), (ins i64mem:$src1, i64i8imm: $src2), |
| 258 | "imul{q}\t{$src2, $src1, $dst|$dst, $src1, $src2}", |
| 259 | [(set GR64:$dst, EFLAGS, |
| 260 | (X86smul_flag (load addr:$src1), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 261 | i64immSExt8:$src2))], |
| 262 | IIC_IMUL64_RMI>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 263 | } // Defs = [EFLAGS] |
| 264 | |
| 265 | |
| 266 | |
| 267 | |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 268 | // unsigned division/remainder |
| 269 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
| 270 | def DIV8r : I<0xF6, MRM6r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 271 | "div{b}\t$src", [], IIC_DIV8_REG>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 272 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
| 273 | def DIV16r : I<0xF7, MRM6r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 274 | "div{w}\t$src", [], IIC_DIV16>, OpSize; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 275 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
| 276 | def DIV32r : I<0xF7, MRM6r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 277 | "div{l}\t$src", [], IIC_DIV32>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 278 | // RDX:RAX/r64 = RAX,RDX |
| 279 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in |
| 280 | def DIV64r : RI<0xF7, MRM6r, (outs), (ins GR64:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 281 | "div{q}\t$src", [], IIC_DIV64>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 282 | |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 283 | let mayLoad = 1 in { |
| 284 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
| 285 | def DIV8m : I<0xF6, MRM6m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 286 | "div{b}\t$src", [], IIC_DIV8_MEM>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 287 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
| 288 | def DIV16m : I<0xF7, MRM6m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 289 | "div{w}\t$src", [], IIC_DIV16>, OpSize; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 290 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 291 | def DIV32m : I<0xF7, MRM6m, (outs), (ins i32mem:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 292 | "div{l}\t$src", [], IIC_DIV32>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 293 | // RDX:RAX/[mem64] = RAX,RDX |
| 294 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in |
| 295 | def DIV64m : RI<0xF7, MRM6m, (outs), (ins i64mem:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 296 | "div{q}\t$src", [], IIC_DIV64>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | // Signed division/remainder. |
| 300 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
| 301 | def IDIV8r : I<0xF6, MRM7r, (outs), (ins GR8:$src), // AX/r8 = AL,AH |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 302 | "idiv{b}\t$src", [], IIC_IDIV8>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 303 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
| 304 | def IDIV16r: I<0xF7, MRM7r, (outs), (ins GR16:$src), // DX:AX/r16 = AX,DX |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 305 | "idiv{w}\t$src", [], IIC_IDIV16>, OpSize; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 306 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in |
| 307 | def IDIV32r: I<0xF7, MRM7r, (outs), (ins GR32:$src), // EDX:EAX/r32 = EAX,EDX |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 308 | "idiv{l}\t$src", [], IIC_IDIV32>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 309 | // RDX:RAX/r64 = RAX,RDX |
| 310 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in |
| 311 | def IDIV64r: RI<0xF7, MRM7r, (outs), (ins GR64:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 312 | "idiv{q}\t$src", [], IIC_IDIV64>; |
Craig Topper | 7412aa9 | 2011-10-22 23:13:53 +0000 | [diff] [blame] | 313 | |
| 314 | let mayLoad = 1 in { |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 315 | let Defs = [AL,EFLAGS,AX], Uses = [AX] in |
| 316 | def IDIV8m : I<0xF6, MRM7m, (outs), (ins i8mem:$src), // AX/[mem8] = AL,AH |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 317 | "idiv{b}\t$src", [], IIC_IDIV8>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 318 | let Defs = [AX,DX,EFLAGS], Uses = [AX,DX] in |
| 319 | def IDIV16m: I<0xF7, MRM7m, (outs), (ins i16mem:$src), // DX:AX/[mem16] = AX,DX |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 320 | "idiv{w}\t$src", [], IIC_IDIV16>, OpSize; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 321 | let Defs = [EAX,EDX,EFLAGS], Uses = [EAX,EDX] in // EDX:EAX/[mem32] = EAX,EDX |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 322 | def IDIV32m: I<0xF7, MRM7m, (outs), (ins i32mem:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 323 | "idiv{l}\t$src", [], IIC_IDIV32>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 324 | let Defs = [RAX,RDX,EFLAGS], Uses = [RAX,RDX] in // RDX:RAX/[mem64] = RAX,RDX |
| 325 | def IDIV64m: RI<0xF7, MRM7m, (outs), (ins i64mem:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 326 | "idiv{q}\t$src", [], IIC_IDIV64>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 327 | } |
| 328 | |
| 329 | //===----------------------------------------------------------------------===// |
| 330 | // Two address Instructions. |
| 331 | // |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 332 | |
| 333 | // unary instructions |
| 334 | let CodeSize = 2 in { |
| 335 | let Defs = [EFLAGS] in { |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 336 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 337 | def NEG8r : I<0xF6, MRM3r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 338 | "neg{b}\t$dst", |
| 339 | [(set GR8:$dst, (ineg GR8:$src1)), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 340 | (implicit EFLAGS)], IIC_UNARY_REG>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 341 | def NEG16r : I<0xF7, MRM3r, (outs GR16:$dst), (ins GR16:$src1), |
| 342 | "neg{w}\t$dst", |
| 343 | [(set GR16:$dst, (ineg GR16:$src1)), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 344 | (implicit EFLAGS)], IIC_UNARY_REG>, OpSize; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 345 | def NEG32r : I<0xF7, MRM3r, (outs GR32:$dst), (ins GR32:$src1), |
| 346 | "neg{l}\t$dst", |
| 347 | [(set GR32:$dst, (ineg GR32:$src1)), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 348 | (implicit EFLAGS)], IIC_UNARY_REG>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 349 | def NEG64r : RI<0xF7, MRM3r, (outs GR64:$dst), (ins GR64:$src1), "neg{q}\t$dst", |
| 350 | [(set GR64:$dst, (ineg GR64:$src1)), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 351 | (implicit EFLAGS)], IIC_UNARY_REG>; |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 352 | } // Constraints = "$src1 = $dst" |
| 353 | |
| 354 | def NEG8m : I<0xF6, MRM3m, (outs), (ins i8mem :$dst), |
| 355 | "neg{b}\t$dst", |
| 356 | [(store (ineg (loadi8 addr:$dst)), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 357 | (implicit EFLAGS)], IIC_UNARY_MEM>; |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 358 | def NEG16m : I<0xF7, MRM3m, (outs), (ins i16mem:$dst), |
| 359 | "neg{w}\t$dst", |
| 360 | [(store (ineg (loadi16 addr:$dst)), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 361 | (implicit EFLAGS)], IIC_UNARY_MEM>, OpSize; |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 362 | def NEG32m : I<0xF7, MRM3m, (outs), (ins i32mem:$dst), |
| 363 | "neg{l}\t$dst", |
| 364 | [(store (ineg (loadi32 addr:$dst)), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 365 | (implicit EFLAGS)], IIC_UNARY_MEM>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 366 | def NEG64m : RI<0xF7, MRM3m, (outs), (ins i64mem:$dst), "neg{q}\t$dst", |
| 367 | [(store (ineg (loadi64 addr:$dst)), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 368 | (implicit EFLAGS)], IIC_UNARY_MEM>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 369 | } // Defs = [EFLAGS] |
| 370 | |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 371 | |
Chris Lattner | 13111b0 | 2010-10-05 21:09:45 +0000 | [diff] [blame] | 372 | // Note: NOT does not set EFLAGS! |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 373 | |
| 374 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 375 | // Match xor -1 to not. Favors these over a move imm + xor to save code size. |
| 376 | let AddedComplexity = 15 in { |
| 377 | def NOT8r : I<0xF6, MRM2r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 378 | "not{b}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 379 | [(set GR8:$dst, (not GR8:$src1))], IIC_UNARY_REG>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 380 | def NOT16r : I<0xF7, MRM2r, (outs GR16:$dst), (ins GR16:$src1), |
| 381 | "not{w}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 382 | [(set GR16:$dst, (not GR16:$src1))], IIC_UNARY_REG>, OpSize; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 383 | def NOT32r : I<0xF7, MRM2r, (outs GR32:$dst), (ins GR32:$src1), |
| 384 | "not{l}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 385 | [(set GR32:$dst, (not GR32:$src1))], IIC_UNARY_REG>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 386 | def NOT64r : RI<0xF7, MRM2r, (outs GR64:$dst), (ins GR64:$src1), "not{q}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 387 | [(set GR64:$dst, (not GR64:$src1))], IIC_UNARY_REG>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 388 | } |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 389 | } // Constraints = "$src1 = $dst" |
| 390 | |
| 391 | def NOT8m : I<0xF6, MRM2m, (outs), (ins i8mem :$dst), |
| 392 | "not{b}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 393 | [(store (not (loadi8 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>; |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 394 | def NOT16m : I<0xF7, MRM2m, (outs), (ins i16mem:$dst), |
| 395 | "not{w}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 396 | [(store (not (loadi16 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>, |
| 397 | OpSize; |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 398 | def NOT32m : I<0xF7, MRM2m, (outs), (ins i32mem:$dst), |
| 399 | "not{l}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 400 | [(store (not (loadi32 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 401 | def NOT64m : RI<0xF7, MRM2m, (outs), (ins i64mem:$dst), "not{q}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 402 | [(store (not (loadi64 addr:$dst)), addr:$dst)], IIC_UNARY_MEM>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 403 | } // CodeSize |
| 404 | |
| 405 | // TODO: inc/dec is slow for P4, but fast for Pentium-M. |
| 406 | let Defs = [EFLAGS] in { |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 407 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 408 | let CodeSize = 2 in |
| 409 | def INC8r : I<0xFE, MRM0r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 410 | "inc{b}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 411 | [(set GR8:$dst, EFLAGS, (X86inc_flag GR8:$src1))], |
| 412 | IIC_UNARY_REG>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 413 | |
| 414 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 415 | def INC16r : I<0x40, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 416 | "inc{w}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 417 | [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], IIC_UNARY_REG>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 418 | OpSize, Requires<[In32BitMode]>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 419 | def INC32r : I<0x40, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 420 | "inc{l}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 421 | [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))], |
| 422 | IIC_UNARY_REG>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 423 | Requires<[In32BitMode]>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 424 | def INC64r : RI<0xFF, MRM0r, (outs GR64:$dst), (ins GR64:$src1), "inc{q}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 425 | [(set GR64:$dst, EFLAGS, (X86inc_flag GR64:$src1))], |
| 426 | IIC_UNARY_REG>; |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 427 | } // isConvertibleToThreeAddress = 1, CodeSize = 1 |
| 428 | |
| 429 | |
| 430 | // In 64-bit mode, single byte INC and DEC cannot be encoded. |
| 431 | let isConvertibleToThreeAddress = 1, CodeSize = 2 in { |
| 432 | // Can transform into LEA. |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 433 | def INC64_16r : I<0xFF, MRM0r, (outs GR16:$dst), (ins GR16:$src1), |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 434 | "inc{w}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 435 | [(set GR16:$dst, EFLAGS, (X86inc_flag GR16:$src1))], |
| 436 | IIC_UNARY_REG>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 437 | OpSize, Requires<[In64BitMode]>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 438 | def INC64_32r : I<0xFF, MRM0r, (outs GR32:$dst), (ins GR32:$src1), |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 439 | "inc{l}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 440 | [(set GR32:$dst, EFLAGS, (X86inc_flag GR32:$src1))], |
| 441 | IIC_UNARY_REG>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 442 | Requires<[In64BitMode]>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 443 | def DEC64_16r : I<0xFF, MRM1r, (outs GR16:$dst), (ins GR16:$src1), |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 444 | "dec{w}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 445 | [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))], |
| 446 | IIC_UNARY_REG>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 447 | OpSize, Requires<[In64BitMode]>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 448 | def DEC64_32r : I<0xFF, MRM1r, (outs GR32:$dst), (ins GR32:$src1), |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 449 | "dec{l}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 450 | [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))], |
| 451 | IIC_UNARY_REG>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 452 | Requires<[In64BitMode]>; |
| 453 | } // isConvertibleToThreeAddress = 1, CodeSize = 2 |
| 454 | |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 455 | } // Constraints = "$src1 = $dst" |
| 456 | |
| 457 | let CodeSize = 2 in { |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 458 | def INC8m : I<0xFE, MRM0m, (outs), (ins i8mem :$dst), "inc{b}\t$dst", |
| 459 | [(store (add (loadi8 addr:$dst), 1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 460 | (implicit EFLAGS)], IIC_UNARY_MEM>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 461 | def INC16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
| 462 | [(store (add (loadi16 addr:$dst), 1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 463 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 464 | OpSize, Requires<[In32BitMode]>; |
| 465 | def INC32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
| 466 | [(store (add (loadi32 addr:$dst), 1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 467 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 468 | Requires<[In32BitMode]>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 469 | def INC64m : RI<0xFF, MRM0m, (outs), (ins i64mem:$dst), "inc{q}\t$dst", |
| 470 | [(store (add (loadi64 addr:$dst), 1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 471 | (implicit EFLAGS)], IIC_UNARY_MEM>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 472 | |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 473 | // These are duplicates of their 32-bit counterparts. Only needed so X86 knows |
| 474 | // how to unfold them. |
| 475 | // FIXME: What is this for?? |
| 476 | def INC64_16m : I<0xFF, MRM0m, (outs), (ins i16mem:$dst), "inc{w}\t$dst", |
| 477 | [(store (add (loadi16 addr:$dst), 1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 478 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 479 | OpSize, Requires<[In64BitMode]>; |
| 480 | def INC64_32m : I<0xFF, MRM0m, (outs), (ins i32mem:$dst), "inc{l}\t$dst", |
| 481 | [(store (add (loadi32 addr:$dst), 1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 482 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 483 | Requires<[In64BitMode]>; |
| 484 | def DEC64_16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
| 485 | [(store (add (loadi16 addr:$dst), -1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 486 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 487 | OpSize, Requires<[In64BitMode]>; |
| 488 | def DEC64_32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
| 489 | [(store (add (loadi32 addr:$dst), -1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 490 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 27c763d | 2010-10-05 20:35:37 +0000 | [diff] [blame] | 491 | Requires<[In64BitMode]>; |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 492 | } // CodeSize = 2 |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 493 | |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 494 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 495 | let CodeSize = 2 in |
| 496 | def DEC8r : I<0xFE, MRM1r, (outs GR8 :$dst), (ins GR8 :$src1), |
| 497 | "dec{b}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 498 | [(set GR8:$dst, EFLAGS, (X86dec_flag GR8:$src1))], |
| 499 | IIC_UNARY_REG>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 500 | let isConvertibleToThreeAddress = 1, CodeSize = 1 in { // Can xform into LEA. |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 501 | def DEC16r : I<0x48, AddRegFrm, (outs GR16:$dst), (ins GR16:$src1), |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 502 | "dec{w}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 503 | [(set GR16:$dst, EFLAGS, (X86dec_flag GR16:$src1))], |
| 504 | IIC_UNARY_REG>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 505 | OpSize, Requires<[In32BitMode]>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 506 | def DEC32r : I<0x48, AddRegFrm, (outs GR32:$dst), (ins GR32:$src1), |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 507 | "dec{l}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 508 | [(set GR32:$dst, EFLAGS, (X86dec_flag GR32:$src1))], |
| 509 | IIC_UNARY_REG>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 510 | Requires<[In32BitMode]>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 511 | def DEC64r : RI<0xFF, MRM1r, (outs GR64:$dst), (ins GR64:$src1), "dec{q}\t$dst", |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 512 | [(set GR64:$dst, EFLAGS, (X86dec_flag GR64:$src1))], |
| 513 | IIC_UNARY_REG>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 514 | } // CodeSize = 2 |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 515 | } // Constraints = "$src1 = $dst" |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 516 | |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 517 | |
| 518 | let CodeSize = 2 in { |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 519 | def DEC8m : I<0xFE, MRM1m, (outs), (ins i8mem :$dst), "dec{b}\t$dst", |
| 520 | [(store (add (loadi8 addr:$dst), -1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 521 | (implicit EFLAGS)], IIC_UNARY_MEM>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 522 | def DEC16m : I<0xFF, MRM1m, (outs), (ins i16mem:$dst), "dec{w}\t$dst", |
| 523 | [(store (add (loadi16 addr:$dst), -1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 524 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 525 | OpSize, Requires<[In32BitMode]>; |
| 526 | def DEC32m : I<0xFF, MRM1m, (outs), (ins i32mem:$dst), "dec{l}\t$dst", |
| 527 | [(store (add (loadi32 addr:$dst), -1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 528 | (implicit EFLAGS)], IIC_UNARY_MEM>, |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 529 | Requires<[In32BitMode]>; |
Chris Lattner | c2f5e57 | 2010-10-05 20:23:31 +0000 | [diff] [blame] | 530 | def DEC64m : RI<0xFF, MRM1m, (outs), (ins i64mem:$dst), "dec{q}\t$dst", |
| 531 | [(store (add (loadi64 addr:$dst), -1), addr:$dst), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 532 | (implicit EFLAGS)], IIC_UNARY_MEM>; |
Chris Lattner | 182e87c | 2010-10-05 16:52:25 +0000 | [diff] [blame] | 533 | } // CodeSize = 2 |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 534 | } // Defs = [EFLAGS] |
| 535 | |
Chris Lattner | b6da2be | 2010-10-06 05:20:57 +0000 | [diff] [blame] | 536 | |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 537 | /// X86TypeInfo - This is a bunch of information that describes relevant X86 |
| 538 | /// information about value types. For example, it can tell you what the |
| 539 | /// register class and preferred load to use. |
| 540 | class X86TypeInfo<ValueType vt, string instrsuffix, RegisterClass regclass, |
Chris Lattner | e17d721 | 2010-10-07 00:12:45 +0000 | [diff] [blame] | 541 | PatFrag loadnode, X86MemOperand memoperand, ImmType immkind, |
| 542 | Operand immoperand, SDPatternOperator immoperator, |
| 543 | Operand imm8operand, SDPatternOperator imm8operator, |
Chris Lattner | a46073b | 2010-10-06 05:28:38 +0000 | [diff] [blame] | 544 | bit hasOddOpcode, bit hasOpSizePrefix, bit hasREX_WPrefix> { |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 545 | /// VT - This is the value type itself. |
| 546 | ValueType VT = vt; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 547 | |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 548 | /// InstrSuffix - This is the suffix used on instructions with this type. For |
| 549 | /// example, i8 -> "b", i16 -> "w", i32 -> "l", i64 -> "q". |
| 550 | string InstrSuffix = instrsuffix; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 551 | |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 552 | /// RegClass - This is the register class associated with this type. For |
| 553 | /// example, i8 -> GR8, i16 -> GR16, i32 -> GR32, i64 -> GR64. |
| 554 | RegisterClass RegClass = regclass; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 555 | |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 556 | /// LoadNode - This is the load node associated with this type. For |
| 557 | /// example, i8 -> loadi8, i16 -> loadi16, i32 -> loadi32, i64 -> loadi64. |
| 558 | PatFrag LoadNode = loadnode; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 559 | |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 560 | /// MemOperand - This is the memory operand associated with this type. For |
| 561 | /// example, i8 -> i8mem, i16 -> i16mem, i32 -> i32mem, i64 -> i64mem. |
| 562 | X86MemOperand MemOperand = memoperand; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 563 | |
Chris Lattner | 6e85be2 | 2010-10-06 05:55:42 +0000 | [diff] [blame] | 564 | /// ImmEncoding - This is the encoding of an immediate of this type. For |
| 565 | /// example, i8 -> Imm8, i16 -> Imm16, i32 -> Imm32. Note that i64 -> Imm32 |
| 566 | /// since the immediate fields of i64 instructions is a 32-bit sign extended |
| 567 | /// value. |
| 568 | ImmType ImmEncoding = immkind; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 569 | |
Chris Lattner | 6e85be2 | 2010-10-06 05:55:42 +0000 | [diff] [blame] | 570 | /// ImmOperand - This is the operand kind of an immediate of this type. For |
| 571 | /// example, i8 -> i8imm, i16 -> i16imm, i32 -> i32imm. Note that i64 -> |
| 572 | /// i64i32imm since the immediate fields of i64 instructions is a 32-bit sign |
| 573 | /// extended value. |
| 574 | Operand ImmOperand = immoperand; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 575 | |
Chris Lattner | 356f16c | 2010-10-07 00:01:39 +0000 | [diff] [blame] | 576 | /// ImmOperator - This is the operator that should be used to match an |
| 577 | /// immediate of this kind in a pattern (e.g. imm, or i64immSExt32). |
| 578 | SDPatternOperator ImmOperator = immoperator; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 579 | |
Chris Lattner | e17d721 | 2010-10-07 00:12:45 +0000 | [diff] [blame] | 580 | /// Imm8Operand - This is the operand kind to use for an imm8 of this type. |
| 581 | /// For example, i8 -> <invalid>, i16 -> i16i8imm, i32 -> i32i8imm. This is |
| 582 | /// only used for instructions that have a sign-extended imm8 field form. |
| 583 | Operand Imm8Operand = imm8operand; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 584 | |
Chris Lattner | e17d721 | 2010-10-07 00:12:45 +0000 | [diff] [blame] | 585 | /// Imm8Operator - This is the operator that should be used to match an 8-bit |
| 586 | /// sign extended immediate of this kind in a pattern (e.g. imm16immSExt8). |
| 587 | SDPatternOperator Imm8Operator = imm8operator; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 588 | |
Chris Lattner | a46073b | 2010-10-06 05:28:38 +0000 | [diff] [blame] | 589 | /// HasOddOpcode - This bit is true if the instruction should have an odd (as |
| 590 | /// opposed to even) opcode. Operations on i8 are usually even, operations on |
| 591 | /// other datatypes are odd. |
| 592 | bit HasOddOpcode = hasOddOpcode; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 593 | |
Chris Lattner | b6da2be | 2010-10-06 05:20:57 +0000 | [diff] [blame] | 594 | /// HasOpSizePrefix - This bit is set to true if the instruction should have |
| 595 | /// the 0x66 operand size prefix. This is set for i16 types. |
| 596 | bit HasOpSizePrefix = hasOpSizePrefix; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 597 | |
Chris Lattner | b6da2be | 2010-10-06 05:20:57 +0000 | [diff] [blame] | 598 | /// HasREX_WPrefix - This bit is set to true if the instruction should have |
| 599 | /// the 0x40 REX prefix. This is set for i64 types. |
| 600 | bit HasREX_WPrefix = hasREX_WPrefix; |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 601 | } |
Chris Lattner | 7359194 | 2010-10-05 23:32:05 +0000 | [diff] [blame] | 602 | |
Chris Lattner | e17d721 | 2010-10-07 00:12:45 +0000 | [diff] [blame] | 603 | def invalid_node : SDNode<"<<invalid_node>>", SDTIntLeaf,[],"<<invalid_node>>">; |
| 604 | |
| 605 | |
| 606 | def Xi8 : X86TypeInfo<i8 , "b", GR8 , loadi8 , i8mem , |
| 607 | Imm8 , i8imm , imm, i8imm , invalid_node, |
| 608 | 0, 0, 0>; |
| 609 | def Xi16 : X86TypeInfo<i16, "w", GR16, loadi16, i16mem, |
| 610 | Imm16, i16imm, imm, i16i8imm, i16immSExt8, |
| 611 | 1, 1, 0>; |
| 612 | def Xi32 : X86TypeInfo<i32, "l", GR32, loadi32, i32mem, |
| 613 | Imm32, i32imm, imm, i32i8imm, i32immSExt8, |
| 614 | 1, 0, 0>; |
| 615 | def Xi64 : X86TypeInfo<i64, "q", GR64, loadi64, i64mem, |
| 616 | Imm32, i64i32imm, i64immSExt32, i64i8imm, i64immSExt8, |
| 617 | 1, 0, 1>; |
Chris Lattner | b6da2be | 2010-10-06 05:20:57 +0000 | [diff] [blame] | 618 | |
| 619 | /// ITy - This instruction base class takes the type info for the instruction. |
| 620 | /// Using this, it: |
| 621 | /// 1. Concatenates together the instruction mnemonic with the appropriate |
| 622 | /// suffix letter, a tab, and the arguments. |
| 623 | /// 2. Infers whether the instruction should have a 0x66 prefix byte. |
| 624 | /// 3. Infers whether the instruction should have a 0x40 REX_W prefix. |
Chris Lattner | a46073b | 2010-10-06 05:28:38 +0000 | [diff] [blame] | 625 | /// 4. Infers whether the low bit of the opcode should be 0 (for i8 operations) |
| 626 | /// or 1 (for i16,i32,i64 operations). |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 627 | class ITy<bits<8> opcode, Format f, X86TypeInfo typeinfo, dag outs, dag ins, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 628 | string mnemonic, string args, list<dag> pattern, |
| 629 | InstrItinClass itin = IIC_BIN_NONMEM> |
Chris Lattner | a46073b | 2010-10-06 05:28:38 +0000 | [diff] [blame] | 630 | : I<{opcode{7}, opcode{6}, opcode{5}, opcode{4}, |
| 631 | opcode{3}, opcode{2}, opcode{1}, typeinfo.HasOddOpcode }, |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 632 | f, outs, ins, |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 633 | !strconcat(mnemonic, "{", typeinfo.InstrSuffix, "}\t", args), pattern, |
| 634 | itin> { |
Chris Lattner | b6da2be | 2010-10-06 05:20:57 +0000 | [diff] [blame] | 635 | |
| 636 | // Infer instruction prefixes from type info. |
| 637 | let hasOpSizePrefix = typeinfo.HasOpSizePrefix; |
| 638 | let hasREX_WPrefix = typeinfo.HasREX_WPrefix; |
| 639 | } |
Chris Lattner | 1fc81e9 | 2010-10-06 00:45:24 +0000 | [diff] [blame] | 640 | |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 641 | // BinOpRR - Instructions like "add reg, reg, reg". |
| 642 | class BinOpRR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 643 | dag outlist, list<dag> pattern, InstrItinClass itin, |
| 644 | Format f = MRMDestReg> |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 645 | : ITy<opcode, f, typeinfo, outlist, |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 646 | (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 647 | mnemonic, "{$src2, $src1|$src1, $src2}", pattern, itin>; |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 648 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 649 | // BinOpRR_R - Instructions like "add reg, reg, reg", where the pattern has |
| 650 | // just a regclass (no eflags) as a result. |
| 651 | class BinOpRR_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 652 | SDNode opnode> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 653 | : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 654 | [(set typeinfo.RegClass:$dst, |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 655 | (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))], |
| 656 | IIC_BIN_NONMEM>; |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 657 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 658 | // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has |
| 659 | // just a EFLAGS as a result. |
| 660 | class BinOpRR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 661 | SDPatternOperator opnode, Format f = MRMDestReg> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 662 | : BinOpRR<opcode, mnemonic, typeinfo, (outs), |
| 663 | [(set EFLAGS, |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 664 | (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))], |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 665 | IIC_BIN_NONMEM, f>; |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 666 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 667 | // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has |
| 668 | // both a regclass and EFLAGS as a result. |
| 669 | class BinOpRR_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 670 | SDNode opnode> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 671 | : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 672 | [(set typeinfo.RegClass:$dst, EFLAGS, |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 673 | (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))], |
| 674 | IIC_BIN_NONMEM>; |
Chris Lattner | 7359194 | 2010-10-05 23:32:05 +0000 | [diff] [blame] | 675 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 676 | // BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has |
| 677 | // both a regclass and EFLAGS as a result, and has EFLAGS as input. |
| 678 | class BinOpRR_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 679 | SDNode opnode> |
| 680 | : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), |
| 681 | [(set typeinfo.RegClass:$dst, EFLAGS, |
| 682 | (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2, |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 683 | EFLAGS))], IIC_BIN_NONMEM>; |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 684 | |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 685 | // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding). |
Chris Lattner | 94eff91 | 2010-10-06 05:35:22 +0000 | [diff] [blame] | 686 | class BinOpRR_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo> |
| 687 | : ITy<opcode, MRMSrcReg, typeinfo, |
| 688 | (outs typeinfo.RegClass:$dst), |
| 689 | (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 690 | mnemonic, "{$src2, $dst|$dst, $src2}", [], IIC_BIN_NONMEM> { |
Chris Lattner | 94eff91 | 2010-10-06 05:35:22 +0000 | [diff] [blame] | 691 | // The disassembler should know about this, but not the asmparser. |
| 692 | let isCodeGenOnly = 1; |
Craig Topper | 1b8c075 | 2012-12-26 21:30:22 +0000 | [diff] [blame] | 693 | let hasSideEffects = 0; |
Chris Lattner | 94eff91 | 2010-10-06 05:35:22 +0000 | [diff] [blame] | 694 | } |
Chris Lattner | eadaeaa | 2010-10-06 00:30:49 +0000 | [diff] [blame] | 695 | |
Craig Topper | a88e356 | 2011-09-11 21:41:45 +0000 | [diff] [blame] | 696 | // BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding). |
| 697 | class BinOpRR_F_Rev<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo> |
| 698 | : ITy<opcode, MRMSrcReg, typeinfo, (outs), |
| 699 | (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 700 | mnemonic, "{$src2, $src1|$src1, $src2}", [], IIC_BIN_NONMEM> { |
Craig Topper | a88e356 | 2011-09-11 21:41:45 +0000 | [diff] [blame] | 701 | // The disassembler should know about this, but not the asmparser. |
| 702 | let isCodeGenOnly = 1; |
| 703 | } |
| 704 | |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 705 | // BinOpRM - Instructions like "add reg, reg, [mem]". |
| 706 | class BinOpRM<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 707 | dag outlist, list<dag> pattern> |
| 708 | : ITy<opcode, MRMSrcMem, typeinfo, outlist, |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 709 | (ins typeinfo.RegClass:$src1, typeinfo.MemOperand:$src2), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 710 | mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM>; |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 711 | |
| 712 | // BinOpRM_R - Instructions like "add reg, reg, [mem]". |
| 713 | class BinOpRM_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 714 | SDNode opnode> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 715 | : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 716 | [(set typeinfo.RegClass:$dst, |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 717 | (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>; |
| 718 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 719 | // BinOpRM_F - Instructions like "cmp reg, [mem]". |
| 720 | class BinOpRM_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 721 | SDPatternOperator opnode> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 722 | : BinOpRM<opcode, mnemonic, typeinfo, (outs), |
| 723 | [(set EFLAGS, |
| 724 | (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>; |
| 725 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 726 | // BinOpRM_RF - Instructions like "add reg, reg, [mem]". |
| 727 | class BinOpRM_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | 9fece2b | 2010-10-07 20:06:24 +0000 | [diff] [blame] | 728 | SDNode opnode> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 729 | : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 730 | [(set typeinfo.RegClass:$dst, EFLAGS, |
Chris Lattner | 7bbd809 | 2010-10-06 04:58:43 +0000 | [diff] [blame] | 731 | (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2)))]>; |
Chris Lattner | eadaeaa | 2010-10-06 00:30:49 +0000 | [diff] [blame] | 732 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 733 | // BinOpRM_RFF - Instructions like "adc reg, reg, [mem]". |
| 734 | class BinOpRM_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 735 | SDNode opnode> |
| 736 | : BinOpRM<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), |
| 737 | [(set typeinfo.RegClass:$dst, EFLAGS, |
| 738 | (opnode typeinfo.RegClass:$src1, (typeinfo.LoadNode addr:$src2), |
| 739 | EFLAGS))]>; |
| 740 | |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 741 | // BinOpRI - Instructions like "add reg, reg, imm". |
| 742 | class BinOpRI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 743 | Format f, dag outlist, list<dag> pattern> |
| 744 | : ITy<opcode, f, typeinfo, outlist, |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 745 | (ins typeinfo.RegClass:$src1, typeinfo.ImmOperand:$src2), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 746 | mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM> { |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 747 | let ImmT = typeinfo.ImmEncoding; |
| 748 | } |
| 749 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 750 | // BinOpRI_R - Instructions like "add reg, reg, imm". |
| 751 | class BinOpRI_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 752 | SDNode opnode, Format f> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 753 | : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 754 | [(set typeinfo.RegClass:$dst, |
| 755 | (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>; |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 756 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 757 | // BinOpRI_F - Instructions like "cmp reg, imm". |
| 758 | class BinOpRI_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 759 | SDPatternOperator opnode, Format f> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 760 | : BinOpRI<opcode, mnemonic, typeinfo, f, (outs), |
| 761 | [(set EFLAGS, |
| 762 | (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>; |
| 763 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 764 | // BinOpRI_RF - Instructions like "add reg, reg, imm". |
| 765 | class BinOpRI_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 766 | SDNode opnode, Format f> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 767 | : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 768 | [(set typeinfo.RegClass:$dst, EFLAGS, |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 769 | (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2))]>; |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 770 | // BinOpRI_RFF - Instructions like "adc reg, reg, imm". |
| 771 | class BinOpRI_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 772 | SDNode opnode, Format f> |
| 773 | : BinOpRI<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 774 | [(set typeinfo.RegClass:$dst, EFLAGS, |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 775 | (opnode typeinfo.RegClass:$src1, typeinfo.ImmOperator:$src2, |
| 776 | EFLAGS))]>; |
| 777 | |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 778 | // BinOpRI8 - Instructions like "add reg, reg, imm8". |
| 779 | class BinOpRI8<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 780 | Format f, dag outlist, list<dag> pattern> |
| 781 | : ITy<opcode, f, typeinfo, outlist, |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 782 | (ins typeinfo.RegClass:$src1, typeinfo.Imm8Operand:$src2), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 783 | mnemonic, "{$src2, $src1|$src1, $src2}", pattern, IIC_BIN_NONMEM> { |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 784 | let ImmT = Imm8; // Always 8-bit immediate. |
Chris Lattner | 6e85be2 | 2010-10-06 05:55:42 +0000 | [diff] [blame] | 785 | } |
Chris Lattner | eadaeaa | 2010-10-06 00:30:49 +0000 | [diff] [blame] | 786 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 787 | // BinOpRI8_R - Instructions like "add reg, reg, imm8". |
| 788 | class BinOpRI8_R<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 789 | SDNode opnode, Format f> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 790 | : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 791 | [(set typeinfo.RegClass:$dst, |
| 792 | (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 793 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 794 | // BinOpRI8_F - Instructions like "cmp reg, imm8". |
| 795 | class BinOpRI8_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 796 | SDNode opnode, Format f> |
| 797 | : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs), |
| 798 | [(set EFLAGS, |
| 799 | (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>; |
Chris Lattner | 94eff91 | 2010-10-06 05:35:22 +0000 | [diff] [blame] | 800 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 801 | // BinOpRI8_RF - Instructions like "add reg, reg, imm8". |
| 802 | class BinOpRI8_RF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 803 | SDNode opnode, Format f> |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 804 | : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), |
Chris Lattner | a8c0bbb | 2010-10-07 20:14:23 +0000 | [diff] [blame] | 805 | [(set typeinfo.RegClass:$dst, EFLAGS, |
| 806 | (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2))]>; |
Chris Lattner | e17d721 | 2010-10-07 00:12:45 +0000 | [diff] [blame] | 807 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 808 | // BinOpRI8_RFF - Instructions like "adc reg, reg, imm8". |
| 809 | class BinOpRI8_RFF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 810 | SDNode opnode, Format f> |
| 811 | : BinOpRI8<opcode, mnemonic, typeinfo, f, (outs typeinfo.RegClass:$dst), |
| 812 | [(set typeinfo.RegClass:$dst, EFLAGS, |
| 813 | (opnode typeinfo.RegClass:$src1, typeinfo.Imm8Operator:$src2, |
| 814 | EFLAGS))]>; |
| 815 | |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 816 | // BinOpMR - Instructions like "add [mem], reg". |
| 817 | class BinOpMR<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 818 | list<dag> pattern> |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 819 | : ITy<opcode, MRMDestMem, typeinfo, |
| 820 | (outs), (ins typeinfo.MemOperand:$dst, typeinfo.RegClass:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 821 | mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM>; |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 822 | |
| 823 | // BinOpMR_RMW - Instructions like "add [mem], reg". |
| 824 | class BinOpMR_RMW<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 825 | SDNode opnode> |
| 826 | : BinOpMR<opcode, mnemonic, typeinfo, |
| 827 | [(store (opnode (load addr:$dst), typeinfo.RegClass:$src), addr:$dst), |
| 828 | (implicit EFLAGS)]>; |
| 829 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 830 | // BinOpMR_RMW_FF - Instructions like "adc [mem], reg". |
| 831 | class BinOpMR_RMW_FF<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 832 | SDNode opnode> |
| 833 | : BinOpMR<opcode, mnemonic, typeinfo, |
| 834 | [(store (opnode (load addr:$dst), typeinfo.RegClass:$src, EFLAGS), |
| 835 | addr:$dst), |
| 836 | (implicit EFLAGS)]>; |
| 837 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 838 | // BinOpMR_F - Instructions like "cmp [mem], reg". |
| 839 | class BinOpMR_F<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
| 840 | SDNode opnode> |
| 841 | : BinOpMR<opcode, mnemonic, typeinfo, |
| 842 | [(set EFLAGS, (opnode (load addr:$dst), typeinfo.RegClass:$src))]>; |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 843 | |
| 844 | // BinOpMI - Instructions like "add [mem], imm". |
Chris Lattner | 9fece2b | 2010-10-07 20:06:24 +0000 | [diff] [blame] | 845 | class BinOpMI<string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 846 | Format f, list<dag> pattern, bits<8> opcode = 0x80> |
| 847 | : ITy<opcode, f, typeinfo, |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 848 | (outs), (ins typeinfo.MemOperand:$dst, typeinfo.ImmOperand:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 849 | mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> { |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 850 | let ImmT = typeinfo.ImmEncoding; |
| 851 | } |
| 852 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 853 | // BinOpMI_RMW - Instructions like "add [mem], imm". |
| 854 | class BinOpMI_RMW<string mnemonic, X86TypeInfo typeinfo, |
| 855 | SDNode opnode, Format f> |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 856 | : BinOpMI<mnemonic, typeinfo, f, |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 857 | [(store (opnode (typeinfo.VT (load addr:$dst)), |
| 858 | typeinfo.ImmOperator:$src), addr:$dst), |
| 859 | (implicit EFLAGS)]>; |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 860 | // BinOpMI_RMW_FF - Instructions like "adc [mem], imm". |
| 861 | class BinOpMI_RMW_FF<string mnemonic, X86TypeInfo typeinfo, |
| 862 | SDNode opnode, Format f> |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 863 | : BinOpMI<mnemonic, typeinfo, f, |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 864 | [(store (opnode (typeinfo.VT (load addr:$dst)), |
| 865 | typeinfo.ImmOperator:$src, EFLAGS), addr:$dst), |
| 866 | (implicit EFLAGS)]>; |
| 867 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 868 | // BinOpMI_F - Instructions like "cmp [mem], imm". |
| 869 | class BinOpMI_F<string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 870 | SDPatternOperator opnode, Format f, bits<8> opcode = 0x80> |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 871 | : BinOpMI<mnemonic, typeinfo, f, |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 872 | [(set EFLAGS, (opnode (typeinfo.VT (load addr:$dst)), |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 873 | typeinfo.ImmOperator:$src))], |
| 874 | opcode>; |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 875 | |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 876 | // BinOpMI8 - Instructions like "add [mem], imm8". |
Chris Lattner | 9fece2b | 2010-10-07 20:06:24 +0000 | [diff] [blame] | 877 | class BinOpMI8<string mnemonic, X86TypeInfo typeinfo, |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 878 | Format f, list<dag> pattern> |
Chris Lattner | 9fece2b | 2010-10-07 20:06:24 +0000 | [diff] [blame] | 879 | : ITy<0x82, f, typeinfo, |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 880 | (outs), (ins typeinfo.MemOperand:$dst, typeinfo.Imm8Operand:$src), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 881 | mnemonic, "{$src, $dst|$dst, $src}", pattern, IIC_BIN_MEM> { |
Chris Lattner | 894d2e6 | 2010-10-07 00:35:28 +0000 | [diff] [blame] | 882 | let ImmT = Imm8; // Always 8-bit immediate. |
| 883 | } |
| 884 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 885 | // BinOpMI8_RMW - Instructions like "add [mem], imm8". |
| 886 | class BinOpMI8_RMW<string mnemonic, X86TypeInfo typeinfo, |
| 887 | SDNode opnode, Format f> |
| 888 | : BinOpMI8<mnemonic, typeinfo, f, |
| 889 | [(store (opnode (load addr:$dst), |
| 890 | typeinfo.Imm8Operator:$src), addr:$dst), |
| 891 | (implicit EFLAGS)]>; |
| 892 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 893 | // BinOpMI8_RMW_FF - Instructions like "adc [mem], imm8". |
| 894 | class BinOpMI8_RMW_FF<string mnemonic, X86TypeInfo typeinfo, |
| 895 | SDNode opnode, Format f> |
| 896 | : BinOpMI8<mnemonic, typeinfo, f, |
| 897 | [(store (opnode (load addr:$dst), |
| 898 | typeinfo.Imm8Operator:$src, EFLAGS), addr:$dst), |
| 899 | (implicit EFLAGS)]>; |
| 900 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 901 | // BinOpMI8_F - Instructions like "cmp [mem], imm8". |
| 902 | class BinOpMI8_F<string mnemonic, X86TypeInfo typeinfo, |
| 903 | SDNode opnode, Format f> |
| 904 | : BinOpMI8<mnemonic, typeinfo, f, |
| 905 | [(set EFLAGS, (opnode (load addr:$dst), |
| 906 | typeinfo.Imm8Operator:$src))]>; |
| 907 | |
Chris Lattner | b71a77d | 2010-10-07 00:43:39 +0000 | [diff] [blame] | 908 | // BinOpAI - Instructions like "add %eax, %eax, imm". |
| 909 | class BinOpAI<bits<8> opcode, string mnemonic, X86TypeInfo typeinfo, |
Craig Topper | 7aea69d | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 910 | Register areg, string operands> |
Chris Lattner | b71a77d | 2010-10-07 00:43:39 +0000 | [diff] [blame] | 911 | : ITy<opcode, RawFrm, typeinfo, |
| 912 | (outs), (ins typeinfo.ImmOperand:$src), |
Craig Topper | 7aea69d | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 913 | mnemonic, operands, []> { |
Chris Lattner | b71a77d | 2010-10-07 00:43:39 +0000 | [diff] [blame] | 914 | let ImmT = typeinfo.ImmEncoding; |
| 915 | let Uses = [areg]; |
| 916 | let Defs = [areg]; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 917 | let hasSideEffects = 0; |
Chris Lattner | b71a77d | 2010-10-07 00:43:39 +0000 | [diff] [blame] | 918 | } |
Chris Lattner | 94eff91 | 2010-10-06 05:35:22 +0000 | [diff] [blame] | 919 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 920 | /// ArithBinOp_RF - This is an arithmetic binary operator where the pattern is |
| 921 | /// defined with "(set GPR:$dst, EFLAGS, (...". |
| 922 | /// |
| 923 | /// It would be nice to get rid of the second and third argument here, but |
| 924 | /// tblgen can't handle dependent type references aggressively enough: PR8330 |
| 925 | multiclass ArithBinOp_RF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, |
| 926 | string mnemonic, Format RegMRM, Format MemMRM, |
| 927 | SDNode opnodeflag, SDNode opnode, |
| 928 | bit CommutableRR, bit ConvertibleToThreeAddress> { |
Chris Lattner | 26d6a04 | 2010-10-07 01:10:20 +0000 | [diff] [blame] | 929 | let Defs = [EFLAGS] in { |
| 930 | let Constraints = "$src1 = $dst" in { |
Chris Lattner | 6767751 | 2010-10-07 01:37:01 +0000 | [diff] [blame] | 931 | let isCommutable = CommutableRR, |
| 932 | isConvertibleToThreeAddress = ConvertibleToThreeAddress in { |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 933 | def #NAME#8rr : BinOpRR_RF<BaseOpc, mnemonic, Xi8 , opnodeflag>; |
| 934 | def #NAME#16rr : BinOpRR_RF<BaseOpc, mnemonic, Xi16, opnodeflag>; |
| 935 | def #NAME#32rr : BinOpRR_RF<BaseOpc, mnemonic, Xi32, opnodeflag>; |
| 936 | def #NAME#64rr : BinOpRR_RF<BaseOpc, mnemonic, Xi64, opnodeflag>; |
Chris Lattner | 26d6a04 | 2010-10-07 01:10:20 +0000 | [diff] [blame] | 937 | } // isCommutable |
| 938 | |
| 939 | def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>; |
| 940 | def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>; |
| 941 | def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>; |
| 942 | def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>; |
| 943 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 944 | def #NAME#8rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi8 , opnodeflag>; |
| 945 | def #NAME#16rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi16, opnodeflag>; |
| 946 | def #NAME#32rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi32, opnodeflag>; |
| 947 | def #NAME#64rm : BinOpRM_RF<BaseOpc2, mnemonic, Xi64, opnodeflag>; |
Chris Lattner | 26d6a04 | 2010-10-07 01:10:20 +0000 | [diff] [blame] | 948 | |
Chris Lattner | 6767751 | 2010-10-07 01:37:01 +0000 | [diff] [blame] | 949 | let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { |
Chris Lattner | 35e6ce47 | 2010-10-08 05:12:14 +0000 | [diff] [blame] | 950 | // NOTE: These are order specific, we want the ri8 forms to be listed |
| 951 | // first so that they are slightly preferred to the ri forms. |
| 952 | def #NAME#16ri8 : BinOpRI8_RF<0x82, mnemonic, Xi16, opnodeflag, RegMRM>; |
| 953 | def #NAME#32ri8 : BinOpRI8_RF<0x82, mnemonic, Xi32, opnodeflag, RegMRM>; |
| 954 | def #NAME#64ri8 : BinOpRI8_RF<0x82, mnemonic, Xi64, opnodeflag, RegMRM>; |
| 955 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 956 | def #NAME#8ri : BinOpRI_RF<0x80, mnemonic, Xi8 , opnodeflag, RegMRM>; |
| 957 | def #NAME#16ri : BinOpRI_RF<0x80, mnemonic, Xi16, opnodeflag, RegMRM>; |
| 958 | def #NAME#32ri : BinOpRI_RF<0x80, mnemonic, Xi32, opnodeflag, RegMRM>; |
| 959 | def #NAME#64ri32: BinOpRI_RF<0x80, mnemonic, Xi64, opnodeflag, RegMRM>; |
Chris Lattner | 6767751 | 2010-10-07 01:37:01 +0000 | [diff] [blame] | 960 | } |
Chris Lattner | 26d6a04 | 2010-10-07 01:10:20 +0000 | [diff] [blame] | 961 | } // Constraints = "$src1 = $dst" |
| 962 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 963 | def #NAME#8mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi8 , opnode>; |
| 964 | def #NAME#16mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi16, opnode>; |
| 965 | def #NAME#32mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi32, opnode>; |
| 966 | def #NAME#64mr : BinOpMR_RMW<BaseOpc, mnemonic, Xi64, opnode>; |
Chris Lattner | 26d6a04 | 2010-10-07 01:10:20 +0000 | [diff] [blame] | 967 | |
Chris Lattner | 35e6ce47 | 2010-10-08 05:12:14 +0000 | [diff] [blame] | 968 | // NOTE: These are order specific, we want the mi8 forms to be listed |
| 969 | // first so that they are slightly preferred to the mi forms. |
| 970 | def #NAME#16mi8 : BinOpMI8_RMW<mnemonic, Xi16, opnode, MemMRM>; |
| 971 | def #NAME#32mi8 : BinOpMI8_RMW<mnemonic, Xi32, opnode, MemMRM>; |
| 972 | def #NAME#64mi8 : BinOpMI8_RMW<mnemonic, Xi64, opnode, MemMRM>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 973 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 974 | def #NAME#8mi : BinOpMI_RMW<mnemonic, Xi8 , opnode, MemMRM>; |
| 975 | def #NAME#16mi : BinOpMI_RMW<mnemonic, Xi16, opnode, MemMRM>; |
| 976 | def #NAME#32mi : BinOpMI_RMW<mnemonic, Xi32, opnode, MemMRM>; |
| 977 | def #NAME#64mi32 : BinOpMI_RMW<mnemonic, Xi64, opnode, MemMRM>; |
Chris Lattner | 26d6a04 | 2010-10-07 01:10:20 +0000 | [diff] [blame] | 978 | |
Craig Topper | 7aea69d | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 979 | def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL, |
| 980 | "{$src, %al|AL, $src}">; |
| 981 | def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX, |
| 982 | "{$src, %ax|AX, $src}">; |
| 983 | def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX, |
| 984 | "{$src, %eax|EAX, $src}">; |
| 985 | def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX, |
| 986 | "{$src, %rax|RAX, $src}">; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 987 | } |
Chris Lattner | 26d6a04 | 2010-10-07 01:10:20 +0000 | [diff] [blame] | 988 | } |
| 989 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 990 | /// ArithBinOp_RFF - This is an arithmetic binary operator where the pattern is |
| 991 | /// defined with "(set GPR:$dst, EFLAGS, (node LHS, RHS, EFLAGS))" like ADC and |
| 992 | /// SBB. |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 993 | /// |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 994 | /// It would be nice to get rid of the second and third argument here, but |
| 995 | /// tblgen can't handle dependent type references aggressively enough: PR8330 |
| 996 | multiclass ArithBinOp_RFF<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, |
| 997 | string mnemonic, Format RegMRM, Format MemMRM, |
| 998 | SDNode opnode, bit CommutableRR, |
| 999 | bit ConvertibleToThreeAddress> { |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1000 | let Defs = [EFLAGS] in { |
| 1001 | let Constraints = "$src1 = $dst" in { |
| 1002 | let isCommutable = CommutableRR, |
| 1003 | isConvertibleToThreeAddress = ConvertibleToThreeAddress in { |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1004 | def #NAME#8rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi8 , opnode>; |
| 1005 | def #NAME#16rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi16, opnode>; |
| 1006 | def #NAME#32rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi32, opnode>; |
| 1007 | def #NAME#64rr : BinOpRR_RFF<BaseOpc, mnemonic, Xi64, opnode>; |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1008 | } // isCommutable |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 1009 | |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1010 | def #NAME#8rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi8>; |
| 1011 | def #NAME#16rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi16>; |
| 1012 | def #NAME#32rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi32>; |
| 1013 | def #NAME#64rr_REV : BinOpRR_Rev<BaseOpc2, mnemonic, Xi64>; |
| 1014 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1015 | def #NAME#8rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi8 , opnode>; |
| 1016 | def #NAME#16rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi16, opnode>; |
| 1017 | def #NAME#32rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi32, opnode>; |
| 1018 | def #NAME#64rm : BinOpRM_RFF<BaseOpc2, mnemonic, Xi64, opnode>; |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1019 | |
| 1020 | let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { |
Chris Lattner | 35e6ce47 | 2010-10-08 05:12:14 +0000 | [diff] [blame] | 1021 | // NOTE: These are order specific, we want the ri8 forms to be listed |
| 1022 | // first so that they are slightly preferred to the ri forms. |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1023 | def #NAME#16ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi16, opnode, RegMRM>; |
| 1024 | def #NAME#32ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi32, opnode, RegMRM>; |
| 1025 | def #NAME#64ri8 : BinOpRI8_RFF<0x82, mnemonic, Xi64, opnode, RegMRM>; |
Chris Lattner | 35e6ce47 | 2010-10-08 05:12:14 +0000 | [diff] [blame] | 1026 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1027 | def #NAME#8ri : BinOpRI_RFF<0x80, mnemonic, Xi8 , opnode, RegMRM>; |
| 1028 | def #NAME#16ri : BinOpRI_RFF<0x80, mnemonic, Xi16, opnode, RegMRM>; |
| 1029 | def #NAME#32ri : BinOpRI_RFF<0x80, mnemonic, Xi32, opnode, RegMRM>; |
| 1030 | def #NAME#64ri32: BinOpRI_RFF<0x80, mnemonic, Xi64, opnode, RegMRM>; |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1031 | } |
| 1032 | } // Constraints = "$src1 = $dst" |
| 1033 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1034 | def #NAME#8mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi8 , opnode>; |
| 1035 | def #NAME#16mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi16, opnode>; |
| 1036 | def #NAME#32mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi32, opnode>; |
| 1037 | def #NAME#64mr : BinOpMR_RMW_FF<BaseOpc, mnemonic, Xi64, opnode>; |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1038 | |
Chris Lattner | 35e6ce47 | 2010-10-08 05:12:14 +0000 | [diff] [blame] | 1039 | // NOTE: These are order specific, we want the mi8 forms to be listed |
| 1040 | // first so that they are slightly preferred to the mi forms. |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1041 | def #NAME#16mi8 : BinOpMI8_RMW_FF<mnemonic, Xi16, opnode, MemMRM>; |
| 1042 | def #NAME#32mi8 : BinOpMI8_RMW_FF<mnemonic, Xi32, opnode, MemMRM>; |
| 1043 | def #NAME#64mi8 : BinOpMI8_RMW_FF<mnemonic, Xi64, opnode, MemMRM>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 1044 | |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1045 | def #NAME#8mi : BinOpMI_RMW_FF<mnemonic, Xi8 , opnode, MemMRM>; |
| 1046 | def #NAME#16mi : BinOpMI_RMW_FF<mnemonic, Xi16, opnode, MemMRM>; |
| 1047 | def #NAME#32mi : BinOpMI_RMW_FF<mnemonic, Xi32, opnode, MemMRM>; |
| 1048 | def #NAME#64mi32 : BinOpMI_RMW_FF<mnemonic, Xi64, opnode, MemMRM>; |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1049 | |
Craig Topper | 7aea69d | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1050 | def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL, |
| 1051 | "{$src, %al|AL, $src}">; |
| 1052 | def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX, |
| 1053 | "{$src, %ax|AX, $src}">; |
| 1054 | def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX, |
| 1055 | "{$src, %eax|EAX, $src}">; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 1056 | def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX, |
Craig Topper | 7aea69d | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1057 | "{$src, %rax|RAX, $src}">; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 1058 | } |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 1059 | } |
| 1060 | |
| 1061 | /// ArithBinOp_F - This is an arithmetic binary operator where the pattern is |
| 1062 | /// defined with "(set EFLAGS, (...". It would be really nice to find a way |
| 1063 | /// to factor this with the other ArithBinOp_*. |
| 1064 | /// |
| 1065 | multiclass ArithBinOp_F<bits<8> BaseOpc, bits<8> BaseOpc2, bits<8> BaseOpc4, |
| 1066 | string mnemonic, Format RegMRM, Format MemMRM, |
| 1067 | SDNode opnode, |
| 1068 | bit CommutableRR, bit ConvertibleToThreeAddress> { |
| 1069 | let Defs = [EFLAGS] in { |
| 1070 | let isCommutable = CommutableRR, |
| 1071 | isConvertibleToThreeAddress = ConvertibleToThreeAddress in { |
| 1072 | def #NAME#8rr : BinOpRR_F<BaseOpc, mnemonic, Xi8 , opnode>; |
| 1073 | def #NAME#16rr : BinOpRR_F<BaseOpc, mnemonic, Xi16, opnode>; |
| 1074 | def #NAME#32rr : BinOpRR_F<BaseOpc, mnemonic, Xi32, opnode>; |
| 1075 | def #NAME#64rr : BinOpRR_F<BaseOpc, mnemonic, Xi64, opnode>; |
| 1076 | } // isCommutable |
| 1077 | |
Craig Topper | a88e356 | 2011-09-11 21:41:45 +0000 | [diff] [blame] | 1078 | def #NAME#8rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi8>; |
| 1079 | def #NAME#16rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi16>; |
| 1080 | def #NAME#32rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi32>; |
| 1081 | def #NAME#64rr_REV : BinOpRR_F_Rev<BaseOpc2, mnemonic, Xi64>; |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 1082 | |
| 1083 | def #NAME#8rm : BinOpRM_F<BaseOpc2, mnemonic, Xi8 , opnode>; |
| 1084 | def #NAME#16rm : BinOpRM_F<BaseOpc2, mnemonic, Xi16, opnode>; |
| 1085 | def #NAME#32rm : BinOpRM_F<BaseOpc2, mnemonic, Xi32, opnode>; |
| 1086 | def #NAME#64rm : BinOpRM_F<BaseOpc2, mnemonic, Xi64, opnode>; |
| 1087 | |
| 1088 | let isConvertibleToThreeAddress = ConvertibleToThreeAddress in { |
Chris Lattner | 35e6ce47 | 2010-10-08 05:12:14 +0000 | [diff] [blame] | 1089 | // NOTE: These are order specific, we want the ri8 forms to be listed |
| 1090 | // first so that they are slightly preferred to the ri forms. |
| 1091 | def #NAME#16ri8 : BinOpRI8_F<0x82, mnemonic, Xi16, opnode, RegMRM>; |
| 1092 | def #NAME#32ri8 : BinOpRI8_F<0x82, mnemonic, Xi32, opnode, RegMRM>; |
| 1093 | def #NAME#64ri8 : BinOpRI8_F<0x82, mnemonic, Xi64, opnode, RegMRM>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 1094 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 1095 | def #NAME#8ri : BinOpRI_F<0x80, mnemonic, Xi8 , opnode, RegMRM>; |
| 1096 | def #NAME#16ri : BinOpRI_F<0x80, mnemonic, Xi16, opnode, RegMRM>; |
| 1097 | def #NAME#32ri : BinOpRI_F<0x80, mnemonic, Xi32, opnode, RegMRM>; |
| 1098 | def #NAME#64ri32: BinOpRI_F<0x80, mnemonic, Xi64, opnode, RegMRM>; |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | def #NAME#8mr : BinOpMR_F<BaseOpc, mnemonic, Xi8 , opnode>; |
| 1102 | def #NAME#16mr : BinOpMR_F<BaseOpc, mnemonic, Xi16, opnode>; |
| 1103 | def #NAME#32mr : BinOpMR_F<BaseOpc, mnemonic, Xi32, opnode>; |
| 1104 | def #NAME#64mr : BinOpMR_F<BaseOpc, mnemonic, Xi64, opnode>; |
| 1105 | |
Chris Lattner | 35e6ce47 | 2010-10-08 05:12:14 +0000 | [diff] [blame] | 1106 | // NOTE: These are order specific, we want the mi8 forms to be listed |
| 1107 | // first so that they are slightly preferred to the mi forms. |
| 1108 | def #NAME#16mi8 : BinOpMI8_F<mnemonic, Xi16, opnode, MemMRM>; |
| 1109 | def #NAME#32mi8 : BinOpMI8_F<mnemonic, Xi32, opnode, MemMRM>; |
| 1110 | def #NAME#64mi8 : BinOpMI8_F<mnemonic, Xi64, opnode, MemMRM>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 1111 | |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 1112 | def #NAME#8mi : BinOpMI_F<mnemonic, Xi8 , opnode, MemMRM>; |
| 1113 | def #NAME#16mi : BinOpMI_F<mnemonic, Xi16, opnode, MemMRM>; |
| 1114 | def #NAME#32mi : BinOpMI_F<mnemonic, Xi32, opnode, MemMRM>; |
| 1115 | def #NAME#64mi32 : BinOpMI_F<mnemonic, Xi64, opnode, MemMRM>; |
| 1116 | |
Craig Topper | 7aea69d | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1117 | def #NAME#8i8 : BinOpAI<BaseOpc4, mnemonic, Xi8 , AL, |
| 1118 | "{$src, %al|AL, $src}">; |
| 1119 | def #NAME#16i16 : BinOpAI<BaseOpc4, mnemonic, Xi16, AX, |
| 1120 | "{$src, %ax|AX, $src}">; |
| 1121 | def #NAME#32i32 : BinOpAI<BaseOpc4, mnemonic, Xi32, EAX, |
| 1122 | "{$src, %eax|EAX, $src}">; |
| 1123 | def #NAME#64i32 : BinOpAI<BaseOpc4, mnemonic, Xi64, RAX, |
| 1124 | "{$src, %rax|RAX, $src}">; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 1125 | } |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1126 | } |
| 1127 | |
| 1128 | |
| 1129 | defm AND : ArithBinOp_RF<0x20, 0x22, 0x24, "and", MRM4r, MRM4m, |
| 1130 | X86and_flag, and, 1, 0>; |
| 1131 | defm OR : ArithBinOp_RF<0x08, 0x0A, 0x0C, "or", MRM1r, MRM1m, |
| 1132 | X86or_flag, or, 1, 0>; |
| 1133 | defm XOR : ArithBinOp_RF<0x30, 0x32, 0x34, "xor", MRM6r, MRM6m, |
| 1134 | X86xor_flag, xor, 1, 0>; |
| 1135 | defm ADD : ArithBinOp_RF<0x00, 0x02, 0x04, "add", MRM0r, MRM0m, |
| 1136 | X86add_flag, add, 1, 1>; |
Manman Ren | 1be131b | 2012-08-08 00:51:41 +0000 | [diff] [blame] | 1137 | let isCompare = 1 in { |
Chris Lattner | 752b60b | 2010-10-07 20:01:55 +0000 | [diff] [blame] | 1138 | defm SUB : ArithBinOp_RF<0x28, 0x2A, 0x2C, "sub", MRM5r, MRM5m, |
| 1139 | X86sub_flag, sub, 0, 0>; |
Manman Ren | 1be131b | 2012-08-08 00:51:41 +0000 | [diff] [blame] | 1140 | } |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 1141 | |
| 1142 | // Arithmetic. |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 1143 | let Uses = [EFLAGS] in { |
Chris Lattner | 846c20d | 2010-12-20 00:59:46 +0000 | [diff] [blame] | 1144 | defm ADC : ArithBinOp_RFF<0x10, 0x12, 0x14, "adc", MRM2r, MRM2m, X86adc_flag, |
| 1145 | 1, 0>; |
| 1146 | defm SBB : ArithBinOp_RFF<0x18, 0x1A, 0x1C, "sbb", MRM3r, MRM3m, X86sbb_flag, |
| 1147 | 0, 0>; |
Chris Lattner | 39c70f4 | 2010-10-05 16:39:12 +0000 | [diff] [blame] | 1148 | } |
| 1149 | |
Manman Ren | c965673 | 2012-07-06 17:36:20 +0000 | [diff] [blame] | 1150 | let isCompare = 1 in { |
Chris Lattner | ae8d67d | 2010-10-07 20:56:25 +0000 | [diff] [blame] | 1151 | defm CMP : ArithBinOp_F<0x38, 0x3A, 0x3C, "cmp", MRM7r, MRM7m, X86cmp, 0, 0>; |
Manman Ren | c965673 | 2012-07-06 17:36:20 +0000 | [diff] [blame] | 1152 | } |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 1153 | |
| 1154 | |
| 1155 | //===----------------------------------------------------------------------===// |
| 1156 | // Semantically, test instructions are similar like AND, except they don't |
| 1157 | // generate a result. From an encoding perspective, they are very different: |
| 1158 | // they don't have all the usual imm8 and REV forms, and are encoded into a |
| 1159 | // different space. |
| 1160 | def X86testpat : PatFrag<(ops node:$lhs, node:$rhs), |
| 1161 | (X86cmp (and_su node:$lhs, node:$rhs), 0)>; |
| 1162 | |
Manman Ren | d0a4ee8 | 2012-07-18 21:40:01 +0000 | [diff] [blame] | 1163 | let isCompare = 1, Defs = [EFLAGS] in { |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 1164 | let isCommutable = 1 in { |
| 1165 | def TEST8rr : BinOpRR_F<0x84, "test", Xi8 , X86testpat, MRMSrcReg>; |
| 1166 | def TEST16rr : BinOpRR_F<0x84, "test", Xi16, X86testpat, MRMSrcReg>; |
| 1167 | def TEST32rr : BinOpRR_F<0x84, "test", Xi32, X86testpat, MRMSrcReg>; |
| 1168 | def TEST64rr : BinOpRR_F<0x84, "test", Xi64, X86testpat, MRMSrcReg>; |
| 1169 | } // isCommutable |
| 1170 | |
| 1171 | def TEST8rm : BinOpRM_F<0x84, "test", Xi8 , X86testpat>; |
| 1172 | def TEST16rm : BinOpRM_F<0x84, "test", Xi16, X86testpat>; |
| 1173 | def TEST32rm : BinOpRM_F<0x84, "test", Xi32, X86testpat>; |
| 1174 | def TEST64rm : BinOpRM_F<0x84, "test", Xi64, X86testpat>; |
| 1175 | |
| 1176 | def TEST8ri : BinOpRI_F<0xF6, "test", Xi8 , X86testpat, MRM0r>; |
| 1177 | def TEST16ri : BinOpRI_F<0xF6, "test", Xi16, X86testpat, MRM0r>; |
| 1178 | def TEST32ri : BinOpRI_F<0xF6, "test", Xi32, X86testpat, MRM0r>; |
| 1179 | def TEST64ri32 : BinOpRI_F<0xF6, "test", Xi64, X86testpat, MRM0r>; |
| 1180 | |
| 1181 | def TEST8mi : BinOpMI_F<"test", Xi8 , X86testpat, MRM0m, 0xF6>; |
| 1182 | def TEST16mi : BinOpMI_F<"test", Xi16, X86testpat, MRM0m, 0xF6>; |
| 1183 | def TEST32mi : BinOpMI_F<"test", Xi32, X86testpat, MRM0m, 0xF6>; |
| 1184 | def TEST64mi32 : BinOpMI_F<"test", Xi64, X86testpat, MRM0m, 0xF6>; |
Craig Topper | af23720 | 2012-12-26 22:19:23 +0000 | [diff] [blame^] | 1185 | |
Craig Topper | 7aea69d | 2011-10-02 21:08:12 +0000 | [diff] [blame] | 1186 | def TEST8i8 : BinOpAI<0xA8, "test", Xi8 , AL, |
| 1187 | "{$src, %al|AL, $src}">; |
| 1188 | def TEST16i16 : BinOpAI<0xA8, "test", Xi16, AX, |
| 1189 | "{$src, %ax|AX, $src}">; |
| 1190 | def TEST32i32 : BinOpAI<0xA8, "test", Xi32, EAX, |
| 1191 | "{$src, %eax|EAX, $src}">; |
| 1192 | def TEST64i32 : BinOpAI<0xA8, "test", Xi64, RAX, |
| 1193 | "{$src, %rax|RAX, $src}">; |
Jakob Stoklund Olesen | 729abd3 | 2011-10-08 18:28:28 +0000 | [diff] [blame] | 1194 | |
| 1195 | // When testing the result of EXTRACT_SUBREG sub_8bit_hi, make sure the |
| 1196 | // register class is constrained to GR8_NOREX. |
| 1197 | let isPseudo = 1 in |
| 1198 | def TEST8ri_NOREX : I<0, Pseudo, (outs), (ins GR8_NOREX:$src, i8imm:$mask), |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 1199 | "", [], IIC_BIN_NONMEM>; |
Craig Topper | 965de2c | 2011-10-14 07:06:56 +0000 | [diff] [blame] | 1200 | } |
Chris Lattner | f5c60d8 | 2010-10-07 21:31:03 +0000 | [diff] [blame] | 1201 | |
Craig Topper | 965de2c | 2011-10-14 07:06:56 +0000 | [diff] [blame] | 1202 | //===----------------------------------------------------------------------===// |
| 1203 | // ANDN Instruction |
| 1204 | // |
| 1205 | multiclass bmi_andn<string mnemonic, RegisterClass RC, X86MemOperand x86memop, |
| 1206 | PatFrag ld_frag> { |
| 1207 | def rr : I<0xF2, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2), |
| 1208 | !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
Craig Topper | f3ff6ae | 2012-12-17 05:12:30 +0000 | [diff] [blame] | 1209 | [(set RC:$dst, EFLAGS, (X86and_flag (not RC:$src1), RC:$src2))], |
Andrew Trick | 8523b16 | 2012-02-01 23:20:51 +0000 | [diff] [blame] | 1210 | IIC_BIN_NONMEM>; |
Craig Topper | 965de2c | 2011-10-14 07:06:56 +0000 | [diff] [blame] | 1211 | def rm : I<0xF2, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2), |
| 1212 | !strconcat(mnemonic, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), |
| 1213 | [(set RC:$dst, EFLAGS, |
Craig Topper | f3ff6ae | 2012-12-17 05:12:30 +0000 | [diff] [blame] | 1214 | (X86and_flag (not RC:$src1), (ld_frag addr:$src2)))], IIC_BIN_MEM>; |
Craig Topper | 965de2c | 2011-10-14 07:06:56 +0000 | [diff] [blame] | 1215 | } |
| 1216 | |
| 1217 | let Predicates = [HasBMI], Defs = [EFLAGS] in { |
| 1218 | defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V; |
| 1219 | defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W; |
| 1220 | } |
Craig Topper | e94d277 | 2011-10-23 00:33:32 +0000 | [diff] [blame] | 1221 | |
Craig Topper | f3ff6ae | 2012-12-17 05:12:30 +0000 | [diff] [blame] | 1222 | let Predicates = [HasBMI] in { |
| 1223 | def : Pat<(and (not GR32:$src1), GR32:$src2), |
| 1224 | (ANDN32rr GR32:$src1, GR32:$src2)>; |
| 1225 | def : Pat<(and (not GR64:$src1), GR64:$src2), |
| 1226 | (ANDN64rr GR64:$src1, GR64:$src2)>; |
| 1227 | def : Pat<(and (not GR32:$src1), (loadi32 addr:$src2)), |
| 1228 | (ANDN32rm GR32:$src1, addr:$src2)>; |
| 1229 | def : Pat<(and (not GR64:$src1), (loadi64 addr:$src2)), |
| 1230 | (ANDN64rm GR64:$src1, addr:$src2)>; |
| 1231 | } |
| 1232 | |
Craig Topper | e94d277 | 2011-10-23 00:33:32 +0000 | [diff] [blame] | 1233 | //===----------------------------------------------------------------------===// |
| 1234 | // MULX Instruction |
| 1235 | // |
| 1236 | multiclass bmi_mulx<string mnemonic, RegisterClass RC, X86MemOperand x86memop> { |
| 1237 | let neverHasSideEffects = 1 in { |
| 1238 | let isCommutable = 1 in |
| 1239 | def rr : I<0xF6, MRMSrcReg, (outs RC:$dst1, RC:$dst2), (ins RC:$src), |
| 1240 | !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 1241 | [], IIC_MUL8>, T8XD, VEX_4V; |
Craig Topper | e94d277 | 2011-10-23 00:33:32 +0000 | [diff] [blame] | 1242 | |
| 1243 | let mayLoad = 1 in |
| 1244 | def rm : I<0xF6, MRMSrcMem, (outs RC:$dst1, RC:$dst2), (ins x86memop:$src), |
| 1245 | !strconcat(mnemonic, "\t{$src, $dst2, $dst1|$dst1, $dst2, $src}"), |
Preston Gurd | 2eec367 | 2012-04-09 15:32:22 +0000 | [diff] [blame] | 1246 | [], IIC_MUL8>, T8XD, VEX_4V; |
Craig Topper | e94d277 | 2011-10-23 00:33:32 +0000 | [diff] [blame] | 1247 | } |
| 1248 | } |
| 1249 | |
| 1250 | let Predicates = [HasBMI2] in { |
| 1251 | let Uses = [EDX] in |
| 1252 | defm MULX32 : bmi_mulx<"mulx{l}", GR32, i32mem>; |
| 1253 | let Uses = [RDX] in |
| 1254 | defm MULX64 : bmi_mulx<"mulx{q}", GR64, i64mem>, VEX_W; |
| 1255 | } |