Matt Arsenault | 5e740db | 2015-06-03 20:04:05 +0000 | [diff] [blame] | 1 | ;RUN: llc < %s -march=r600 -mcpu=redwood < %s | FileCheck %s |
Vincent Lejeune | 04d9aa4 | 2013-04-10 13:29:20 +0000 | [diff] [blame] | 2 | |
Vincent Lejeune | 04d9aa4 | 2013-04-10 13:29:20 +0000 | [diff] [blame] | 3 | ;CHECK: ALU_PUSH |
Vincent Lejeune | a4da6fb | 2013-10-01 19:32:58 +0000 | [diff] [blame] | 4 | ;CHECK: LOOP_START_DX10 @11 |
| 5 | ;CHECK: LOOP_BREAK @10 |
| 6 | ;CHECK: POP @10 |
Vincent Lejeune | 04d9aa4 | 2013-04-10 13:29:20 +0000 | [diff] [blame] | 7 | |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 8 | define amdgpu_kernel void @loop_ge(i32 addrspace(1)* nocapture %out, i32 %iterations) #0 { |
Vincent Lejeune | 04d9aa4 | 2013-04-10 13:29:20 +0000 | [diff] [blame] | 9 | entry: |
| 10 | %cmp5 = icmp sgt i32 %iterations, 0 |
| 11 | br i1 %cmp5, label %for.body, label %for.end |
| 12 | |
| 13 | for.body: ; preds = %for.body, %entry |
| 14 | %i.07.in = phi i32 [ %i.07, %for.body ], [ %iterations, %entry ] |
| 15 | %ai.06 = phi i32 [ %add, %for.body ], [ 0, %entry ] |
| 16 | %i.07 = add nsw i32 %i.07.in, -1 |
David Blaikie | 79e6c74 | 2015-02-27 19:29:02 +0000 | [diff] [blame] | 17 | %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %ai.06 |
Manman Ren | 1a5ff28 | 2013-04-30 17:52:57 +0000 | [diff] [blame] | 18 | store i32 %i.07, i32 addrspace(1)* %arrayidx, align 4 |
Vincent Lejeune | 04d9aa4 | 2013-04-10 13:29:20 +0000 | [diff] [blame] | 19 | %add = add nsw i32 %ai.06, 1 |
| 20 | %exitcond = icmp eq i32 %add, %iterations |
| 21 | br i1 %exitcond, label %for.end, label %for.body |
| 22 | |
| 23 | for.end: ; preds = %for.body, %entry |
| 24 | ret void |
| 25 | } |
| 26 | |
| 27 | attributes #0 = { nounwind "fp-contract-model"="standard" "relocation-model"="pic" "ssp-buffers-size"="8" } |
| 28 | |
| 29 | !opencl.kernels = !{!0, !1, !2, !3} |
| 30 | |
Duncan P. N. Exon Smith | be7ea19 | 2014-12-15 19:07:53 +0000 | [diff] [blame] | 31 | !0 = !{void (i32 addrspace(1)*, i32)* @loop_ge} |
| 32 | !1 = !{null} |
| 33 | !2 = !{null} |
| 34 | !3 = !{null} |