Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 1 | //===- SIMachineFunctionInfo.h - SIMachineFunctionInfo interface -*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | /// \file |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| 14 | |
| 15 | #ifndef SIMACHINEFUNCTIONINFO_H_ |
| 16 | #define SIMACHINEFUNCTIONINFO_H_ |
| 17 | |
Vincent Lejeune | ace6f73 | 2013-04-01 21:47:53 +0000 | [diff] [blame] | 18 | #include "AMDGPUMachineFunction.h" |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 19 | #include <map> |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 20 | |
| 21 | namespace llvm { |
| 22 | |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 23 | class MachineRegisterInfo; |
| 24 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 25 | /// This class keeps track of the SPI_SP_INPUT_ADDR config register, which |
| 26 | /// tells the hardware which interpolation parameters to load. |
Vincent Lejeune | ace6f73 | 2013-04-01 21:47:53 +0000 | [diff] [blame] | 27 | class SIMachineFunctionInfo : public AMDGPUMachineFunction { |
Craig Topper | 5656db4 | 2014-04-29 07:57:24 +0000 | [diff] [blame] | 28 | void anchor() override; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 29 | public: |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 30 | |
| 31 | struct SpilledReg { |
| 32 | unsigned VGPR; |
| 33 | int Lane; |
| 34 | SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } |
| 35 | SpilledReg() : VGPR(0), Lane(-1) { } |
| 36 | bool hasLane() { return Lane != -1;} |
| 37 | }; |
| 38 | |
| 39 | struct RegSpillTracker { |
| 40 | private: |
| 41 | unsigned CurrentLane; |
| 42 | std::map<unsigned, SpilledReg> SpilledRegisters; |
| 43 | public: |
| 44 | unsigned LaneVGPR; |
| 45 | RegSpillTracker() : CurrentLane(0), SpilledRegisters(), LaneVGPR(0) { } |
Tom Stellard | eba6107 | 2014-05-02 15:41:42 +0000 | [diff] [blame] | 46 | /// \p NumRegs The number of consecutive registers what need to be spilled. |
| 47 | /// This function will ensure that all registers are stored in |
| 48 | /// the same VGPR. |
| 49 | /// \returns The lane to be used for storing the first register. |
| 50 | unsigned reserveLanes(MachineRegisterInfo &MRI, MachineFunction *MF, |
| 51 | unsigned NumRegs = 1); |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 52 | void addSpilledReg(unsigned FrameIndex, unsigned Reg, int Lane = -1); |
| 53 | const SpilledReg& getSpilledReg(unsigned FrameIndex); |
| 54 | bool programSpillsRegisters() { return !SpilledRegisters.empty(); } |
| 55 | }; |
| 56 | |
| 57 | // SIMachineFunctionInfo definition |
| 58 | |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 59 | SIMachineFunctionInfo(const MachineFunction &MF); |
Christian Konig | 99ee0f4 | 2013-03-07 09:04:14 +0000 | [diff] [blame] | 60 | unsigned PSInputAddr; |
Tom Stellard | c149dc0 | 2013-11-27 21:23:35 +0000 | [diff] [blame] | 61 | struct RegSpillTracker SpillTracker; |
Tom Stellard | b02094e | 2014-07-21 15:45:01 +0000 | [diff] [blame^] | 62 | unsigned NumUserSGPRs; |
Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 63 | }; |
| 64 | |
| 65 | } // End namespace llvm |
| 66 | |
| 67 | |
| 68 | #endif //_SIMACHINEFUNCTIONINFO_H_ |