| Tim Northover | 228c943 | 2014-11-05 00:27:13 +0000 | [diff] [blame] | 1 | ; RUN: llc -mtriple=thumbv7-netbsd-eabi -o - %s | FileCheck %s |
| 2 | declare void @bar() |
| 3 | |
| 4 | ; ARM's frame lowering attempts to tack another callee-saved register onto the |
| 5 | ; list when it detects a potential misaligned VFP store. However, if there are |
| 6 | ; none available it used to just vpush anyway and misreport the location of the |
| 7 | ; registers in unwind info. Since there are benefits to aligned stores, it's |
| 8 | ; better to correct the code than the .cfi_offset directive. |
| 9 | |
| 10 | define void @test_dpr_align(i8 %l, i8 %r) { |
| 11 | ; CHECK-LABEL: test_dpr_align: |
| 12 | ; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} |
| Tim Northover | 603d316 | 2014-11-14 22:45:33 +0000 | [diff] [blame] | 13 | ; CHECK: .cfi_def_cfa_offset 36 |
| Tim Northover | 228c943 | 2014-11-05 00:27:13 +0000 | [diff] [blame] | 14 | ; CHECK: sub sp, #4 |
| Tim Northover | 603d316 | 2014-11-14 22:45:33 +0000 | [diff] [blame] | 15 | ; CHECK: .cfi_def_cfa_offset 40 |
| Tim Northover | 228c943 | 2014-11-05 00:27:13 +0000 | [diff] [blame] | 16 | ; CHECK: vpush {d8} |
| 17 | ; CHECK: .cfi_offset d8, -48 |
| 18 | ; CHECK-NOT: sub sp |
| 19 | ; [...] |
| 20 | ; CHECK: bl bar |
| 21 | ; CHECK-NOT: add sp |
| 22 | ; CHECK: vpop {d8} |
| 23 | ; CHECK: add sp, #4 |
| 24 | ; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} |
| 25 | call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"() |
| 26 | call void @bar() |
| 27 | ret void |
| 28 | } |
| 29 | |
| 30 | ; The prologue (but not the epilogue) can be made more space efficient by |
| 31 | ; chucking an argument register into the list. Not worth it in general though, |
| 32 | ; "sub sp, #4" is likely faster. |
| 33 | define void @test_dpr_align_tiny(i8 %l, i8 %r) minsize { |
| 34 | ; CHECK-LABEL: test_dpr_align_tiny: |
| 35 | ; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} |
| 36 | ; CHECK-NOT: sub sp |
| 37 | ; CHECK: vpush {d8} |
| 38 | ; CHECK: .cfi_offset d8, -48 |
| 39 | ; CHECK-NOT: sub sp |
| 40 | ; [...] |
| 41 | ; CHECK: bl bar |
| 42 | ; CHECK-NOT: add sp |
| 43 | ; CHECK: vpop {d8} |
| 44 | ; CHECK: add sp, #4 |
| 45 | ; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} |
| 46 | call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"() |
| 47 | call void @bar() |
| 48 | ret void |
| 49 | } |
| 50 | |
| 51 | |
| 52 | ; However, we shouldn't do a 2-step align/adjust if there are no DPRs to be |
| 53 | ; saved. |
| 54 | define void @test_nodpr_noalign(i8 %l, i8 %r) { |
| 55 | ; CHECK-LABEL: test_nodpr_noalign: |
| 56 | ; CHECK: push.w {r4, r5, r6, r7, r8, r9, r10, r11, lr} |
| 57 | ; CHECK-NOT: sub sp |
| 58 | ; CHECK: sub sp, #12 |
| 59 | ; CHECK-NOT: sub sp |
| 60 | ; [...] |
| 61 | ; CHECK: bl bar |
| 62 | ; CHECK-NOT: add sp |
| 63 | ; CHECK: add sp, #12 |
| 64 | ; CHECK-NOT: add sp |
| 65 | ; CHECK: pop.w {r4, r5, r6, r7, r8, r9, r10, r11, pc} |
| 66 | alloca i64 |
| 67 | call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11}"() |
| 68 | call void @bar() |
| 69 | ret void |
| 70 | } |
| Tim Northover | 9d2d218 | 2014-11-14 22:45:31 +0000 | [diff] [blame] | 71 | |
| 72 | define void @test_frame_pointer_offset() minsize "no-frame-pointer-elim"="true" { |
| 73 | ; CHECK-LABEL: test_frame_pointer_offset: |
| 74 | ; CHECK: push.w {r3, r4, r5, r6, r7, r8, r9, r10, r11, lr} |
| Tim Northover | 603d316 | 2014-11-14 22:45:33 +0000 | [diff] [blame] | 75 | ; CHECK: .cfi_def_cfa_offset 40 |
| Tim Northover | 9d2d218 | 2014-11-14 22:45:31 +0000 | [diff] [blame] | 76 | ; CHECK: add r7, sp, #16 |
| Tim Northover | 603d316 | 2014-11-14 22:45:33 +0000 | [diff] [blame] | 77 | ; CHECK: .cfi_def_cfa r7, 24 |
| 78 | ; CHECK-NOT: .cfi_def_cfa_offset |
| Tim Northover | 9d2d218 | 2014-11-14 22:45:31 +0000 | [diff] [blame] | 79 | call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{r9},~{r10},~{r11},~{d8}"() |
| 80 | call void @bar() |
| 81 | ret void |
| 82 | } |