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gerrit-public.fairphone.software / toolchain / llvm-project / b33c2ef215707b5a2d58146933d1b0ddefc185b9 / . / llvm / lib / Target / X86 / Disassembler / X86DisassemblerDecoderCommon.h
blob: a5c26d0b71167aa511a5022318b13f6eda508606 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1/*===-- X86DisassemblerDecoderCommon.h - Disassembler decoder -----*- C -*-===*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]2 *
3 * The LLVM Compiler Infrastructure
4 *
5 * This file is distributed under the University of Illinois Open Source
6 * License. See LICENSE.TXT for details.
7 *
8 *===----------------------------------------------------------------------===*
9 *
10 * This file is part of the X86 Disassembler.
11 * It contains common definitions used by both the disassembler and the table
12 * generator.
13 * Documentation for the disassembler can be found in X86Disassembler.h.
14 *
15 *===----------------------------------------------------------------------===*/
16
17/*
18 * This header file provides those definitions that need to be shared between
19 * the decoder and the table generator in a C-friendly manner.
20 */
21
22#ifndef X86DISASSEMBLERDECODERCOMMON_H
23#define X86DISASSEMBLERDECODERCOMMON_H
24
Michael J. Spencer447762d2010-11-29 18:16:10 +0000[diff] [blame]25#include "llvm/Support/DataTypes.h"
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]26
27#define INSTRUCTIONS_SYM x86DisassemblerInstrSpecifiers
28#define CONTEXTS_SYM x86DisassemblerContexts
29#define ONEBYTE_SYM x86DisassemblerOneByteOpcodes
30#define TWOBYTE_SYM x86DisassemblerTwoByteOpcodes
31#define THREEBYTE38_SYM x86DisassemblerThreeByte38Opcodes
32#define THREEBYTE3A_SYM x86DisassemblerThreeByte3AOpcodes
Joerg Sonnenbergerfc4789d2011-04-04 16:58:13 +0000[diff] [blame]33#define THREEBYTEA6_SYM x86DisassemblerThreeByteA6Opcodes
34#define THREEBYTEA7_SYM x86DisassemblerThreeByteA7Opcodes
Craig Topper9e3e38a2013-10-03 05:17:48 +0000[diff] [blame]35#define XOP8_MAP_SYM x86DisassemblerXOP8Opcodes
36#define XOP9_MAP_SYM x86DisassemblerXOP9Opcodes
37#define XOPA_MAP_SYM x86DisassemblerXOPAOpcodes
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]38
39#define INSTRUCTIONS_STR "x86DisassemblerInstrSpecifiers"
40#define CONTEXTS_STR "x86DisassemblerContexts"
41#define ONEBYTE_STR "x86DisassemblerOneByteOpcodes"
42#define TWOBYTE_STR "x86DisassemblerTwoByteOpcodes"
43#define THREEBYTE38_STR "x86DisassemblerThreeByte38Opcodes"
44#define THREEBYTE3A_STR "x86DisassemblerThreeByte3AOpcodes"
Joerg Sonnenbergerfc4789d2011-04-04 16:58:13 +0000[diff] [blame]45#define THREEBYTEA6_STR "x86DisassemblerThreeByteA6Opcodes"
46#define THREEBYTEA7_STR "x86DisassemblerThreeByteA7Opcodes"
Craig Topper9e3e38a2013-10-03 05:17:48 +0000[diff] [blame]47#define XOP8_MAP_STR "x86DisassemblerXOP8Opcodes"
48#define XOP9_MAP_STR "x86DisassemblerXOP9Opcodes"
49#define XOPA_MAP_STR "x86DisassemblerXOPAOpcodes"
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]50
51/*
52 * Attributes of an instruction that must be known before the opcode can be
53 * processed correctly. Most of these indicate the presence of particular
54 * prefixes, but ATTR_64BIT is simply an attribute of the decoding context.
55 */
Elena Demikhovsky371e3632013-12-25 11:40:51 +0000[diff] [blame]56#define ATTRIBUTE_BITS \
57 ENUM_ENTRY(ATTR_NONE, 0x00) \
58 ENUM_ENTRY(ATTR_64BIT, (0x1 << 0)) \
59 ENUM_ENTRY(ATTR_XS, (0x1 << 1)) \
60 ENUM_ENTRY(ATTR_XD, (0x1 << 2)) \
61 ENUM_ENTRY(ATTR_REXW, (0x1 << 3)) \
62 ENUM_ENTRY(ATTR_OPSIZE, (0x1 << 4)) \
63 ENUM_ENTRY(ATTR_ADSIZE, (0x1 << 5)) \
64 ENUM_ENTRY(ATTR_VEX, (0x1 << 6)) \
65 ENUM_ENTRY(ATTR_VEXL, (0x1 << 7)) \
66 ENUM_ENTRY(ATTR_EVEX, (0x1 << 8)) \
67 ENUM_ENTRY(ATTR_EVEXL, (0x1 << 9)) \
68 ENUM_ENTRY(ATTR_EVEXL2, (0x1 << 10)) \
69 ENUM_ENTRY(ATTR_EVEXK, (0x1 << 11)) \
70 ENUM_ENTRY(ATTR_EVEXKZ, (0x1 << 12)) \
71 ENUM_ENTRY(ATTR_EVEXB, (0x1 << 13))
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]72
73#define ENUM_ENTRY(n, v) n = v,
74enum attributeBits {
75 ATTRIBUTE_BITS
76 ATTR_max
77};
78#undef ENUM_ENTRY
79
80/*
81 * Combinations of the above attributes that are relevant to instruction
Elena Demikhovsky371e3632013-12-25 11:40:51 +0000[diff] [blame]82 * decode. Although other combinations are possible, they can be reduced to
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]83 * these without affecting the ultimately decoded instruction.
84 */
85
86/* Class name Rank Rationale for rank assignment */
87#define INSTRUCTION_CONTEXTS \
88 ENUM_ENTRY(IC, 0, "says nothing about the instruction") \
89 ENUM_ENTRY(IC_64BIT, 1, "says the instruction applies in " \
90 "64-bit mode but no more") \
91 ENUM_ENTRY(IC_OPSIZE, 3, "requires an OPSIZE prefix, so " \
92 "operands change width") \
Craig Topper6491c802012-02-27 01:54:29 +0000[diff] [blame]93 ENUM_ENTRY(IC_ADSIZE, 3, "requires an ADSIZE prefix, so " \
94 "operands change width") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]95 ENUM_ENTRY(IC_XD, 2, "may say something about the opcode " \
96 "but not the operands") \
97 ENUM_ENTRY(IC_XS, 2, "may say something about the opcode " \
98 "but not the operands") \
Craig Topper88cb33e2011-10-01 19:54:56 +0000[diff] [blame]99 ENUM_ENTRY(IC_XD_OPSIZE, 3, "requires an OPSIZE prefix, so " \
100 "operands change width") \
Craig Toppera6978522011-10-11 04:34:23 +0000[diff] [blame]101 ENUM_ENTRY(IC_XS_OPSIZE, 3, "requires an OPSIZE prefix, so " \
102 "operands change width") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]103 ENUM_ENTRY(IC_64BIT_REXW, 4, "requires a REX.W prefix, so operands "\
104 "change width; overrides IC_OPSIZE") \
105 ENUM_ENTRY(IC_64BIT_OPSIZE, 3, "Just as meaningful as IC_OPSIZE") \
Craig Topper6491c802012-02-27 01:54:29 +0000[diff] [blame]106 ENUM_ENTRY(IC_64BIT_ADSIZE, 3, "Just as meaningful as IC_ADSIZE") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]107 ENUM_ENTRY(IC_64BIT_XD, 5, "XD instructions are SSE; REX.W is " \
108 "secondary") \
109 ENUM_ENTRY(IC_64BIT_XS, 5, "Just as meaningful as IC_64BIT_XD") \
Craig Topper88cb33e2011-10-01 19:54:56 +0000[diff] [blame]110 ENUM_ENTRY(IC_64BIT_XD_OPSIZE, 3, "Just as meaningful as IC_XD_OPSIZE") \
Craig Toppera6978522011-10-11 04:34:23 +0000[diff] [blame]111 ENUM_ENTRY(IC_64BIT_XS_OPSIZE, 3, "Just as meaningful as IC_XS_OPSIZE") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]112 ENUM_ENTRY(IC_64BIT_REXW_XS, 6, "OPSIZE could mean a different " \
113 "opcode") \
114 ENUM_ENTRY(IC_64BIT_REXW_XD, 6, "Just as meaningful as " \
115 "IC_64BIT_REXW_XS") \
116 ENUM_ENTRY(IC_64BIT_REXW_OPSIZE, 7, "The Dynamic Duo! Prefer over all " \
117 "else because this changes most " \
Sean Callananc3fd5232011-03-15 01:23:15 +0000[diff] [blame]118 "operands' meaning") \
119 ENUM_ENTRY(IC_VEX, 1, "requires a VEX prefix") \
120 ENUM_ENTRY(IC_VEX_XS, 2, "requires VEX and the XS prefix") \
121 ENUM_ENTRY(IC_VEX_XD, 2, "requires VEX and the XD prefix") \
122 ENUM_ENTRY(IC_VEX_OPSIZE, 2, "requires VEX and the OpSize prefix") \
123 ENUM_ENTRY(IC_VEX_W, 3, "requires VEX and the W prefix") \
124 ENUM_ENTRY(IC_VEX_W_XS, 4, "requires VEX, W, and XS prefix") \
125 ENUM_ENTRY(IC_VEX_W_XD, 4, "requires VEX, W, and XD prefix") \
126 ENUM_ENTRY(IC_VEX_W_OPSIZE, 4, "requires VEX, W, and OpSize") \
127 ENUM_ENTRY(IC_VEX_L, 3, "requires VEX and the L prefix") \
128 ENUM_ENTRY(IC_VEX_L_XS, 4, "requires VEX and the L and XS prefix")\
Craig Topperf18c8962011-10-04 06:30:42 +0000[diff] [blame]129 ENUM_ENTRY(IC_VEX_L_XD, 4, "requires VEX and the L and XD prefix")\
Craig Topperf01f1b52011-11-06 23:04:08 +0000[diff] [blame]130 ENUM_ENTRY(IC_VEX_L_OPSIZE, 4, "requires VEX, L, and OpSize") \
Craig Toppered59dd32013-09-30 02:46:36 +0000[diff] [blame]131 ENUM_ENTRY(IC_VEX_L_W, 4, "requires VEX, L and W") \
132 ENUM_ENTRY(IC_VEX_L_W_XS, 5, "requires VEX, L, W and XS prefix") \
133 ENUM_ENTRY(IC_VEX_L_W_XD, 5, "requires VEX, L, W and XD prefix") \
134 ENUM_ENTRY(IC_VEX_L_W_OPSIZE, 5, "requires VEX, L, W and OpSize") \
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]135 ENUM_ENTRY(IC_EVEX, 1, "requires an EVEX prefix") \
136 ENUM_ENTRY(IC_EVEX_XS, 2, "requires EVEX and the XS prefix") \
137 ENUM_ENTRY(IC_EVEX_XD, 2, "requires EVEX and the XD prefix") \
138 ENUM_ENTRY(IC_EVEX_OPSIZE, 2, "requires EVEX and the OpSize prefix") \
139 ENUM_ENTRY(IC_EVEX_W, 3, "requires EVEX and the W prefix") \
140 ENUM_ENTRY(IC_EVEX_W_XS, 4, "requires EVEX, W, and XS prefix") \
141 ENUM_ENTRY(IC_EVEX_W_XD, 4, "requires EVEX, W, and XD prefix") \
142 ENUM_ENTRY(IC_EVEX_W_OPSIZE, 4, "requires EVEX, W, and OpSize") \
143 ENUM_ENTRY(IC_EVEX_L, 3, "requires EVEX and the L prefix") \
144 ENUM_ENTRY(IC_EVEX_L_XS, 4, "requires EVEX and the L and XS prefix")\
145 ENUM_ENTRY(IC_EVEX_L_XD, 4, "requires EVEX and the L and XD prefix")\
146 ENUM_ENTRY(IC_EVEX_L_OPSIZE, 4, "requires EVEX, L, and OpSize") \
147 ENUM_ENTRY(IC_EVEX_L_W, 3, "requires EVEX, L and W") \
148 ENUM_ENTRY(IC_EVEX_L_W_XS, 4, "requires EVEX, L, W and XS prefix") \
149 ENUM_ENTRY(IC_EVEX_L_W_XD, 4, "requires EVEX, L, W and XD prefix") \
150 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE, 4, "requires EVEX, L, W and OpSize") \
151 ENUM_ENTRY(IC_EVEX_L2, 3, "requires EVEX and the L2 prefix") \
152 ENUM_ENTRY(IC_EVEX_L2_XS, 4, "requires EVEX and the L2 and XS prefix")\
153 ENUM_ENTRY(IC_EVEX_L2_XD, 4, "requires EVEX and the L2 and XD prefix")\
154 ENUM_ENTRY(IC_EVEX_L2_OPSIZE, 4, "requires EVEX, L2, and OpSize") \
155 ENUM_ENTRY(IC_EVEX_L2_W, 3, "requires EVEX, L2 and W") \
156 ENUM_ENTRY(IC_EVEX_L2_W_XS, 4, "requires EVEX, L2, W and XS prefix") \
157 ENUM_ENTRY(IC_EVEX_L2_W_XD, 4, "requires EVEX, L2, W and XD prefix") \
158 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE, 4, "requires EVEX, L2, W and OpSize") \
159 ENUM_ENTRY(IC_EVEX_K, 1, "requires an EVEX_K prefix") \
160 ENUM_ENTRY(IC_EVEX_XS_K, 2, "requires EVEX_K and the XS prefix") \
161 ENUM_ENTRY(IC_EVEX_XD_K, 2, "requires EVEX_K and the XD prefix") \
162 ENUM_ENTRY(IC_EVEX_OPSIZE_K, 2, "requires EVEX_K and the OpSize prefix") \
163 ENUM_ENTRY(IC_EVEX_W_K, 3, "requires EVEX_K and the W prefix") \
164 ENUM_ENTRY(IC_EVEX_W_XS_K, 4, "requires EVEX_K, W, and XS prefix") \
165 ENUM_ENTRY(IC_EVEX_W_XD_K, 4, "requires EVEX_K, W, and XD prefix") \
166 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K, 4, "requires EVEX_K, W, and OpSize") \
167 ENUM_ENTRY(IC_EVEX_L_K, 3, "requires EVEX_K and the L prefix") \
168 ENUM_ENTRY(IC_EVEX_L_XS_K, 4, "requires EVEX_K and the L and XS prefix")\
169 ENUM_ENTRY(IC_EVEX_L_XD_K, 4, "requires EVEX_K and the L and XD prefix")\
170 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K, 4, "requires EVEX_K, L, and OpSize") \
171 ENUM_ENTRY(IC_EVEX_L_W_K, 3, "requires EVEX_K, L and W") \
172 ENUM_ENTRY(IC_EVEX_L_W_XS_K, 4, "requires EVEX_K, L, W and XS prefix") \
173 ENUM_ENTRY(IC_EVEX_L_W_XD_K, 4, "requires EVEX_K, L, W and XD prefix") \
174 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K, 4, "requires EVEX_K, L, W and OpSize") \
175 ENUM_ENTRY(IC_EVEX_L2_K, 3, "requires EVEX_K and the L2 prefix") \
176 ENUM_ENTRY(IC_EVEX_L2_XS_K, 4, "requires EVEX_K and the L2 and XS prefix")\
177 ENUM_ENTRY(IC_EVEX_L2_XD_K, 4, "requires EVEX_K and the L2 and XD prefix")\
178 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K, 4, "requires EVEX_K, L2, and OpSize") \
179 ENUM_ENTRY(IC_EVEX_L2_W_K, 3, "requires EVEX_K, L2 and W") \
180 ENUM_ENTRY(IC_EVEX_L2_W_XS_K, 4, "requires EVEX_K, L2, W and XS prefix") \
181 ENUM_ENTRY(IC_EVEX_L2_W_XD_K, 4, "requires EVEX_K, L2, W and XD prefix") \
182 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K, 4, "requires EVEX_K, L2, W and OpSize") \
183 ENUM_ENTRY(IC_EVEX_B, 1, "requires an EVEX_B prefix") \
184 ENUM_ENTRY(IC_EVEX_XS_B, 2, "requires EVEX_B and the XS prefix") \
185 ENUM_ENTRY(IC_EVEX_XD_B, 2, "requires EVEX_B and the XD prefix") \
186 ENUM_ENTRY(IC_EVEX_OPSIZE_B, 2, "requires EVEX_B and the OpSize prefix") \
187 ENUM_ENTRY(IC_EVEX_W_B, 3, "requires EVEX_B and the W prefix") \
188 ENUM_ENTRY(IC_EVEX_W_XS_B, 4, "requires EVEX_B, W, and XS prefix") \
189 ENUM_ENTRY(IC_EVEX_W_XD_B, 4, "requires EVEX_B, W, and XD prefix") \
190 ENUM_ENTRY(IC_EVEX_W_OPSIZE_B, 4, "requires EVEX_B, W, and OpSize") \
191 ENUM_ENTRY(IC_EVEX_L_B, 3, "requires EVEX_B and the L prefix") \
192 ENUM_ENTRY(IC_EVEX_L_XS_B, 4, "requires EVEX_B and the L and XS prefix")\
193 ENUM_ENTRY(IC_EVEX_L_XD_B, 4, "requires EVEX_B and the L and XD prefix")\
194 ENUM_ENTRY(IC_EVEX_L_OPSIZE_B, 4, "requires EVEX_B, L, and OpSize") \
195 ENUM_ENTRY(IC_EVEX_L_W_B, 3, "requires EVEX_B, L and W") \
196 ENUM_ENTRY(IC_EVEX_L_W_XS_B, 4, "requires EVEX_B, L, W and XS prefix") \
197 ENUM_ENTRY(IC_EVEX_L_W_XD_B, 4, "requires EVEX_B, L, W and XD prefix") \
198 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_B, 4, "requires EVEX_B, L, W and OpSize") \
199 ENUM_ENTRY(IC_EVEX_L2_B, 3, "requires EVEX_B and the L2 prefix") \
200 ENUM_ENTRY(IC_EVEX_L2_XS_B, 4, "requires EVEX_B and the L2 and XS prefix")\
201 ENUM_ENTRY(IC_EVEX_L2_XD_B, 4, "requires EVEX_B and the L2 and XD prefix")\
202 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_B, 4, "requires EVEX_B, L2, and OpSize") \
203 ENUM_ENTRY(IC_EVEX_L2_W_B, 3, "requires EVEX_B, L2 and W") \
204 ENUM_ENTRY(IC_EVEX_L2_W_XS_B, 4, "requires EVEX_B, L2, W and XS prefix") \
205 ENUM_ENTRY(IC_EVEX_L2_W_XD_B, 4, "requires EVEX_B, L2, W and XD prefix") \
206 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_B, 4, "requires EVEX_B, L2, W and OpSize") \
Elena Demikhovsky371e3632013-12-25 11:40:51 +0000[diff] [blame]207 ENUM_ENTRY(IC_EVEX_K_B, 1, "requires EVEX_B and EVEX_K prefix") \
208 ENUM_ENTRY(IC_EVEX_XS_K_B, 2, "requires EVEX_B, EVEX_K and the XS prefix") \
209 ENUM_ENTRY(IC_EVEX_XD_K_B, 2, "requires EVEX_B, EVEX_K and the XD prefix") \
210 ENUM_ENTRY(IC_EVEX_OPSIZE_K_B, 2, "requires EVEX_B, EVEX_K and the OpSize prefix") \
211 ENUM_ENTRY(IC_EVEX_W_K_B, 3, "requires EVEX_B, EVEX_K and the W prefix") \
212 ENUM_ENTRY(IC_EVEX_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, W, and XS prefix") \
213 ENUM_ENTRY(IC_EVEX_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, W, and XD prefix") \
214 ENUM_ENTRY(IC_EVEX_W_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, W, and OpSize") \
215 ENUM_ENTRY(IC_EVEX_L_K_B, 3, "requires EVEX_B, EVEX_K and the L prefix") \
216 ENUM_ENTRY(IC_EVEX_L_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L and XS prefix")\
217 ENUM_ENTRY(IC_EVEX_L_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L and XD prefix")\
218 ENUM_ENTRY(IC_EVEX_L_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L, and OpSize") \
219 ENUM_ENTRY(IC_EVEX_L_W_K_B, 3, "requires EVEX_B, EVEX_K, L and W") \
220 ENUM_ENTRY(IC_EVEX_L_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XS prefix") \
221 ENUM_ENTRY(IC_EVEX_L_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L, W and XD prefix") \
222 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L, W and OpSize") \
223 ENUM_ENTRY(IC_EVEX_L2_K_B, 3, "requires EVEX_B, EVEX_K and the L2 prefix") \
224 ENUM_ENTRY(IC_EVEX_L2_XS_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XS prefix")\
225 ENUM_ENTRY(IC_EVEX_L2_XD_K_B, 4, "requires EVEX_B, EVEX_K and the L2 and XD prefix")\
226 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_K_B, 4, "requires EVEX_B, EVEX_K, L2, and OpSize") \
227 ENUM_ENTRY(IC_EVEX_L2_W_K_B, 3, "requires EVEX_B, EVEX_K, L2 and W") \
228 ENUM_ENTRY(IC_EVEX_L2_W_XS_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XS prefix") \
229 ENUM_ENTRY(IC_EVEX_L2_W_XD_K_B, 4, "requires EVEX_B, EVEX_K, L2, W and XD prefix") \
230 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_K_B,4, "requires EVEX_B, EVEX_K, L2, W and OpSize") \
231 ENUM_ENTRY(IC_EVEX_KZ_B, 1, "requires EVEX_B and EVEX_KZ prefix") \
232 ENUM_ENTRY(IC_EVEX_XS_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XS prefix") \
233 ENUM_ENTRY(IC_EVEX_XD_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the XD prefix") \
234 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ_B, 2, "requires EVEX_B, EVEX_KZ and the OpSize prefix") \
235 ENUM_ENTRY(IC_EVEX_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the W prefix") \
236 ENUM_ENTRY(IC_EVEX_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XS prefix") \
237 ENUM_ENTRY(IC_EVEX_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and XD prefix") \
238 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, W, and OpSize") \
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]239 ENUM_ENTRY(IC_EVEX_L_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L prefix") \
240 ENUM_ENTRY(IC_EVEX_L_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XS prefix")\
241 ENUM_ENTRY(IC_EVEX_L_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L and XD prefix")\
242 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, and OpSize") \
243 ENUM_ENTRY(IC_EVEX_L_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L and W") \
244 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XS prefix") \
245 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and XD prefix") \
246 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L, W and OpSize") \
247 ENUM_ENTRY(IC_EVEX_L2_KZ_B, 3, "requires EVEX_B, EVEX_KZ and the L2 prefix") \
248 ENUM_ENTRY(IC_EVEX_L2_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XS prefix")\
249 ENUM_ENTRY(IC_EVEX_L2_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ and the L2 and XD prefix")\
250 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, and OpSize") \
251 ENUM_ENTRY(IC_EVEX_L2_W_KZ_B, 3, "requires EVEX_B, EVEX_KZ, L2 and W") \
252 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XS prefix") \
253 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and XD prefix") \
254 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ_B, 4, "requires EVEX_B, EVEX_KZ, L2, W and OpSize") \
255 ENUM_ENTRY(IC_EVEX_KZ, 1, "requires an EVEX_KZ prefix") \
256 ENUM_ENTRY(IC_EVEX_XS_KZ, 2, "requires EVEX_KZ and the XS prefix") \
257 ENUM_ENTRY(IC_EVEX_XD_KZ, 2, "requires EVEX_KZ and the XD prefix") \
258 ENUM_ENTRY(IC_EVEX_OPSIZE_KZ, 2, "requires EVEX_KZ and the OpSize prefix") \
259 ENUM_ENTRY(IC_EVEX_W_KZ, 3, "requires EVEX_KZ and the W prefix") \
260 ENUM_ENTRY(IC_EVEX_W_XS_KZ, 4, "requires EVEX_KZ, W, and XS prefix") \
261 ENUM_ENTRY(IC_EVEX_W_XD_KZ, 4, "requires EVEX_KZ, W, and XD prefix") \
262 ENUM_ENTRY(IC_EVEX_W_OPSIZE_KZ, 4, "requires EVEX_KZ, W, and OpSize") \
263 ENUM_ENTRY(IC_EVEX_L_KZ, 3, "requires EVEX_KZ and the L prefix") \
264 ENUM_ENTRY(IC_EVEX_L_XS_KZ, 4, "requires EVEX_KZ and the L and XS prefix")\
265 ENUM_ENTRY(IC_EVEX_L_XD_KZ, 4, "requires EVEX_KZ and the L and XD prefix")\
266 ENUM_ENTRY(IC_EVEX_L_OPSIZE_KZ, 4, "requires EVEX_KZ, L, and OpSize") \
267 ENUM_ENTRY(IC_EVEX_L_W_KZ, 3, "requires EVEX_KZ, L and W") \
268 ENUM_ENTRY(IC_EVEX_L_W_XS_KZ, 4, "requires EVEX_KZ, L, W and XS prefix") \
269 ENUM_ENTRY(IC_EVEX_L_W_XD_KZ, 4, "requires EVEX_KZ, L, W and XD prefix") \
270 ENUM_ENTRY(IC_EVEX_L_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L, W and OpSize") \
271 ENUM_ENTRY(IC_EVEX_L2_KZ, 3, "requires EVEX_KZ and the L2 prefix") \
272 ENUM_ENTRY(IC_EVEX_L2_XS_KZ, 4, "requires EVEX_KZ and the L2 and XS prefix")\
273 ENUM_ENTRY(IC_EVEX_L2_XD_KZ, 4, "requires EVEX_KZ and the L2 and XD prefix")\
274 ENUM_ENTRY(IC_EVEX_L2_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, and OpSize") \
275 ENUM_ENTRY(IC_EVEX_L2_W_KZ, 3, "requires EVEX_KZ, L2 and W") \
276 ENUM_ENTRY(IC_EVEX_L2_W_XS_KZ, 4, "requires EVEX_KZ, L2, W and XS prefix") \
277 ENUM_ENTRY(IC_EVEX_L2_W_XD_KZ, 4, "requires EVEX_KZ, L2, W and XD prefix") \
278 ENUM_ENTRY(IC_EVEX_L2_W_OPSIZE_KZ, 4, "requires EVEX_KZ, L2, W and OpSize")
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]279
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]280#define ENUM_ENTRY(n, r, d) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]281typedef enum {
282 INSTRUCTION_CONTEXTS
283 IC_max
284} InstructionContext;
285#undef ENUM_ENTRY
286
287/*
288 * Opcode types, which determine which decode table to use, both in the Intel
289 * manual and also for the decoder.
290 */
291typedef enum {
292 ONEBYTE = 0,
293 TWOBYTE = 1,
294 THREEBYTE_38 = 2,
Joerg Sonnenbergerfc4789d2011-04-04 16:58:13 +0000[diff] [blame]295 THREEBYTE_3A = 3,
296 THREEBYTE_A6 = 4,
Craig Topper9e3e38a2013-10-03 05:17:48 +0000[diff] [blame]297 THREEBYTE_A7 = 5,
298 XOP8_MAP = 6,
299 XOP9_MAP = 7,
300 XOPA_MAP = 8
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]301} OpcodeType;
302
303/*
304 * The following structs are used for the hierarchical decode table. After
305 * determining the instruction's class (i.e., which IC_* constant applies to
306 * it), the decoder reads the opcode. Some instructions require specific
307 * values of the ModR/M byte, so the ModR/M byte indexes into the final table.
308 *
309 * If a ModR/M byte is not required, "required" is left unset, and the values
310 * for each instructionID are identical.
311 */
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]312
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]313typedef uint16_t InstrUID;
314
315/*
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]316 * ModRMDecisionType - describes the type of ModR/M decision, allowing the
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]317 * consumer to determine the number of entries in it.
318 *
319 * MODRM_ONEENTRY - No matter what the value of the ModR/M byte is, the decoded
320 * instruction is the same.
321 * MODRM_SPLITRM - If the ModR/M byte is between 0x00 and 0xbf, the opcode
322 * corresponds to one instruction; otherwise, it corresponds to
323 * a different instruction.
Craig Topper963305b2012-09-13 05:45:42 +0000[diff] [blame]324 * MODRM_SPLITMISC- If the ModR/M byte is between 0x00 and 0xbf, ModR/M byte
325 * divided by 8 is used to select instruction; otherwise, each
326 * value of the ModR/M byte could correspond to a different
327 * instruction.
Craig Toppera0cd9702012-02-09 08:58:07 +0000[diff] [blame]328 * MODRM_SPLITREG - ModR/M byte divided by 8 is used to select instruction. This
329 corresponds to instructions that use reg field as opcode
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]330 * MODRM_FULL - Potentially, each value of the ModR/M byte could correspond
331 * to a different instruction.
332 */
333
334#define MODRMTYPES \
335 ENUM_ENTRY(MODRM_ONEENTRY) \
336 ENUM_ENTRY(MODRM_SPLITRM) \
Craig Topper963305b2012-09-13 05:45:42 +0000[diff] [blame]337 ENUM_ENTRY(MODRM_SPLITMISC) \
Craig Toppera0cd9702012-02-09 08:58:07 +0000[diff] [blame]338 ENUM_ENTRY(MODRM_SPLITREG) \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]339 ENUM_ENTRY(MODRM_FULL)
340
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]341#define ENUM_ENTRY(n) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]342typedef enum {
343 MODRMTYPES
344 MODRM_max
345} ModRMDecisionType;
346#undef ENUM_ENTRY
347
348/*
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]349 * ModRMDecision - Specifies whether a ModR/M byte is needed and (if so) which
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]350 * instruction each possible value of the ModR/M byte corresponds to. Once
351 * this information is known, we have narrowed down to a single instruction.
352 */
353struct ModRMDecision {
354 uint8_t modrm_type;
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]355
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]356 /* The macro below must be defined wherever this file is included. */
357 INSTRUCTION_IDS
358};
359
360/*
361 * OpcodeDecision - Specifies which set of ModR/M->instruction tables to look at
362 * given a particular opcode.
363 */
364struct OpcodeDecision {
365 struct ModRMDecision modRMDecisions[256];
366};
367
368/*
369 * ContextDecision - Specifies which opcode->instruction tables to look at given
370 * a particular context (set of attributes). Since there are many possible
371 * contexts, the decoder first uses CONTEXTS_SYM to determine which context
372 * applies given a specific set of attributes. Hence there are only IC_max
373 * entries in this table, rather than 2^(ATTR_max).
374 */
375struct ContextDecision {
376 struct OpcodeDecision opcodeDecisions[IC_max];
377};
378
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]379/*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]380 * Physical encodings of instruction operands.
381 */
382
383#define ENCODINGS \
384 ENUM_ENTRY(ENCODING_NONE, "") \
385 ENUM_ENTRY(ENCODING_REG, "Register operand in ModR/M byte.") \
386 ENUM_ENTRY(ENCODING_RM, "R/M operand in ModR/M byte.") \
Sean Callananc3fd5232011-03-15 01:23:15 +0000[diff] [blame]387 ENUM_ENTRY(ENCODING_VVVV, "Register operand in VEX.vvvv byte.") \
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]388 ENUM_ENTRY(ENCODING_WRITEMASK, "Register operand in EVEX.aaa byte.") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]389 ENUM_ENTRY(ENCODING_CB, "1-byte code offset (possible new CS value)") \
390 ENUM_ENTRY(ENCODING_CW, "2-byte") \
391 ENUM_ENTRY(ENCODING_CD, "4-byte") \
392 ENUM_ENTRY(ENCODING_CP, "6-byte") \
393 ENUM_ENTRY(ENCODING_CO, "8-byte") \
394 ENUM_ENTRY(ENCODING_CT, "10-byte") \
395 ENUM_ENTRY(ENCODING_IB, "1-byte immediate") \
396 ENUM_ENTRY(ENCODING_IW, "2-byte") \
397 ENUM_ENTRY(ENCODING_ID, "4-byte") \
398 ENUM_ENTRY(ENCODING_IO, "8-byte") \
399 ENUM_ENTRY(ENCODING_RB, "(AL..DIL, R8L..R15L) Register code added to " \
400 "the opcode byte") \
401 ENUM_ENTRY(ENCODING_RW, "(AX..DI, R8W..R15W)") \
402 ENUM_ENTRY(ENCODING_RD, "(EAX..EDI, R8D..R15D)") \
403 ENUM_ENTRY(ENCODING_RO, "(RAX..RDI, R8..R15)") \
Craig Topper623b0d62014-01-01 14:22:37 +0000[diff] [blame]404 ENUM_ENTRY(ENCODING_FP, "Position on floating-point stack in ModR/M " \
405 "byte.") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]406 \
407 ENUM_ENTRY(ENCODING_Iv, "Immediate of operand size") \
408 ENUM_ENTRY(ENCODING_Ia, "Immediate of address size") \
409 ENUM_ENTRY(ENCODING_Rv, "Register code of operand size added to the " \
410 "opcode byte") \
411 ENUM_ENTRY(ENCODING_DUP, "Duplicate of another operand; ID is encoded " \
David Woodhouse2ef8d9c2014-01-22 15:08:08 +0000[diff] [blame]412 "in type") \
David Woodhouseb33c2ef2014-01-22 15:08:21 +0000[diff] [blame^]413 ENUM_ENTRY(ENCODING_SI, "Source index; encoded in OpSize/Adsize prefix") \
414 ENUM_ENTRY(ENCODING_DI, "Destination index; encoded in prefixes")
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]415
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]416#define ENUM_ENTRY(n, d) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]417 typedef enum {
418 ENCODINGS
419 ENCODING_max
420 } OperandEncoding;
421#undef ENUM_ENTRY
422
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]423/*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]424 * Semantic interpretations of instruction operands.
425 */
426
427#define TYPES \
428 ENUM_ENTRY(TYPE_NONE, "") \
429 ENUM_ENTRY(TYPE_REL8, "1-byte immediate address") \
430 ENUM_ENTRY(TYPE_REL16, "2-byte") \
431 ENUM_ENTRY(TYPE_REL32, "4-byte") \
432 ENUM_ENTRY(TYPE_REL64, "8-byte") \
433 ENUM_ENTRY(TYPE_PTR1616, "2+2-byte segment+offset address") \
434 ENUM_ENTRY(TYPE_PTR1632, "2+4-byte") \
435 ENUM_ENTRY(TYPE_PTR1664, "2+8-byte") \
436 ENUM_ENTRY(TYPE_R8, "1-byte register operand") \
437 ENUM_ENTRY(TYPE_R16, "2-byte") \
438 ENUM_ENTRY(TYPE_R32, "4-byte") \
439 ENUM_ENTRY(TYPE_R64, "8-byte") \
440 ENUM_ENTRY(TYPE_IMM8, "1-byte immediate operand") \
441 ENUM_ENTRY(TYPE_IMM16, "2-byte") \
442 ENUM_ENTRY(TYPE_IMM32, "4-byte") \
443 ENUM_ENTRY(TYPE_IMM64, "8-byte") \
Sean Callanan1efe6612010-04-07 21:42:19 +0000[diff] [blame]444 ENUM_ENTRY(TYPE_IMM3, "1-byte immediate operand between 0 and 7") \
Craig Topper7629d632012-04-03 05:20:24 +0000[diff] [blame]445 ENUM_ENTRY(TYPE_IMM5, "1-byte immediate operand between 0 and 31") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]446 ENUM_ENTRY(TYPE_RM8, "1-byte register or memory operand") \
447 ENUM_ENTRY(TYPE_RM16, "2-byte") \
448 ENUM_ENTRY(TYPE_RM32, "4-byte") \
449 ENUM_ENTRY(TYPE_RM64, "8-byte") \
450 ENUM_ENTRY(TYPE_M, "Memory operand") \
451 ENUM_ENTRY(TYPE_M8, "1-byte") \
452 ENUM_ENTRY(TYPE_M16, "2-byte") \
453 ENUM_ENTRY(TYPE_M32, "4-byte") \
454 ENUM_ENTRY(TYPE_M64, "8-byte") \
Sean Callanan36eab802009-12-22 21:12:55 +0000[diff] [blame]455 ENUM_ENTRY(TYPE_LEA, "Effective address") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]456 ENUM_ENTRY(TYPE_M128, "16-byte (SSE/SSE2)") \
Chris Lattnerf60062f2010-09-29 02:57:56 +0000[diff] [blame]457 ENUM_ENTRY(TYPE_M256, "256-byte (AVX)") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]458 ENUM_ENTRY(TYPE_M1616, "2+2-byte segment+offset address") \
459 ENUM_ENTRY(TYPE_M1632, "2+4-byte") \
460 ENUM_ENTRY(TYPE_M1664, "2+8-byte") \
461 ENUM_ENTRY(TYPE_M16_32, "2+4-byte two-part memory operand (LIDT, LGDT)") \
462 ENUM_ENTRY(TYPE_M16_16, "2+2-byte (BOUND)") \
463 ENUM_ENTRY(TYPE_M32_32, "4+4-byte (BOUND)") \
464 ENUM_ENTRY(TYPE_M16_64, "2+8-byte (LIDT, LGDT)") \
David Woodhouse2ef8d9c2014-01-22 15:08:08 +0000[diff] [blame]465 ENUM_ENTRY(TYPE_SRCIDX8, "1-byte memory at source index") \
466 ENUM_ENTRY(TYPE_SRCIDX16, "2-byte memory at source index") \
467 ENUM_ENTRY(TYPE_SRCIDX32, "4-byte memory at source index") \
468 ENUM_ENTRY(TYPE_SRCIDX64, "8-byte memory at source index") \
David Woodhouseb33c2ef2014-01-22 15:08:21 +0000[diff] [blame^]469 ENUM_ENTRY(TYPE_DSTIDX8, "1-byte memory at destination index") \
470 ENUM_ENTRY(TYPE_DSTIDX16, "2-byte memory at destination index") \
471 ENUM_ENTRY(TYPE_DSTIDX32, "4-byte memory at destination index") \
472 ENUM_ENTRY(TYPE_DSTIDX64, "8-byte memory at destination index") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]473 ENUM_ENTRY(TYPE_MOFFS8, "1-byte memory offset (relative to segment " \
474 "base)") \
475 ENUM_ENTRY(TYPE_MOFFS16, "2-byte") \
476 ENUM_ENTRY(TYPE_MOFFS32, "4-byte") \
477 ENUM_ENTRY(TYPE_MOFFS64, "8-byte") \
478 ENUM_ENTRY(TYPE_SREG, "Byte with single bit set: 0 = ES, 1 = CS, " \
479 "2 = SS, 3 = DS, 4 = FS, 5 = GS") \
480 ENUM_ENTRY(TYPE_M32FP, "32-bit IEE754 memory floating-point operand") \
481 ENUM_ENTRY(TYPE_M64FP, "64-bit") \
482 ENUM_ENTRY(TYPE_M80FP, "80-bit extended") \
483 ENUM_ENTRY(TYPE_M16INT, "2-byte memory integer operand for use in " \
484 "floating-point instructions") \
485 ENUM_ENTRY(TYPE_M32INT, "4-byte") \
486 ENUM_ENTRY(TYPE_M64INT, "8-byte") \
487 ENUM_ENTRY(TYPE_ST, "Position on the floating-point stack") \
488 ENUM_ENTRY(TYPE_MM, "MMX register operand") \
489 ENUM_ENTRY(TYPE_MM32, "4-byte MMX register or memory operand") \
490 ENUM_ENTRY(TYPE_MM64, "8-byte") \
491 ENUM_ENTRY(TYPE_XMM, "XMM register operand") \
492 ENUM_ENTRY(TYPE_XMM32, "4-byte XMM register or memory operand") \
493 ENUM_ENTRY(TYPE_XMM64, "8-byte") \
494 ENUM_ENTRY(TYPE_XMM128, "16-byte") \
Sean Callananc3fd5232011-03-15 01:23:15 +0000[diff] [blame]495 ENUM_ENTRY(TYPE_XMM256, "32-byte") \
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]496 ENUM_ENTRY(TYPE_XMM512, "64-byte") \
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]497 ENUM_ENTRY(TYPE_VK1, "1-bit") \
Elena Demikhovsky003e7d72013-07-28 08:28:38 +0000[diff] [blame]498 ENUM_ENTRY(TYPE_VK8, "8-bit") \
499 ENUM_ENTRY(TYPE_VK16, "16-bit") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]500 ENUM_ENTRY(TYPE_XMM0, "Implicit use of XMM0") \
501 ENUM_ENTRY(TYPE_SEGMENTREG, "Segment register operand") \
502 ENUM_ENTRY(TYPE_DEBUGREG, "Debug register operand") \
Sean Callanane7e1cf92010-05-06 20:59:00 +0000[diff] [blame]503 ENUM_ENTRY(TYPE_CONTROLREG, "Control register operand") \
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]504 \
505 ENUM_ENTRY(TYPE_Mv, "Memory operand of operand size") \
506 ENUM_ENTRY(TYPE_Rv, "Register operand of operand size") \
507 ENUM_ENTRY(TYPE_IMMv, "Immediate operand of operand size") \
508 ENUM_ENTRY(TYPE_RELv, "Immediate address of operand size") \
509 ENUM_ENTRY(TYPE_DUP0, "Duplicate of operand 0") \
510 ENUM_ENTRY(TYPE_DUP1, "operand 1") \
511 ENUM_ENTRY(TYPE_DUP2, "operand 2") \
512 ENUM_ENTRY(TYPE_DUP3, "operand 3") \
513 ENUM_ENTRY(TYPE_DUP4, "operand 4") \
514 ENUM_ENTRY(TYPE_M512, "512-bit FPU/MMX/XMM/MXCSR state")
515
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]516#define ENUM_ENTRY(n, d) n,
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]517typedef enum {
518 TYPES
519 TYPE_max
520} OperandType;
521#undef ENUM_ENTRY
522
Craig Topper5f33d902012-07-31 04:38:27 +0000[diff] [blame]523/*
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]524 * OperandSpecifier - The specification for how to extract and interpret one
525 * operand.
526 */
527struct OperandSpecifier {
Craig Topper6dedbae2012-03-04 02:16:41 +0000[diff] [blame]528 uint8_t encoding;
529 uint8_t type;
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]530};
531
532/*
533 * Indicates where the opcode modifier (if any) is to be found. Extended
534 * opcodes with AddRegFrm have the opcode modifier in the ModR/M byte.
535 */
536
537#define MODIFIER_TYPES \
Craig Topper91551182014-01-01 15:29:32 +0000[diff] [blame]538 ENUM_ENTRY(MODIFIER_NONE)
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]539
540#define ENUM_ENTRY(n) n,
541typedef enum {
542 MODIFIER_TYPES
543 MODIFIER_max
544} ModifierType;
545#undef ENUM_ENTRY
546
547#define X86_MAX_OPERANDS 5
548
549/*
550 * The specification for how to extract and interpret a full instruction and
551 * its operands.
552 */
553struct InstructionSpecifier {
Sean Callanan04cc3072009-12-19 02:59:52 +0000[diff] [blame]554 /* The macro below must be defined wherever this file is included. */
555 INSTRUCTION_SPECIFIER_FIELDS
556};
557
558/*
559 * Decoding mode for the Intel disassembler. 16-bit, 32-bit, and 64-bit mode
560 * are supported, and represent real mode, IA-32e, and IA-32e in 64-bit mode,
561 * respectively.
562 */
563typedef enum {
564 MODE_16BIT,
565 MODE_32BIT,
566 MODE_64BIT
567} DisassemblerMode;
568
569#endif