Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / b4a8b056f82016499b232c3840fca0945ea8f77a / . / llvm / docs / CodeGenerator.html
blob: 4f762dc956ad26083a001c239458b32db2db4172 [file] [log] [blame]
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]1<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01//EN"
2 "http://www.w3.org/TR/html4/strict.dtd">
3<html>
4<head>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]5 <meta http-equiv="content-type" content="text/html; charset=utf-8">
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]6 <title>The LLVM Target-Independent Code Generator</title>
7 <link rel="stylesheet" href="llvm.css" type="text/css">
Benjamin Kramerc940bcf2010-10-30 21:07:28 +0000[diff] [blame]8
9 <style type="text/css">
10 .unknown { background-color: #C0C0C0; text-align: center; }
11 .unknown:before { content: "?" }
12 .no { background-color: #C11B17 }
13 .no:before { content: "N" }
14 .partial { background-color: #F88017 }
15 .yes { background-color: #0F0; }
16 .yes:before { content: "Y" }
17 </style>
18
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]19</head>
20<body>
21
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]22<h1>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]23 The LLVM Target-Independent Code Generator
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]24</h1>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]25
26<ol>
27 <li><a href="#introduction">Introduction</a>
28 <ul>
29 <li><a href="#required">Required components in the code generator</a></li>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]30 <li><a href="#high-level-design">The high-level design of the code
31 generator</a></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]32 <li><a href="#tablegen">Using TableGen for target description</a></li>
33 </ul>
34 </li>
35 <li><a href="#targetdesc">Target description classes</a>
36 <ul>
37 <li><a href="#targetmachine">The <tt>TargetMachine</tt> class</a></li>
38 <li><a href="#targetdata">The <tt>TargetData</tt> class</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]39 <li><a href="#targetlowering">The <tt>TargetLowering</tt> class</a></li>
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]40 <li><a href="#targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]41 <li><a href="#targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a></li>
42 <li><a href="#targetframeinfo">The <tt>TargetFrameInfo</tt> class</a></li>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]43 <li><a href="#targetsubtarget">The <tt>TargetSubtarget</tt> class</a></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]44 <li><a href="#targetjitinfo">The <tt>TargetJITInfo</tt> class</a></li>
45 </ul>
46 </li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]47 <li><a href="#codegendesc">The "Machine" Code Generator classes</a>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]48 <ul>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]49 <li><a href="#machineinstr">The <tt>MachineInstr</tt> class</a></li>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]50 <li><a href="#machinebasicblock">The <tt>MachineBasicBlock</tt>
51 class</a></li>
52 <li><a href="#machinefunction">The <tt>MachineFunction</tt> class</a></li>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]53 </ul>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]54 </li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]55 <li><a href="#mc">The "MC" Layer</a>
56 <ul>
57 <li><a href="#mcstreamer">The <tt>MCStreamer</tt> API</a></li>
58 <li><a href="#mccontext">The <tt>MCContext</tt> class</a>
59 <li><a href="#mcsymbol">The <tt>MCSymbol</tt> class</a></li>
60 <li><a href="#mcsection">The <tt>MCSection</tt> class</a></li>
61 <li><a href="#mcinst">The <tt>MCInst</tt> class</a></li>
62 </ul>
63 </li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]64 <li><a href="#codegenalgs">Target-independent code generation algorithms</a>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]65 <ul>
66 <li><a href="#instselect">Instruction Selection</a>
67 <ul>
68 <li><a href="#selectiondag_intro">Introduction to SelectionDAGs</a></li>
69 <li><a href="#selectiondag_process">SelectionDAG Code Generation
70 Process</a></li>
71 <li><a href="#selectiondag_build">Initial SelectionDAG
72 Construction</a></li>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]73 <li><a href="#selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]74 <li><a href="#selectiondag_legalize">SelectionDAG Legalize Phase</a></li>
75 <li><a href="#selectiondag_optimize">SelectionDAG Optimization
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]76 Phase: the DAG Combiner</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]77 <li><a href="#selectiondag_select">SelectionDAG Select Phase</a></li>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]78 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]79 Phase</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]80 <li><a href="#selectiondag_future">Future directions for the
81 SelectionDAG</a></li>
82 </ul></li>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]83 <li><a href="#liveintervals">Live Intervals</a>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]84 <ul>
85 <li><a href="#livevariable_analysis">Live Variable Analysis</a></li>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]86 <li><a href="#liveintervals_analysis">Live Intervals Analysis</a></li>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]87 </ul></li>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]88 <li><a href="#regalloc">Register Allocation</a>
89 <ul>
90 <li><a href="#regAlloc_represent">How registers are represented in
91 LLVM</a></li>
92 <li><a href="#regAlloc_howTo">Mapping virtual registers to physical
93 registers</a></li>
94 <li><a href="#regAlloc_twoAddr">Handling two address instructions</a></li>
95 <li><a href="#regAlloc_ssaDecon">The SSA deconstruction phase</a></li>
96 <li><a href="#regAlloc_fold">Instruction folding</a></li>
97 <li><a href="#regAlloc_builtIn">Built in register allocators</a></li>
98 </ul></li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]99 <li><a href="#codeemit">Code Emission</a></li>
Anshuman Dasguptabcfa2f82011-12-06 23:12:42 +0000[diff] [blame]100 <li><a href="#vliw_packetizer">VLIW Packetizer</a>
101 <ul>
102 <li><a href="#vliw_mapping">Mapping from instructions to functional
103 units</a></li>
104 <li><a href="#vliw_repr">How the packetization tables are
105 generated and used</a></li>
106 </ul>
107 </li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]108 </ul>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]109 </li>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]110 <li><a href="#nativeassembler">Implementing a Native Assembler</a></li>
111
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]112 <li><a href="#targetimpls">Target-specific Implementation Notes</a>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]113 <ul>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]114 <li><a href="#targetfeatures">Target Feature Matrix</a></li>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]115 <li><a href="#tailcallopt">Tail call optimization</a></li>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]116 <li><a href="#sibcallopt">Sibling call optimization</a></li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]117 <li><a href="#x86">The X86 backend</a></li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]118 <li><a href="#ppc">The PowerPC backend</a>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]119 <ul>
120 <li><a href="#ppc_abi">LLVM PowerPC ABI</a></li>
121 <li><a href="#ppc_frame">Frame Layout</a></li>
122 <li><a href="#ppc_prolog">Prolog/Epilog</a></li>
123 <li><a href="#ppc_dynamic">Dynamic Allocation</a></li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]124 </ul></li>
Justin Holewinski6c6a7fd2011-08-11 17:34:16 +0000[diff] [blame]125 <li><a href="#ptx">The PTX backend</a></li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]126 </ul></li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]127
128</ol>
129
130<div class="doc_author">
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]131 <p>Written by the LLVM Team.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]132</div>
133
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]134<div class="doc_warning">
135 <p>Warning: This is a work in progress.</p>
136</div>
137
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]138<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]139<h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]140 <a name="introduction">Introduction</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]141</h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]142<!-- *********************************************************************** -->
143
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]144<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]145
146<p>The LLVM target-independent code generator is a framework that provides a
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]147 suite of reusable components for translating the LLVM internal representation
148 to the machine code for a specified target&mdash;either in assembly form
149 (suitable for a static compiler) or in binary machine code format (usable for
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]150 a JIT compiler). The LLVM target-independent code generator consists of six
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]151 main components:</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]152
153<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]154 <li><a href="#targetdesc">Abstract target description</a> interfaces which
155 capture important properties about various aspects of the machine,
156 independently of how they will be used. These interfaces are defined in
157 <tt>include/llvm/Target/</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]158
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]159 <li>Classes used to represent the <a href="#codegendesc">code being
160 generated</a> for a target. These classes are intended to be abstract
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]161 enough to represent the machine code for <i>any</i> target machine. These
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]162 classes are defined in <tt>include/llvm/CodeGen/</tt>. At this level,
163 concepts like "constant pool entries" and "jump tables" are explicitly
164 exposed.</li>
165
166 <li>Classes and algorithms used to represent code as the object file level,
167 the <a href="#mc">MC Layer</a>. These classes represent assembly level
168 constructs like labels, sections, and instructions. At this level,
169 concepts like "constant pool entries" and "jump tables" don't exist.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]170
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]171 <li><a href="#codegenalgs">Target-independent algorithms</a> used to implement
172 various phases of native code generation (register allocation, scheduling,
173 stack frame representation, etc). This code lives
174 in <tt>lib/CodeGen/</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]175
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]176 <li><a href="#targetimpls">Implementations of the abstract target description
177 interfaces</a> for particular targets. These machine descriptions make
178 use of the components provided by LLVM, and can optionally provide custom
179 target-specific passes, to build complete code generators for a specific
180 target. Target descriptions live in <tt>lib/Target/</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]181
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]182 <li><a href="#jit">The target-independent JIT components</a>. The LLVM JIT is
183 completely target independent (it uses the <tt>TargetJITInfo</tt>
184 structure to interface for target-specific issues. The code for the
185 target-independent JIT lives in <tt>lib/ExecutionEngine/JIT</tt>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]186</ol>
187
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]188<p>Depending on which part of the code generator you are interested in working
189 on, different pieces of this will be useful to you. In any case, you should
190 be familiar with the <a href="#targetdesc">target description</a>
191 and <a href="#codegendesc">machine code representation</a> classes. If you
192 want to add a backend for a new target, you will need
193 to <a href="#targetimpls">implement the target description</a> classes for
194 your new target and understand the <a href="LangRef.html">LLVM code
195 representation</a>. If you are interested in implementing a
196 new <a href="#codegenalgs">code generation algorithm</a>, it should only
197 depend on the target-description and machine code representation classes,
198 ensuring that it is portable.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]199
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]200<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]201<h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]202 <a name="required">Required components in the code generator</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]203</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]204
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]205<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]206
207<p>The two pieces of the LLVM code generator are the high-level interface to the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]208 code generator and the set of reusable components that can be used to build
209 target-specific backends. The two most important interfaces
210 (<a href="#targetmachine"><tt>TargetMachine</tt></a>
211 and <a href="#targetdata"><tt>TargetData</tt></a>) are the only ones that are
212 required to be defined for a backend to fit into the LLVM system, but the
213 others must be defined if the reusable code generator components are going to
214 be used.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]215
216<p>This design has two important implications. The first is that LLVM can
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]217 support completely non-traditional code generation targets. For example, the
218 C backend does not require register allocation, instruction selection, or any
219 of the other standard components provided by the system. As such, it only
220 implements these two interfaces, and does its own thing. Another example of
221 a code generator like this is a (purely hypothetical) backend that converts
222 LLVM to the GCC RTL form and uses GCC to emit machine code for a target.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]223
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]224<p>This design also implies that it is possible to design and implement
225 radically different code generators in the LLVM system that do not make use
226 of any of the built-in components. Doing so is not recommended at all, but
227 could be required for radically different targets that do not fit into the
228 LLVM machine description model: FPGAs for example.</p>
Chris Lattnere6cad6c2004-06-02 07:06:06 +0000[diff] [blame]229
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]230</div>
231
232<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]233<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]234 <a name="high-level-design">The high-level design of the code generator</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]235</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]236
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]237<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]238
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]239<p>The LLVM target-independent code generator is designed to support efficient
240 and quality code generation for standard register-based microprocessors.
241 Code generation in this model is divided into the following stages:</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]242
243<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]244 <li><b><a href="#instselect">Instruction Selection</a></b> &mdash; This phase
245 determines an efficient way to express the input LLVM code in the target
246 instruction set. This stage produces the initial code for the program in
247 the target instruction set, then makes use of virtual registers in SSA
248 form and physical registers that represent any required register
249 assignments due to target constraints or calling conventions. This step
250 turns the LLVM code into a DAG of target instructions.</li>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]251
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]252 <li><b><a href="#selectiondag_sched">Scheduling and Formation</a></b> &mdash;
253 This phase takes the DAG of target instructions produced by the
254 instruction selection phase, determines an ordering of the instructions,
255 then emits the instructions
256 as <tt><a href="#machineinstr">MachineInstr</a></tt>s with that ordering.
257 Note that we describe this in the <a href="#instselect">instruction
258 selection section</a> because it operates on
259 a <a href="#selectiondag_intro">SelectionDAG</a>.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]260
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]261 <li><b><a href="#ssamco">SSA-based Machine Code Optimizations</a></b> &mdash;
262 This optional stage consists of a series of machine-code optimizations
263 that operate on the SSA-form produced by the instruction selector.
264 Optimizations like modulo-scheduling or peephole optimization work
265 here.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]266
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]267 <li><b><a href="#regalloc">Register Allocation</a></b> &mdash; The target code
268 is transformed from an infinite virtual register file in SSA form to the
269 concrete register file used by the target. This phase introduces spill
270 code and eliminates all virtual register references from the program.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]271
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]272 <li><b><a href="#proepicode">Prolog/Epilog Code Insertion</a></b> &mdash; Once
273 the machine code has been generated for the function and the amount of
274 stack space required is known (used for LLVM alloca's and spill slots),
275 the prolog and epilog code for the function can be inserted and "abstract
276 stack location references" can be eliminated. This stage is responsible
277 for implementing optimizations like frame-pointer elimination and stack
278 packing.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]279
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]280 <li><b><a href="#latemco">Late Machine Code Optimizations</a></b> &mdash;
281 Optimizations that operate on "final" machine code can go here, such as
282 spill code scheduling and peephole optimizations.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]283
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]284 <li><b><a href="#codeemit">Code Emission</a></b> &mdash; The final stage
285 actually puts out the code for the current function, either in the target
286 assembler format or in machine code.</li>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]287</ol>
288
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]289<p>The code generator is based on the assumption that the instruction selector
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]290 will use an optimal pattern matching selector to create high-quality
291 sequences of native instructions. Alternative code generator designs based
292 on pattern expansion and aggressive iterative peephole optimization are much
293 slower. This design permits efficient compilation (important for JIT
294 environments) and aggressive optimization (used when generating code offline)
295 by allowing components of varying levels of sophistication to be used for any
296 step of compilation.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]297
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]298<p>In addition to these stages, target implementations can insert arbitrary
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]299 target-specific passes into the flow. For example, the X86 target uses a
300 special pass to handle the 80x87 floating point stack architecture. Other
301 targets with unusual requirements can be supported with custom passes as
302 needed.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]303
304</div>
305
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]306<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]307<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]308 <a name="tablegen">Using TableGen for target description</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]309</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]310
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]311<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]312
Chris Lattnerd9be5fa2004-06-01 18:35:00 +0000[diff] [blame]313<p>The target description classes require a detailed description of the target
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]314 architecture. These target descriptions often have a large amount of common
315 information (e.g., an <tt>add</tt> instruction is almost identical to a
316 <tt>sub</tt> instruction). In order to allow the maximum amount of
317 commonality to be factored out, the LLVM code generator uses
318 the <a href="TableGenFundamentals.html">TableGen</a> tool to describe big
319 chunks of the target machine, which allows the use of domain-specific and
320 target-specific abstractions to reduce the amount of repetition.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]321
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]322<p>As LLVM continues to be developed and refined, we plan to move more and more
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]323 of the target description to the <tt>.td</tt> form. Doing so gives us a
324 number of advantages. The most important is that it makes it easier to port
325 LLVM because it reduces the amount of C++ code that has to be written, and
326 the surface area of the code generator that needs to be understood before
327 someone can get something working. Second, it makes it easier to change
328 things. In particular, if tables and other things are all emitted
329 by <tt>tblgen</tt>, we only need a change in one place (<tt>tblgen</tt>) to
330 update all of the targets to a new interface.</p>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]331
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]332</div>
333
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]334</div>
335
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]336<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]337<h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]338 <a name="targetdesc">Target description classes</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]339</h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]340<!-- *********************************************************************** -->
341
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]342<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]343
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]344<p>The LLVM target description classes (located in the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]345 <tt>include/llvm/Target</tt> directory) provide an abstract description of
346 the target machine independent of any particular client. These classes are
347 designed to capture the <i>abstract</i> properties of the target (such as the
348 instructions and registers it has), and do not incorporate any particular
349 pieces of code generation algorithms.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]350
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]351<p>All of the target description classes (except the
352 <tt><a href="#targetdata">TargetData</a></tt> class) are designed to be
353 subclassed by the concrete target implementation, and have virtual methods
354 implemented. To get to these implementations, the
355 <tt><a href="#targetmachine">TargetMachine</a></tt> class provides accessors
356 that should be implemented by the target.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]357
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]358<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]359<h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]360 <a name="targetmachine">The <tt>TargetMachine</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]361</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]362
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]363<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]364
365<p>The <tt>TargetMachine</tt> class provides virtual methods that are used to
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]366 access the target-specific implementations of the various target description
367 classes via the <tt>get*Info</tt> methods (<tt>getInstrInfo</tt>,
368 <tt>getRegisterInfo</tt>, <tt>getFrameInfo</tt>, etc.). This class is
369 designed to be specialized by a concrete target implementation
370 (e.g., <tt>X86TargetMachine</tt>) which implements the various virtual
371 methods. The only required target description class is
372 the <a href="#targetdata"><tt>TargetData</tt></a> class, but if the code
373 generator components are to be used, the other interfaces should be
374 implemented as well.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]375
376</div>
377
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]378<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]379<h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]380 <a name="targetdata">The <tt>TargetData</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]381</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]382
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]383<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]384
385<p>The <tt>TargetData</tt> class is the only required target description class,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]386 and it is the only class that is not extensible (you cannot derived a new
387 class from it). <tt>TargetData</tt> specifies information about how the
388 target lays out memory for structures, the alignment requirements for various
389 data types, the size of pointers in the target, and whether the target is
390 little-endian or big-endian.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]391
392</div>
393
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]394<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]395<h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]396 <a name="targetlowering">The <tt>TargetLowering</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]397</h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]398
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]399<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]400
401<p>The <tt>TargetLowering</tt> class is used by SelectionDAG based instruction
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]402 selectors primarily to describe how LLVM code should be lowered to
403 SelectionDAG operations. Among other things, this class indicates:</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]404
405<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]406 <li>an initial register class to use for various <tt>ValueType</tt>s,</li>
407
408 <li>which operations are natively supported by the target machine,</li>
409
410 <li>the return type of <tt>setcc</tt> operations,</li>
411
412 <li>the type to use for shift amounts, and</li>
413
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]414 <li>various high-level characteristics, like whether it is profitable to turn
415 division by a constant into a multiplication sequence</li>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]416</ul>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]417
418</div>
419
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]420<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]421<h3>
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]422 <a name="targetregisterinfo">The <tt>TargetRegisterInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]423</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]424
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]425<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]426
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]427<p>The <tt>TargetRegisterInfo</tt> class is used to describe the register file
428 of the target and any interactions between the registers.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]429
430<p>Registers in the code generator are represented in the code generator by
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]431 unsigned integers. Physical registers (those that actually exist in the
432 target description) are unique small numbers, and virtual registers are
433 generally large. Note that register #0 is reserved as a flag value.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]434
435<p>Each register in the processor description has an associated
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]436 <tt>TargetRegisterDesc</tt> entry, which provides a textual name for the
437 register (used for assembly output and debugging dumps) and a set of aliases
438 (used to indicate whether one register overlaps with another).</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]439
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]440<p>In addition to the per-register description, the <tt>TargetRegisterInfo</tt>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]441 class exposes a set of processor specific register classes (instances of the
442 <tt>TargetRegisterClass</tt> class). Each register class contains sets of
443 registers that have the same properties (for example, they are all 32-bit
444 integer registers). Each SSA virtual register created by the instruction
445 selector has an associated register class. When the register allocator runs,
446 it replaces virtual registers with a physical register in the set.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]447
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]448<p>The target-specific implementations of these classes is auto-generated from
449 a <a href="TableGenFundamentals.html">TableGen</a> description of the
450 register file.</p>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]451
452</div>
453
454<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]455<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]456 <a name="targetinstrinfo">The <tt>TargetInstrInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]457</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]458
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]459<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]460
461<p>The <tt>TargetInstrInfo</tt> class is used to describe the machine
462 instructions supported by the target. It is essentially an array of
463 <tt>TargetInstrDescriptor</tt> objects, each of which describes one
464 instruction the target supports. Descriptors define things like the mnemonic
465 for the opcode, the number of operands, the list of implicit register uses
466 and defs, whether the instruction has certain target-independent properties
467 (accesses memory, is commutable, etc), and holds any target-specific
468 flags.</p>
469
Reid Spencere5dc84b2005-07-19 01:36:35 +0000[diff] [blame]470</div>
471
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]472<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]473<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]474 <a name="targetframeinfo">The <tt>TargetFrameInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]475</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]476
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]477<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]478
479<p>The <tt>TargetFrameInfo</tt> class is used to provide information about the
480 stack frame layout of the target. It holds the direction of stack growth, the
481 known stack alignment on entry to each function, and the offset to the local
482 area. The offset to the local area is the offset from the stack pointer on
483 function entry to the first location where function data (local variables,
484 spill locations) can be stored.</p>
485
Reid Spencere5dc84b2005-07-19 01:36:35 +0000[diff] [blame]486</div>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]487
488<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]489<h3>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]490 <a name="targetsubtarget">The <tt>TargetSubtarget</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]491</h3>
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]492
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]493<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]494
495<p>The <tt>TargetSubtarget</tt> class is used to provide information about the
496 specific chip set being targeted. A sub-target informs code generation of
497 which instructions are supported, instruction latencies and instruction
498 execution itinerary; i.e., which processing units are used, in what order,
499 and for how long.</p>
500
Chris Lattnerc9afa282005-10-16 17:06:07 +0000[diff] [blame]501</div>
502
503
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]504<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]505<h3>
Chris Lattnerf249fdc2004-06-01 17:18:11 +0000[diff] [blame]506 <a name="targetjitinfo">The <tt>TargetJITInfo</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]507</h3>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]508
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]509<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]510
511<p>The <tt>TargetJITInfo</tt> class exposes an abstract interface used by the
512 Just-In-Time code generator to perform target-specific activities, such as
513 emitting stubs. If a <tt>TargetMachine</tt> supports JIT code generation, it
514 should provide one of these objects through the <tt>getJITInfo</tt>
515 method.</p>
516
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]517</div>
518
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]519</div>
520
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]521<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]522<h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]523 <a name="codegendesc">Machine code description classes</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]524</h2>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]525<!-- *********************************************************************** -->
526
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]527<div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]528
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]529<p>At the high-level, LLVM code is translated to a machine specific
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]530 representation formed out of
531 <a href="#machinefunction"><tt>MachineFunction</tt></a>,
532 <a href="#machinebasicblock"><tt>MachineBasicBlock</tt></a>,
533 and <a href="#machineinstr"><tt>MachineInstr</tt></a> instances (defined
534 in <tt>include/llvm/CodeGen</tt>). This representation is completely target
535 agnostic, representing instructions in their most abstract form: an opcode
536 and a series of operands. This representation is designed to support both an
537 SSA representation for machine code, as well as a register allocated, non-SSA
538 form.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]539
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]540<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]541<h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]542 <a name="machineinstr">The <tt>MachineInstr</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]543</h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]544
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]545<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]546
547<p>Target machine instructions are represented as instances of the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]548 <tt>MachineInstr</tt> class. This class is an extremely abstract way of
549 representing machine instructions. In particular, it only keeps track of an
550 opcode number and a set of operands.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]551
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]552<p>The opcode number is a simple unsigned integer that only has meaning to a
553 specific backend. All of the instructions for a target should be defined in
554 the <tt>*InstrInfo.td</tt> file for the target. The opcode enum values are
555 auto-generated from this description. The <tt>MachineInstr</tt> class does
556 not have any information about how to interpret the instruction (i.e., what
557 the semantics of the instruction are); for that you must refer to the
558 <tt><a href="#targetinstrinfo">TargetInstrInfo</a></tt> class.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]559
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]560<p>The operands of a machine instruction can be of several different types: a
561 register reference, a constant integer, a basic block reference, etc. In
562 addition, a machine operand should be marked as a def or a use of the value
563 (though only registers are allowed to be defs).</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]564
565<p>By convention, the LLVM code generator orders instruction operands so that
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]566 all register definitions come before the register uses, even on architectures
567 that are normally printed in other orders. For example, the SPARC add
568 instruction: "<tt>add %i1, %i2, %i3</tt>" adds the "%i1", and "%i2" registers
569 and stores the result into the "%i3" register. In the LLVM code generator,
570 the operands should be stored as "<tt>%i3, %i1, %i2</tt>": with the
571 destination first.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]572
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]573<p>Keeping destination (definition) operands at the beginning of the operand
574 list has several advantages. In particular, the debugging printer will print
575 the instruction like this:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]576
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]577<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]578<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]579%r3 = add %i1, %i2
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]580</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]581</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]582
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]583<p>Also if the first operand is a def, it is easier to <a href="#buildmi">create
584 instructions</a> whose only def is the first operand.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]585
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]586<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]587<h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]588 <a name="buildmi">Using the <tt>MachineInstrBuilder.h</tt> functions</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]589</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]590
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]591<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]592
593<p>Machine instructions are created by using the <tt>BuildMI</tt> functions,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]594 located in the <tt>include/llvm/CodeGen/MachineInstrBuilder.h</tt> file. The
595 <tt>BuildMI</tt> functions make it easy to build arbitrary machine
596 instructions. Usage of the <tt>BuildMI</tt> functions look like this:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]597
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]598<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]599<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]600// Create a 'DestReg = mov 42' (rendered in X86 assembly as 'mov DestReg, 42')
601// instruction. The '1' specifies how many operands will be added.
602MachineInstr *MI = BuildMI(X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]603
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]604// Create the same instr, but insert it at the end of a basic block.
605MachineBasicBlock &amp;MBB = ...
606BuildMI(MBB, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]607
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]608// Create the same instr, but insert it before a specified iterator point.
609MachineBasicBlock::iterator MBBI = ...
610BuildMI(MBB, MBBI, X86::MOV32ri, 1, DestReg).addImm(42);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]611
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]612// Create a 'cmp Reg, 0' instruction, no destination reg.
613MI = BuildMI(X86::CMP32ri, 2).addReg(Reg).addImm(0);
614// Create an 'sahf' instruction which takes no operands and stores nothing.
615MI = BuildMI(X86::SAHF, 0);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]616
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]617// Create a self looping branch instruction.
618BuildMI(MBB, X86::JNE, 1).addMBB(&amp;MBB);
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]619</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]620</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]621
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]622<p>The key thing to remember with the <tt>BuildMI</tt> functions is that you
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]623 have to specify the number of operands that the machine instruction will
624 take. This allows for efficient memory allocation. You also need to specify
625 if operands default to be uses of values, not definitions. If you need to
626 add a definition operand (other than the optional destination register), you
627 must explicitly mark it as such:</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]628
629<div class="doc_code">
630<pre>
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]631MI.addReg(Reg, RegState::Define);
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]632</pre>
633</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]634
635</div>
636
637<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]638<h4>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]639 <a name="fixedregs">Fixed (preassigned) registers</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]640</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]641
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]642<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]643
644<p>One important issue that the code generator needs to be aware of is the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]645 presence of fixed registers. In particular, there are often places in the
646 instruction stream where the register allocator <em>must</em> arrange for a
647 particular value to be in a particular register. This can occur due to
648 limitations of the instruction set (e.g., the X86 can only do a 32-bit divide
649 with the <tt>EAX</tt>/<tt>EDX</tt> registers), or external factors like
650 calling conventions. In any case, the instruction selector should emit code
651 that copies a virtual register into or out of a physical register when
652 needed.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]653
654<p>For example, consider this simple LLVM example:</p>
655
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]656<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]657<pre>
Matthijs Kooijmana6bb22e2008-06-04 15:46:35 +0000[diff] [blame]658define i32 @test(i32 %X, i32 %Y) {
659 %Z = udiv i32 %X, %Y
660 ret i32 %Z
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]661}
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]662</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]663</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]664
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]665<p>The X86 instruction selector produces this machine code for the <tt>div</tt>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]666 and <tt>ret</tt> (use "<tt>llc X.bc -march=x86 -print-machineinstrs</tt>" to
667 get this):</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]668
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]669<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]670<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]671;; Start of div
672%EAX = mov %reg1024 ;; Copy X (in reg1024) into EAX
673%reg1027 = sar %reg1024, 31
674%EDX = mov %reg1027 ;; Sign extend X into EDX
675idiv %reg1025 ;; Divide by Y (in reg1025)
676%reg1026 = mov %EAX ;; Read the result (Z) out of EAX
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]677
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]678;; Start of ret
679%EAX = mov %reg1026 ;; 32-bit return value goes in EAX
680ret
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]681</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]682</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]683
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]684<p>By the end of code generation, the register allocator has coalesced the
685 registers and deleted the resultant identity moves producing the following
686 code:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]687
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]688<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]689<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]690;; X is in EAX, Y is in ECX
691mov %EAX, %EDX
692sar %EDX, 31
693idiv %ECX
694ret
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]695</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]696</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]697
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]698<p>This approach is extremely general (if it can handle the X86 architecture, it
699 can handle anything!) and allows all of the target specific knowledge about
700 the instruction stream to be isolated in the instruction selector. Note that
701 physical registers should have a short lifetime for good code generation, and
702 all physical registers are assumed dead on entry to and exit from basic
703 blocks (before register allocation). Thus, if you need a value to be live
704 across basic block boundaries, it <em>must</em> live in a virtual
705 register.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]706
707</div>
708
709<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]710<h4>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]711 <a name="ssa">Machine code in SSA form</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]712</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]713
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]714<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]715
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]716<p><tt>MachineInstr</tt>'s are initially selected in SSA-form, and are
717 maintained in SSA-form until register allocation happens. For the most part,
718 this is trivially simple since LLVM is already in SSA form; LLVM PHI nodes
719 become machine code PHI nodes, and virtual registers are only allowed to have
720 a single definition.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]721
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]722<p>After register allocation, machine code is no longer in SSA-form because
723 there are no virtual registers left in the code.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]724
725</div>
726
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]727</div>
728
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]729<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]730<h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]731 <a name="machinebasicblock">The <tt>MachineBasicBlock</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]732</h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]733
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]734<div>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]735
736<p>The <tt>MachineBasicBlock</tt> class contains a list of machine instructions
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]737 (<tt><a href="#machineinstr">MachineInstr</a></tt> instances). It roughly
738 corresponds to the LLVM code input to the instruction selector, but there can
739 be a one-to-many mapping (i.e. one LLVM basic block can map to multiple
740 machine basic blocks). The <tt>MachineBasicBlock</tt> class has a
741 "<tt>getBasicBlock</tt>" method, which returns the LLVM basic block that it
742 comes from.</p>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]743
744</div>
745
746<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]747<h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]748 <a name="machinefunction">The <tt>MachineFunction</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]749</h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]750
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]751<div>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]752
753<p>The <tt>MachineFunction</tt> class contains a list of machine basic blocks
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]754 (<tt><a href="#machinebasicblock">MachineBasicBlock</a></tt> instances). It
755 corresponds one-to-one with the LLVM function input to the instruction
756 selector. In addition to a list of basic blocks,
757 the <tt>MachineFunction</tt> contains a a <tt>MachineConstantPool</tt>,
758 a <tt>MachineFrameInfo</tt>, a <tt>MachineFunctionInfo</tt>, and a
759 <tt>MachineRegisterInfo</tt>. See
760 <tt>include/llvm/CodeGen/MachineFunction.h</tt> for more information.</p>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]761
762</div>
763
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]764</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]765
766<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]767<h2>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]768 <a name="mc">The "MC" Layer</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]769</h2>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]770<!-- *********************************************************************** -->
771
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]772<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]773
774<p>
775The MC Layer is used to represent and process code at the raw machine code
776level, devoid of "high level" information like "constant pools", "jump tables",
777"global variables" or anything like that. At this level, LLVM handles things
778like label names, machine instructions, and sections in the object file. The
779code in this layer is used for a number of important purposes: the tail end of
780the code generator uses it to write a .s or .o file, and it is also used by the
Jay Foadfdb9f6a2011-04-13 13:03:56 +0000[diff] [blame]781llvm-mc tool to implement standalone machine code assemblers and disassemblers.
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]782</p>
783
784<p>
785This section describes some of the important classes. There are also a number
786of important subsystems that interact at this layer, they are described later
787in this manual.
788</p>
789
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]790<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]791<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]792 <a name="mcstreamer">The <tt>MCStreamer</tt> API</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]793</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]794
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]795<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]796
797<p>
798MCStreamer is best thought of as an assembler API. It is an abstract API which
799is <em>implemented</em> in different ways (e.g. to output a .s file, output an
800ELF .o file, etc) but whose API correspond directly to what you see in a .s
801file. MCStreamer has one method per directive, such as EmitLabel,
802EmitSymbolAttribute, SwitchSection, EmitValue (for .byte, .word), etc, which
803directly correspond to assembly level directives. It also has an
804EmitInstruction method, which is used to output an MCInst to the streamer.
805</p>
806
807<p>
808This API is most important for two clients: the llvm-mc stand-alone assembler is
809effectively a parser that parses a line, then invokes a method on MCStreamer. In
810the code generator, the <a href="#codeemit">Code Emission</a> phase of the code
811generator lowers higher level LLVM IR and Machine* constructs down to the MC
812layer, emitting directives through MCStreamer.</p>
813
814<p>
815On the implementation side of MCStreamer, there are two major implementations:
816one for writing out a .s file (MCAsmStreamer), and one for writing out a .o
817file (MCObjectStreamer). MCAsmStreamer is a straight-forward implementation
818that prints out a directive for each method (e.g. EmitValue -&gt; .byte), but
819MCObjectStreamer implements a full assembler.
820</p>
821
822</div>
823
824<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]825<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]826 <a name="mccontext">The <tt>MCContext</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]827</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]828
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]829<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]830
831<p>
832The MCContext class is the owner of a variety of uniqued data structures at the
833MC layer, including symbols, sections, etc. As such, this is the class that you
834interact with to create symbols and sections. This class can not be subclassed.
835</p>
836
837</div>
838
839<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]840<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]841 <a name="mcsymbol">The <tt>MCSymbol</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]842</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]843
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]844<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]845
846<p>
847The MCSymbol class represents a symbol (aka label) in the assembly file. There
848are two interesting kinds of symbols: assembler temporary symbols, and normal
849symbols. Assembler temporary symbols are used and processed by the assembler
850but are discarded when the object file is produced. The distinction is usually
851represented by adding a prefix to the label, for example "L" labels are
852assembler temporary labels in MachO.
853</p>
854
855<p>MCSymbols are created by MCContext and uniqued there. This means that
856MCSymbols can be compared for pointer equivalence to find out if they are the
857same symbol. Note that pointer inequality does not guarantee the labels will
858end up at different addresses though. It's perfectly legal to output something
859like this to the .s file:<p>
860
861<pre>
862 foo:
863 bar:
864 .byte 4
865</pre>
866
867<p>In this case, both the foo and bar symbols will have the same address.</p>
868
869</div>
870
871<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]872<h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]873 <a name="mcsection">The <tt>MCSection</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]874</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]875
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]876<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]877
878<p>
879The MCSection class represents an object-file specific section. It is subclassed
880by object file specific implementations (e.g. <tt>MCSectionMachO</tt>,
881<tt>MCSectionCOFF</tt>, <tt>MCSectionELF</tt>) and these are created and uniqued
882by MCContext. The MCStreamer has a notion of the current section, which can be
883changed with the SwitchToSection method (which corresponds to a ".section"
884directive in a .s file).
885</p>
886
887</div>
888
889<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]890<h3>
Benjamin Kramerc940bcf2010-10-30 21:07:28 +0000[diff] [blame]891 <a name="mcinst">The <tt>MCInst</tt> class</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]892</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]893
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]894<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]895
896<p>
897The MCInst class is a target-independent representation of an instruction. It
898is a simple class (much more so than <a href="#machineinstr">MachineInstr</a>)
899that holds a target-specific opcode and a vector of MCOperands. MCOperand, in
900turn, is a simple discriminated union of three cases: 1) a simple immediate,
9012) a target register ID, 3) a symbolic expression (e.g. "Lfoo-Lbar+42") as an
902MCExpr.
903</p>
904
905<p>MCInst is the common currency used to represent machine instructions at the
906MC layer. It is the type used by the instruction encoder, the instruction
907printer, and the type generated by the assembly parser and disassembler.
908</p>
909
910</div>
911
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]912</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]913
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]914<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]915<h2>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]916 <a name="codegenalgs">Target-independent code generation algorithms</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]917</h2>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]918<!-- *********************************************************************** -->
919
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]920<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]921
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]922<p>This section documents the phases described in the
923 <a href="#high-level-design">high-level design of the code generator</a>.
924 It explains how they work and some of the rationale behind their design.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]925
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]926<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]927<h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]928 <a name="instselect">Instruction Selection</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]929</h3>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]930
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]931<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]932
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]933<p>Instruction Selection is the process of translating LLVM code presented to
934 the code generator into target-specific machine instructions. There are
935 several well-known ways to do this in the literature. LLVM uses a
936 SelectionDAG based instruction selector.</p>
937
938<p>Portions of the DAG instruction selector are generated from the target
939 description (<tt>*.td</tt>) files. Our goal is for the entire instruction
940 selector to be generated from these <tt>.td</tt> files, though currently
941 there are still things that require custom C++ code.</p>
942
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]943<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]944<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]945 <a name="selectiondag_intro">Introduction to SelectionDAGs</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]946</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]947
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]948<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]949
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]950<p>The SelectionDAG provides an abstraction for code representation in a way
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]951 that is amenable to instruction selection using automatic techniques
952 (e.g. dynamic-programming based optimal pattern matching selectors). It is
953 also well-suited to other phases of code generation; in particular,
954 instruction scheduling (SelectionDAG's are very close to scheduling DAGs
955 post-selection). Additionally, the SelectionDAG provides a host
956 representation where a large variety of very-low-level (but
957 target-independent) <a href="#selectiondag_optimize">optimizations</a> may be
958 performed; ones which require extensive information about the instructions
959 efficiently supported by the target.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]960
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]961<p>The SelectionDAG is a Directed-Acyclic-Graph whose nodes are instances of the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]962 <tt>SDNode</tt> class. The primary payload of the <tt>SDNode</tt> is its
963 operation code (Opcode) that indicates what operation the node performs and
964 the operands to the operation. The various operation node types are
965 described at the top of the <tt>include/llvm/CodeGen/SelectionDAGNodes.h</tt>
966 file.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]967
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]968<p>Although most operations define a single value, each node in the graph may
969 define multiple values. For example, a combined div/rem operation will
970 define both the dividend and the remainder. Many other situations require
971 multiple values as well. Each node also has some number of operands, which
972 are edges to the node defining the used value. Because nodes may define
973 multiple values, edges are represented by instances of the <tt>SDValue</tt>
974 class, which is a <tt>&lt;SDNode, unsigned&gt;</tt> pair, indicating the node
975 and result value being used, respectively. Each value produced by
976 an <tt>SDNode</tt> has an associated <tt>MVT</tt> (Machine Value Type)
977 indicating what the type of the value is.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]978
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]979<p>SelectionDAGs contain two different kinds of values: those that represent
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]980 data flow and those that represent control flow dependencies. Data values
981 are simple edges with an integer or floating point value type. Control edges
982 are represented as "chain" edges which are of type <tt>MVT::Other</tt>.
983 These edges provide an ordering between nodes that have side effects (such as
984 loads, stores, calls, returns, etc). All nodes that have side effects should
985 take a token chain as input and produce a new one as output. By convention,
986 token chain inputs are always operand #0, and chain results are always the
987 last value produced by an operation.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]988
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]989<p>A SelectionDAG has designated "Entry" and "Root" nodes. The Entry node is
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]990 always a marker node with an Opcode of <tt>ISD::EntryToken</tt>. The Root
991 node is the final side-effecting node in the token chain. For example, in a
992 single basic block function it would be the return node.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]993
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]994<p>One important concept for SelectionDAGs is the notion of a "legal" vs.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]995 "illegal" DAG. A legal DAG for a target is one that only uses supported
996 operations and supported types. On a 32-bit PowerPC, for example, a DAG with
997 a value of type i1, i8, i16, or i64 would be illegal, as would a DAG that
998 uses a SREM or UREM operation. The
999 <a href="#selectinodag_legalize_types">legalize types</a> and
1000 <a href="#selectiondag_legalize">legalize operations</a> phases are
1001 responsible for turning an illegal DAG into a legal DAG.</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1002
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1003</div>
1004
1005<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1006<h4>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1007 <a name="selectiondag_process">SelectionDAG Instruction Selection Process</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1008</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1009
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1010<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1011
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1012<p>SelectionDAG-based instruction selection consists of the following steps:</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1013
1014<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1015 <li><a href="#selectiondag_build">Build initial DAG</a> &mdash; This stage
1016 performs a simple translation from the input LLVM code to an illegal
1017 SelectionDAG.</li>
1018
1019 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; This
1020 stage performs simple optimizations on the SelectionDAG to simplify it,
1021 and recognize meta instructions (like rotates
1022 and <tt>div</tt>/<tt>rem</tt> pairs) for targets that support these meta
1023 operations. This makes the resultant code more efficient and
1024 the <a href="#selectiondag_select">select instructions from DAG</a> phase
1025 (below) simpler.</li>
1026
1027 <li><a href="#selectiondag_legalize_types">Legalize SelectionDAG Types</a>
1028 &mdash; This stage transforms SelectionDAG nodes to eliminate any types
1029 that are unsupported on the target.</li>
1030
1031 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1032 SelectionDAG optimizer is run to clean up redundancies exposed by type
1033 legalization.</li>
1034
Chris Lattner053a0252010-12-12 02:42:57 +0000[diff] [blame]1035 <li><a href="#selectiondag_legalize">Legalize SelectionDAG Ops</a> &mdash;
Chris Lattnerbd614442010-12-13 00:17:12 +0000[diff] [blame]1036 This stage transforms SelectionDAG nodes to eliminate any operations
1037 that are unsupported on the target.</li>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1038
1039 <li><a href="#selectiondag_optimize">Optimize SelectionDAG</a> &mdash; The
1040 SelectionDAG optimizer is run to eliminate inefficiencies introduced by
1041 operation legalization.</li>
1042
1043 <li><a href="#selectiondag_select">Select instructions from DAG</a> &mdash;
1044 Finally, the target instruction selector matches the DAG operations to
1045 target instructions. This process translates the target-independent input
1046 DAG into another DAG of target instructions.</li>
1047
1048 <li><a href="#selectiondag_sched">SelectionDAG Scheduling and Formation</a>
1049 &mdash; The last phase assigns a linear order to the instructions in the
1050 target-instruction DAG and emits them into the MachineFunction being
1051 compiled. This step uses traditional prepass scheduling techniques.</li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1052</ol>
1053
1054<p>After all of these steps are complete, the SelectionDAG is destroyed and the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1055 rest of the code generation passes are run.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1056
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1057<p>One great way to visualize what is going on here is to take advantage of a
1058 few LLC command line options. The following options pop up a window
1059 displaying the SelectionDAG at specific times (if you only get errors printed
1060 to the console while using this, you probably
1061 <a href="ProgrammersManual.html#ViewGraph">need to configure your system</a>
1062 to add support for it).</p>
Dan Gohmandd51d522008-09-10 22:23:41 +0000[diff] [blame]1063
1064<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1065 <li><tt>-view-dag-combine1-dags</tt> displays the DAG after being built,
1066 before the first optimization pass.</li>
1067
1068 <li><tt>-view-legalize-dags</tt> displays the DAG before Legalization.</li>
1069
1070 <li><tt>-view-dag-combine2-dags</tt> displays the DAG before the second
1071 optimization pass.</li>
1072
1073 <li><tt>-view-isel-dags</tt> displays the DAG before the Select phase.</li>
1074
1075 <li><tt>-view-sched-dags</tt> displays the DAG before Scheduling.</li>
Dan Gohmandd51d522008-09-10 22:23:41 +0000[diff] [blame]1076</ul>
1077
1078<p>The <tt>-view-sunit-dags</tt> displays the Scheduler's dependency graph.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1079 This graph is based on the final SelectionDAG, with nodes that must be
1080 scheduled together bundled into a single scheduling-unit node, and with
1081 immediate operands and other nodes that aren't relevant for scheduling
1082 omitted.</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1083
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1084</div>
1085
1086<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1087<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1088 <a name="selectiondag_build">Initial SelectionDAG Construction</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1089</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1090
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1091<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1092
Bill Wendling6737f5d2006-08-28 03:04:05 +0000[diff] [blame]1093<p>The initial SelectionDAG is na&iuml;vely peephole expanded from the LLVM
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1094 input by the <tt>SelectionDAGLowering</tt> class in the
1095 <tt>lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp</tt> file. The intent of
1096 this pass is to expose as much low-level, target-specific details to the
1097 SelectionDAG as possible. This pass is mostly hard-coded (e.g. an
1098 LLVM <tt>add</tt> turns into an <tt>SDNode add</tt> while a
1099 <tt>getelementptr</tt> is expanded into the obvious arithmetic). This pass
1100 requires target-specific hooks to lower calls, returns, varargs, etc. For
1101 these features, the <tt><a href="#targetlowering">TargetLowering</a></tt>
1102 interface is used.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1103
1104</div>
1105
1106<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1107<h4>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1108 <a name="selectiondag_legalize_types">SelectionDAG LegalizeTypes Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1109</h4>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1110
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1111<div>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1112
1113<p>The Legalize phase is in charge of converting a DAG to only use the types
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1114 that are natively supported by the target.</p>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1115
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1116<p>There are two main ways of converting values of unsupported scalar types to
1117 values of supported types: converting small types to larger types
1118 ("promoting"), and breaking up large integer types into smaller ones
1119 ("expanding"). For example, a target might require that all f32 values are
1120 promoted to f64 and that all i1/i8/i16 values are promoted to i32. The same
1121 target might require that all i64 values be expanded into pairs of i32
1122 values. These changes can insert sign and zero extensions as needed to make
1123 sure that the final code has the same behavior as the input.</p>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1124
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1125<p>There are two main ways of converting values of unsupported vector types to
1126 value of supported types: splitting vector types, multiple times if
1127 necessary, until a legal type is found, and extending vector types by adding
1128 elements to the end to round them out to legal types ("widening"). If a
1129 vector gets split all the way down to single-element parts with no supported
1130 vector type being found, the elements are converted to scalars
1131 ("scalarizing").</p>
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1132
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1133<p>A target implementation tells the legalizer which types are supported (and
1134 which register class to use for them) by calling the
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1135 <tt>addRegisterClass</tt> method in its TargetLowering constructor.</p>
1136
1137</div>
1138
1139<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1140<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1141 <a name="selectiondag_legalize">SelectionDAG Legalize Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1142</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1143
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1144<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1145
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1146<p>The Legalize phase is in charge of converting a DAG to only use the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1147 operations that are natively supported by the target.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1148
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1149<p>Targets often have weird constraints, such as not supporting every operation
1150 on every supported datatype (e.g. X86 does not support byte conditional moves
1151 and PowerPC does not support sign-extending loads from a 16-bit memory
1152 location). Legalize takes care of this by open-coding another sequence of
1153 operations to emulate the operation ("expansion"), by promoting one type to a
1154 larger type that supports the operation ("promotion"), or by using a
1155 target-specific hook to implement the legalization ("custom").</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1156
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1157<p>A target implementation tells the legalizer which operations are not
1158 supported (and which of the above three actions to take) by calling the
1159 <tt>setOperationAction</tt> method in its <tt>TargetLowering</tt>
1160 constructor.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1161
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]1162<p>Prior to the existence of the Legalize passes, we required that every target
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1163 <a href="#selectiondag_optimize">selector</a> supported and handled every
1164 operator and type even if they are not natively supported. The introduction
1165 of the Legalize phases allows all of the canonicalization patterns to be
1166 shared across targets, and makes it very easy to optimize the canonicalized
1167 code because it is still in the form of a DAG.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1168
1169</div>
1170
1171<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1172<h4>
1173 <a name="selectiondag_optimize">
1174 SelectionDAG Optimization Phase: the DAG Combiner
1175 </a>
1176</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1177
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1178<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1179
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1180<p>The SelectionDAG optimization phase is run multiple times for code
1181 generation, immediately after the DAG is built and once after each
1182 legalization. The first run of the pass allows the initial code to be
1183 cleaned up (e.g. performing optimizations that depend on knowing that the
1184 operators have restricted type inputs). Subsequent runs of the pass clean up
1185 the messy code generated by the Legalize passes, which allows Legalize to be
1186 very simple (it can focus on making code legal instead of focusing on
1187 generating <em>good</em> and legal code).</p>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1188
1189<p>One important class of optimizations performed is optimizing inserted sign
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1190 and zero extension instructions. We currently use ad-hoc techniques, but
1191 could move to more rigorous techniques in the future. Here are some good
1192 papers on the subject:</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1193
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1194<p>"<a href="http://www.eecs.harvard.edu/~nr/pubs/widen-abstract.html">Widening
1195 integer arithmetic</a>"<br>
1196 Kevin Redwine and Norman Ramsey<br>
1197 International Conference on Compiler Construction (CC) 2004</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1198
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1199<p>"<a href="http://portal.acm.org/citation.cfm?doid=512529.512552">Effective
1200 sign extension elimination</a>"<br>
1201 Motohiro Kawahito, Hideaki Komatsu, and Toshio Nakatani<br>
1202 Proceedings of the ACM SIGPLAN 2002 Conference on Programming Language Design
1203 and Implementation.</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1204
1205</div>
1206
1207<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1208<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1209 <a name="selectiondag_select">SelectionDAG Select Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1210</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1211
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1212<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1213
1214<p>The Select phase is the bulk of the target-specific code for instruction
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1215 selection. This phase takes a legal SelectionDAG as input, pattern matches
1216 the instructions supported by the target to this DAG, and produces a new DAG
1217 of target code. For example, consider the following LLVM fragment:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1218
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1219<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1220<pre>
Dan Gohman6f34abd2010-03-02 01:11:08 +0000[diff] [blame]1221%t1 = fadd float %W, %X
1222%t2 = fmul float %t1, %Y
1223%t3 = fadd float %t2, %Z
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1224</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1225</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1226
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1227<p>This LLVM code corresponds to a SelectionDAG that looks basically like
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1228 this:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1229
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1230<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1231<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1232(fadd:f32 (fmul:f32 (fadd:f32 W, X), Y), Z)
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1233</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1234</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1235
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1236<p>If a target supports floating point multiply-and-add (FMA) operations, one of
1237 the adds can be merged with the multiply. On the PowerPC, for example, the
1238 output of the instruction selector might look like this DAG:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1239
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1240<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1241<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1242(FMADDS (FADDS W, X), Y, Z)
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1243</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1244</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1245
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1246<p>The <tt>FMADDS</tt> instruction is a ternary instruction that multiplies its
1247first two operands and adds the third (as single-precision floating-point
1248numbers). The <tt>FADDS</tt> instruction is a simple binary single-precision
1249add instruction. To perform this pattern match, the PowerPC backend includes
1250the following instruction definitions:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1251
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1252<div class="doc_code">
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1253<pre>
1254def FMADDS : AForm_1&lt;59, 29,
1255 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRC, F4RC:$FRB),
1256 "fmadds $FRT, $FRA, $FRC, $FRB",
1257 [<b>(set F4RC:$FRT, (fadd (fmul F4RC:$FRA, F4RC:$FRC),
1258 F4RC:$FRB))</b>]&gt;;
1259def FADDS : AForm_2&lt;59, 21,
1260 (ops F4RC:$FRT, F4RC:$FRA, F4RC:$FRB),
1261 "fadds $FRT, $FRA, $FRB",
1262 [<b>(set F4RC:$FRT, (fadd F4RC:$FRA, F4RC:$FRB))</b>]&gt;;
1263</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1264</div>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1265
1266<p>The portion of the instruction definition in bold indicates the pattern used
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1267 to match the instruction. The DAG operators
1268 (like <tt>fmul</tt>/<tt>fadd</tt>) are defined in
Dan Gohman2a020352010-03-25 00:03:04 +0000[diff] [blame]1269 the <tt>include/llvm/Target/TargetSelectionDAG.td</tt> file. "
1270 <tt>F4RC</tt>" is the register class of the input and result values.</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1271
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1272<p>The TableGen DAG instruction selector generator reads the instruction
1273 patterns in the <tt>.td</tt> file and automatically builds parts of the
1274 pattern matching code for your target. It has the following strengths:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1275
1276<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1277 <li>At compiler-compiler time, it analyzes your instruction patterns and tells
1278 you if your patterns make sense or not.</li>
1279
1280 <li>It can handle arbitrary constraints on operands for the pattern match. In
1281 particular, it is straight-forward to say things like "match any immediate
1282 that is a 13-bit sign-extended value". For examples, see the
1283 <tt>immSExt16</tt> and related <tt>tblgen</tt> classes in the PowerPC
1284 backend.</li>
1285
1286 <li>It knows several important identities for the patterns defined. For
1287 example, it knows that addition is commutative, so it allows the
1288 <tt>FMADDS</tt> pattern above to match "<tt>(fadd X, (fmul Y, Z))</tt>" as
1289 well as "<tt>(fadd (fmul X, Y), Z)</tt>", without the target author having
1290 to specially handle this case.</li>
1291
1292 <li>It has a full-featured type-inferencing system. In particular, you should
1293 rarely have to explicitly tell the system what type parts of your patterns
1294 are. In the <tt>FMADDS</tt> case above, we didn't have to tell
1295 <tt>tblgen</tt> that all of the nodes in the pattern are of type 'f32'.
1296 It was able to infer and propagate this knowledge from the fact that
1297 <tt>F4RC</tt> has type 'f32'.</li>
1298
1299 <li>Targets can define their own (and rely on built-in) "pattern fragments".
1300 Pattern fragments are chunks of reusable patterns that get inlined into
1301 your patterns during compiler-compiler time. For example, the integer
1302 "<tt>(not x)</tt>" operation is actually defined as a pattern fragment
1303 that expands as "<tt>(xor x, -1)</tt>", since the SelectionDAG does not
1304 have a native '<tt>not</tt>' operation. Targets can define their own
1305 short-hand fragments as they see fit. See the definition of
1306 '<tt>not</tt>' and '<tt>ineg</tt>' for examples.</li>
1307
1308 <li>In addition to instructions, targets can specify arbitrary patterns that
1309 map to one or more instructions using the 'Pat' class. For example, the
1310 PowerPC has no way to load an arbitrary integer immediate into a register
1311 in one instruction. To tell tblgen how to do this, it defines:
1312 <br>
1313 <br>
1314<div class="doc_code">
1315<pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1316// Arbitrary immediate support. Implement in terms of LIS/ORI.
1317def : Pat&lt;(i32 imm:$imm),
1318 (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm))&gt;;
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1319</pre>
1320</div>
1321 <br>
1322 If none of the single-instruction patterns for loading an immediate into a
1323 register match, this will be used. This rule says "match an arbitrary i32
1324 immediate, turning it into an <tt>ORI</tt> ('or a 16-bit immediate') and
1325 an <tt>LIS</tt> ('load 16-bit immediate, where the immediate is shifted to
1326 the left 16 bits') instruction". To make this work, the
1327 <tt>LO16</tt>/<tt>HI16</tt> node transformations are used to manipulate
1328 the input immediate (in this case, take the high or low 16-bits of the
1329 immediate).</li>
1330
1331 <li>While the system does automate a lot, it still allows you to write custom
1332 C++ code to match special cases if there is something that is hard to
1333 express.</li>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1334</ul>
1335
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]1336<p>While it has many strengths, the system currently has some limitations,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1337 primarily because it is a work in progress and is not yet finished:</p>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1338
1339<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1340 <li>Overall, there is no way to define or match SelectionDAG nodes that define
Dan Gohmana4fea5b2009-04-22 15:55:31 +0000[diff] [blame]1341 multiple values (e.g. <tt>SMUL_LOHI</tt>, <tt>LOAD</tt>, <tt>CALL</tt>,
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1342 etc). This is the biggest reason that you currently still <em>have
1343 to</em> write custom C++ code for your instruction selector.</li>
1344
1345 <li>There is no great way to support matching complex addressing modes yet.
1346 In the future, we will extend pattern fragments to allow them to define
1347 multiple values (e.g. the four operands of the <a href="#x86_memory">X86
1348 addressing mode</a>, which are currently matched with custom C++ code).
1349 In addition, we'll extend fragments so that a fragment can match multiple
1350 different patterns.</li>
1351
1352 <li>We don't automatically infer flags like isStore/isLoad yet.</li>
1353
1354 <li>We don't automatically generate the set of supported registers and
1355 operations for the <a href="#selectiondag_legalize">Legalizer</a>
1356 yet.</li>
1357
1358 <li>We don't have a way of tying in custom legalized nodes yet.</li>
Chris Lattner721f3ce2005-10-17 04:18:41 +0000[diff] [blame]1359</ul>
Chris Lattner17acad62005-10-16 20:02:19 +0000[diff] [blame]1360
1361<p>Despite these limitations, the instruction selector generator is still quite
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1362 useful for most of the binary and logical operations in typical instruction
1363 sets. If you run into any problems or can't figure out how to do something,
1364 please let Chris know!</p>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1365
1366</div>
1367
1368<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1369<h4>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]1370 <a name="selectiondag_sched">SelectionDAG Scheduling and Formation Phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1371</h4>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1372
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1373<div>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1374
1375<p>The scheduling phase takes the DAG of target instructions from the selection
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1376 phase and assigns an order. The scheduler can pick an order depending on
1377 various constraints of the machines (i.e. order for minimal register pressure
1378 or try to cover instruction latencies). Once an order is established, the
1379 DAG is converted to a list
1380 of <tt><a href="#machineinstr">MachineInstr</a></tt>s and the SelectionDAG is
1381 destroyed.</p>
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1382
Jeff Cohendd24d7c2005-10-24 16:54:55 +0000[diff] [blame]1383<p>Note that this phase is logically separate from the instruction selection
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1384 phase, but is tied to it closely in the code because it operates on
1385 SelectionDAGs.</p>
Chris Lattner9fcf0002005-10-17 03:09:31 +0000[diff] [blame]1386
Chris Lattneracf3d622005-10-16 00:36:38 +0000[diff] [blame]1387</div>
1388
1389<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1390<h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1391 <a name="selectiondag_future">Future directions for the SelectionDAG</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1392</h4>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1393
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1394<div>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1395
1396<ol>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1397 <li>Optional function-at-a-time selection.</li>
1398
1399 <li>Auto-generate entire selector from <tt>.td</tt> file.</li>
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]1400</ol>
1401
1402</div>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1403
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1404</div>
1405
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1406<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1407<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1408 <a name="ssamco">SSA-based Machine Code Optimizations</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1409</h3>
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1410<div><p>To Be Written</p></div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1411
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1412<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1413<h3>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1414 <a name="liveintervals">Live Intervals</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1415</h3>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1416
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1417<div>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1418
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1419<p>Live Intervals are the ranges (intervals) where a variable is <i>live</i>.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1420 They are used by some <a href="#regalloc">register allocator</a> passes to
1421 determine if two or more virtual registers which require the same physical
1422 register are live at the same point in the program (i.e., they conflict).
1423 When this situation occurs, one virtual register must be <i>spilled</i>.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1424
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1425<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1426<h4>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1427 <a name="livevariable_analysis">Live Variable Analysis</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1428</h4>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1429
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1430<div>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1431
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1432<p>The first step in determining the live intervals of variables is to calculate
1433 the set of registers that are immediately dead after the instruction (i.e.,
1434 the instruction calculates the value, but it is never used) and the set of
1435 registers that are used by the instruction, but are never used after the
1436 instruction (i.e., they are killed). Live variable information is computed
1437 for each <i>virtual</i> register and <i>register allocatable</i> physical
1438 register in the function. This is done in a very efficient manner because it
1439 uses SSA to sparsely compute lifetime information for virtual registers
1440 (which are in SSA form) and only has to track physical registers within a
1441 block. Before register allocation, LLVM can assume that physical registers
1442 are only live within a single basic block. This allows it to do a single,
1443 local analysis to resolve physical register lifetimes within each basic
1444 block. If a physical register is not register allocatable (e.g., a stack
1445 pointer or condition codes), it is not tracked.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1446
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1447<p>Physical registers may be live in to or out of a function. Live in values are
1448 typically arguments in registers. Live out values are typically return values
1449 in registers. Live in values are marked as such, and are given a dummy
1450 "defining" instruction during live intervals analysis. If the last basic
1451 block of a function is a <tt>return</tt>, then it's marked as using all live
1452 out values in the function.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1453
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1454<p><tt>PHI</tt> nodes need to be handled specially, because the calculation of
1455 the live variable information from a depth first traversal of the CFG of the
1456 function won't guarantee that a virtual register used by the <tt>PHI</tt>
1457 node is defined before it's used. When a <tt>PHI</tt> node is encountered,
1458 only the definition is handled, because the uses will be handled in other
1459 basic blocks.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1460
1461<p>For each <tt>PHI</tt> node of the current basic block, we simulate an
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1462 assignment at the end of the current basic block and traverse the successor
1463 basic blocks. If a successor basic block has a <tt>PHI</tt> node and one of
1464 the <tt>PHI</tt> node's operands is coming from the current basic block, then
1465 the variable is marked as <i>alive</i> within the current basic block and all
1466 of its predecessor basic blocks, until the basic block with the defining
1467 instruction is encountered.</p>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1468
1469</div>
1470
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1471<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1472<h4>
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1473 <a name="liveintervals_analysis">Live Intervals Analysis</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1474</h4>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1475
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1476<div>
Bill Wendling34ab0672006-10-11 06:30:10 +0000[diff] [blame]1477
Bill Wendlingf21825f2006-10-11 18:00:22 +0000[diff] [blame]1478<p>We now have the information available to perform the live intervals analysis
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1479 and build the live intervals themselves. We start off by numbering the basic
1480 blocks and machine instructions. We then handle the "live-in" values. These
1481 are in physical registers, so the physical register is assumed to be killed
1482 by the end of the basic block. Live intervals for virtual registers are
1483 computed for some ordering of the machine instructions <tt>[1, N]</tt>. A
1484 live interval is an interval <tt>[i, j)</tt>, where <tt>1 &lt;= i &lt;= j
1485 &lt; N</tt>, for which a variable is live.</p>
Bill Wendling34ab0672006-10-11 06:30:10 +0000[diff] [blame]1486
Bill Wendlingf21825f2006-10-11 18:00:22 +0000[diff] [blame]1487<p><i><b>More to come...</b></i></p>
1488
Bill Wendlingd495bd02006-09-06 18:42:41 +0000[diff] [blame]1489</div>
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1490
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1491</div>
1492
Bill Wendlingbb902cf2006-09-04 23:35:52 +0000[diff] [blame]1493<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1494<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1495 <a name="regalloc">Register Allocation</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1496</h3>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1497
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1498<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1499
Bill Wendling34ab0672006-10-11 06:30:10 +0000[diff] [blame]1500<p>The <i>Register Allocation problem</i> consists in mapping a program
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1501 <i>P<sub>v</sub></i>, that can use an unbounded number of virtual registers,
1502 to a program <i>P<sub>p</sub></i> that contains a finite (possibly small)
1503 number of physical registers. Each target architecture has a different number
1504 of physical registers. If the number of physical registers is not enough to
1505 accommodate all the virtual registers, some of them will have to be mapped
1506 into memory. These virtuals are called <i>spilled virtuals</i>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1507
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1508<!-- _______________________________________________________________________ -->
1509
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1510<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1511 <a name="regAlloc_represent">How registers are represented in LLVM</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1512</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1513
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1514<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1515
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1516<p>In LLVM, physical registers are denoted by integer numbers that normally
1517 range from 1 to 1023. To see how this numbering is defined for a particular
1518 architecture, you can read the <tt>GenRegisterNames.inc</tt> file for that
1519 architecture. For instance, by
1520 inspecting <tt>lib/Target/X86/X86GenRegisterNames.inc</tt> we see that the
1521 32-bit register <tt>EAX</tt> is denoted by 15, and the MMX register
1522 <tt>MM0</tt> is mapped to 48.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1523
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1524<p>Some architectures contain registers that share the same physical location. A
1525 notable example is the X86 platform. For instance, in the X86 architecture,
1526 the registers <tt>EAX</tt>, <tt>AX</tt> and <tt>AL</tt> share the first eight
1527 bits. These physical registers are marked as <i>aliased</i> in LLVM. Given a
1528 particular architecture, you can check which registers are aliased by
1529 inspecting its <tt>RegisterInfo.td</tt> file. Moreover, the method
1530 <tt>TargetRegisterInfo::getAliasSet(p_reg)</tt> returns an array containing
1531 all the physical registers aliased to the register <tt>p_reg</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1532
1533<p>Physical registers, in LLVM, are grouped in <i>Register Classes</i>.
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1534 Elements in the same register class are functionally equivalent, and can be
1535 interchangeably used. Each virtual register can only be mapped to physical
1536 registers of a particular class. For instance, in the X86 architecture, some
1537 virtuals can only be allocated to 8 bit registers. A register class is
1538 described by <tt>TargetRegisterClass</tt> objects. To discover if a virtual
1539 register is compatible with a given physical, this code can be used:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1540
1541<div class="doc_code">
1542<pre>
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]1543bool RegMapping_Fer::compatible_class(MachineFunction &amp;mf,
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1544 unsigned v_reg,
1545 unsigned p_reg) {
Dan Gohman3a4be0f2008-02-10 18:45:23 +0000[diff] [blame]1546 assert(TargetRegisterInfo::isPhysicalRegister(p_reg) &amp;&amp;
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1547 "Target register must be physical");
Chris Lattner21ec2b42007-12-31 04:16:08 +0000[diff] [blame]1548 const TargetRegisterClass *trc = mf.getRegInfo().getRegClass(v_reg);
1549 return trc-&gt;contains(p_reg);
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1550}
1551</pre>
1552</div>
1553
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1554<p>Sometimes, mostly for debugging purposes, it is useful to change the number
1555 of physical registers available in the target architecture. This must be done
1556 statically, inside the <tt>TargetRegsterInfo.td</tt> file. Just <tt>grep</tt>
1557 for <tt>RegisterClass</tt>, the last parameter of which is a list of
1558 registers. Just commenting some out is one simple way to avoid them being
1559 used. A more polite way is to explicitly exclude some registers from
Dan Gohman17151152009-07-24 00:30:09 +0000[diff] [blame]1560 the <i>allocation order</i>. See the definition of the <tt>GR8</tt> register
1561 class in <tt>lib/Target/X86/X86RegisterInfo.td</tt> for an example of this.
1562 </p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1563
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1564<p>Virtual registers are also denoted by integer numbers. Contrary to physical
Jakob Stoklund Olesend3438eb2011-01-08 23:10:59 +0000[diff] [blame]1565 registers, different virtual registers never share the same number. Whereas
1566 physical registers are statically defined in a <tt>TargetRegisterInfo.td</tt>
1567 file and cannot be created by the application developer, that is not the case
1568 with virtual registers. In order to create new virtual registers, use the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1569 method <tt>MachineRegisterInfo::createVirtualRegister()</tt>. This method
Jakob Stoklund Olesend3438eb2011-01-08 23:10:59 +0000[diff] [blame]1570 will return a new virtual register. Use an <tt>IndexedMap&lt;Foo,
1571 VirtReg2IndexFunctor&gt;</tt> to hold information per virtual register. If you
1572 need to enumerate all virtual registers, use the function
1573 <tt>TargetRegisterInfo::index2VirtReg()</tt> to find the virtual register
1574 numbers:</p>
1575
1576<div class="doc_code">
1577<pre>
1578 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) {
1579 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
1580 stuff(VirtReg);
1581 }
1582</pre>
1583</div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1584
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1585<p>Before register allocation, the operands of an instruction are mostly virtual
1586 registers, although physical registers may also be used. In order to check if
1587 a given machine operand is a register, use the boolean
1588 function <tt>MachineOperand::isRegister()</tt>. To obtain the integer code of
1589 a register, use <tt>MachineOperand::getReg()</tt>. An instruction may define
1590 or use a register. For instance, <tt>ADD reg:1026 := reg:1025 reg:1024</tt>
1591 defines the registers 1024, and uses registers 1025 and 1026. Given a
1592 register operand, the method <tt>MachineOperand::isUse()</tt> informs if that
1593 register is being used by the instruction. The
1594 method <tt>MachineOperand::isDef()</tt> informs if that registers is being
1595 defined.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1596
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1597<p>We will call physical registers present in the LLVM bitcode before register
1598 allocation <i>pre-colored registers</i>. Pre-colored registers are used in
1599 many different situations, for instance, to pass parameters of functions
1600 calls, and to store results of particular instructions. There are two types
1601 of pre-colored registers: the ones <i>implicitly</i> defined, and
1602 those <i>explicitly</i> defined. Explicitly defined registers are normal
1603 operands, and can be accessed
1604 with <tt>MachineInstr::getOperand(int)::getReg()</tt>. In order to check
1605 which registers are implicitly defined by an instruction, use
1606 the <tt>TargetInstrInfo::get(opcode)::ImplicitDefs</tt>,
1607 where <tt>opcode</tt> is the opcode of the target instruction. One important
1608 difference between explicit and implicit physical registers is that the
1609 latter are defined statically for each instruction, whereas the former may
1610 vary depending on the program being compiled. For example, an instruction
1611 that represents a function call will always implicitly define or use the same
1612 set of physical registers. To read the registers implicitly used by an
1613 instruction,
1614 use <tt>TargetInstrInfo::get(opcode)::ImplicitUses</tt>. Pre-colored
1615 registers impose constraints on any register allocation algorithm. The
Bob Wilson35e856a2010-04-09 18:39:54 +0000[diff] [blame]1616 register allocator must make sure that none of them are overwritten by
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1617 the values of virtual registers while still alive.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1618
1619</div>
1620
1621<!-- _______________________________________________________________________ -->
1622
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1623<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1624 <a name="regAlloc_howTo">Mapping virtual registers to physical registers</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1625</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1626
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1627<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1628
1629<p>There are two ways to map virtual registers to physical registers (or to
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1630 memory slots). The first way, that we will call <i>direct mapping</i>, is
1631 based on the use of methods of the classes <tt>TargetRegisterInfo</tt>,
1632 and <tt>MachineOperand</tt>. The second way, that we will call <i>indirect
1633 mapping</i>, relies on the <tt>VirtRegMap</tt> class in order to insert loads
1634 and stores sending and getting values to and from memory.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1635
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1636<p>The direct mapping provides more flexibility to the developer of the register
1637 allocator; however, it is more error prone, and demands more implementation
1638 work. Basically, the programmer will have to specify where load and store
1639 instructions should be inserted in the target function being compiled in
1640 order to get and store values in memory. To assign a physical register to a
1641 virtual register present in a given operand,
1642 use <tt>MachineOperand::setReg(p_reg)</tt>. To insert a store instruction,
Jakob Stoklund Olesen94e90b92010-08-31 22:01:07 +0000[diff] [blame]1643 use <tt>TargetInstrInfo::storeRegToStackSlot(...)</tt>, and to insert a
1644 load instruction, use <tt>TargetInstrInfo::loadRegFromStackSlot</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1645
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1646<p>The indirect mapping shields the application developer from the complexities
1647 of inserting load and store instructions. In order to map a virtual register
1648 to a physical one, use <tt>VirtRegMap::assignVirt2Phys(vreg, preg)</tt>. In
1649 order to map a certain virtual register to memory,
1650 use <tt>VirtRegMap::assignVirt2StackSlot(vreg)</tt>. This method will return
1651 the stack slot where <tt>vreg</tt>'s value will be located. If it is
1652 necessary to map another virtual register to the same stack slot,
1653 use <tt>VirtRegMap::assignVirt2StackSlot(vreg, stack_location)</tt>. One
1654 important point to consider when using the indirect mapping, is that even if
1655 a virtual register is mapped to memory, it still needs to be mapped to a
1656 physical register. This physical register is the location where the virtual
1657 register is supposed to be found before being stored or after being
1658 reloaded.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1659
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1660<p>If the indirect strategy is used, after all the virtual registers have been
1661 mapped to physical registers or stack slots, it is necessary to use a spiller
1662 object to place load and store instructions in the code. Every virtual that
1663 has been mapped to a stack slot will be stored to memory after been defined
1664 and will be loaded before being used. The implementation of the spiller tries
1665 to recycle load/store instructions, avoiding unnecessary instructions. For an
1666 example of how to invoke the spiller,
1667 see <tt>RegAllocLinearScan::runOnMachineFunction</tt>
1668 in <tt>lib/CodeGen/RegAllocLinearScan.cpp</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1669
1670</div>
1671
1672<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1673<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1674 <a name="regAlloc_twoAddr">Handling two address instructions</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1675</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1676
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1677<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1678
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1679<p>With very rare exceptions (e.g., function calls), the LLVM machine code
1680 instructions are three address instructions. That is, each instruction is
1681 expected to define at most one register, and to use at most two registers.
1682 However, some architectures use two address instructions. In this case, the
1683 defined register is also one of the used register. For instance, an
1684 instruction such as <tt>ADD %EAX, %EBX</tt>, in X86 is actually equivalent
1685 to <tt>%EAX = %EAX + %EBX</tt>.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1686
1687<p>In order to produce correct code, LLVM must convert three address
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1688 instructions that represent two address instructions into true two address
1689 instructions. LLVM provides the pass <tt>TwoAddressInstructionPass</tt> for
1690 this specific purpose. It must be run before register allocation takes
1691 place. After its execution, the resulting code may no longer be in SSA
1692 form. This happens, for instance, in situations where an instruction such
1693 as <tt>%a = ADD %b %c</tt> is converted to two instructions such as:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1694
1695<div class="doc_code">
1696<pre>
1697%a = MOVE %b
Dan Gohman01cd2d92008-06-13 17:55:57 +0000[diff] [blame]1698%a = ADD %a %c
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1699</pre>
1700</div>
1701
1702<p>Notice that, internally, the second instruction is represented as
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1703 <tt>ADD %a[def/use] %c</tt>. I.e., the register operand <tt>%a</tt> is both
1704 used and defined by the instruction.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1705
1706</div>
1707
1708<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1709<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1710 <a name="regAlloc_ssaDecon">The SSA deconstruction phase</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1711</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1712
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1713<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1714
1715<p>An important transformation that happens during register allocation is called
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1716 the <i>SSA Deconstruction Phase</i>. The SSA form simplifies many analyses
1717 that are performed on the control flow graph of programs. However,
1718 traditional instruction sets do not implement PHI instructions. Thus, in
1719 order to generate executable code, compilers must replace PHI instructions
1720 with other instructions that preserve their semantics.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1721
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1722<p>There are many ways in which PHI instructions can safely be removed from the
1723 target code. The most traditional PHI deconstruction algorithm replaces PHI
1724 instructions with copy instructions. That is the strategy adopted by
1725 LLVM. The SSA deconstruction algorithm is implemented
1726 in <tt>lib/CodeGen/PHIElimination.cpp</tt>. In order to invoke this pass, the
1727 identifier <tt>PHIEliminationID</tt> must be marked as required in the code
1728 of the register allocator.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1729
1730</div>
1731
1732<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1733<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1734 <a name="regAlloc_fold">Instruction folding</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1735</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1736
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1737<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1738
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1739<p><i>Instruction folding</i> is an optimization performed during register
1740 allocation that removes unnecessary copy instructions. For instance, a
1741 sequence of instructions such as:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1742
1743<div class="doc_code">
1744<pre>
1745%EBX = LOAD %mem_address
1746%EAX = COPY %EBX
1747</pre>
1748</div>
1749
Dan Gohman970a5472008-11-24 16:35:31 +0000[diff] [blame]1750<p>can be safely substituted by the single instruction:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1751
1752<div class="doc_code">
1753<pre>
1754%EAX = LOAD %mem_address
1755</pre>
1756</div>
1757
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1758<p>Instructions can be folded with
1759 the <tt>TargetRegisterInfo::foldMemoryOperand(...)</tt> method. Care must be
1760 taken when folding instructions; a folded instruction can be quite different
1761 from the original
1762 instruction. See <tt>LiveIntervals::addIntervalsForSpills</tt>
1763 in <tt>lib/CodeGen/LiveIntervalAnalysis.cpp</tt> for an example of its
1764 use.</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1765
1766</div>
1767
1768<!-- _______________________________________________________________________ -->
1769
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1770<h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1771 <a name="regAlloc_builtIn">Built in register allocators</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1772</h4>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1773
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1774<div>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1775
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1776<p>The LLVM infrastructure provides the application developer with three
1777 different register allocators:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1778
1779<ul>
Jakob Stoklund Olesenec2e9642010-06-15 21:58:33 +0000[diff] [blame]1780 <li><i>Fast</i> &mdash; This register allocator is the default for debug
1781 builds. It allocates registers on a basic block level, attempting to keep
1782 values in registers and reusing registers as appropriate.</li>
1783
Andrew Tricke69a1952011-07-26 18:31:49 +0000[diff] [blame]1784 <li><i>Basic</i> &mdash; This is an incremental approach to register
1785 allocation. Live ranges are assigned to registers one at a time in
1786 an order that is driven by heuristics. Since code can be rewritten
1787 on-the-fly during allocation, this framework allows interesting
1788 allocators to be developed as extensions. It is not itself a
1789 production register allocator but is a potentially useful
1790 stand-alone mode for triaging bugs and as a performance baseline.
1791
1792 <li><i>Greedy</i> &mdash; <i>The default allocator</i>. This is a
1793 highly tuned implementation of the <i>Basic</i> allocator that
1794 incorporates global live range splitting. This allocator works hard
1795 to minimize the cost of spill code.
1796
Jakob Stoklund Olesenec2e9642010-06-15 21:58:33 +0000[diff] [blame]1797 <li><i>PBQP</i> &mdash; A Partitioned Boolean Quadratic Programming (PBQP)
1798 based register allocator. This allocator works by constructing a PBQP
1799 problem representing the register allocation problem under consideration,
1800 solving this using a PBQP solver, and mapping the solution back to a
1801 register assignment.</li>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1802</ul>
1803
1804<p>The type of register allocator used in <tt>llc</tt> can be chosen with the
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]1805 command line option <tt>-regalloc=...</tt>:</p>
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1806
1807<div class="doc_code">
1808<pre>
Dan Gohmandd121d52009-08-25 15:54:01 +0000[diff] [blame]1809$ llc -regalloc=linearscan file.bc -o ln.s;
Jakob Stoklund Olesenec2e9642010-06-15 21:58:33 +0000[diff] [blame]1810$ llc -regalloc=fast file.bc -o fa.s;
1811$ llc -regalloc=pbqp file.bc -o pbqp.s;
Bill Wendling00c5aec2006-09-01 21:46:00 +0000[diff] [blame]1812</pre>
1813</div>
1814
1815</div>
1816
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1817</div>
1818
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1819<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1820<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1821 <a name="proepicode">Prolog/Epilog Code Insertion</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1822</h3>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1823
NAKAMURA Takumia35cdd62011-10-31 13:04:26 +0000[diff] [blame]1824<div>
1825
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1826<!-- _______________________________________________________________________ -->
1827<h4>
1828 <a name="compact_unwind">Compact Unwind</a>
1829</h4>
1830
1831<div>
1832
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1833<p>Throwing an exception requires <em>unwinding</em> out of a function. The
1834 information on how to unwind a given function is traditionally expressed in
1835 DWARF unwind (a.k.a. frame) info. But that format was originally developed
1836 for debuggers to backtrace, and each Frame Description Entry (FDE) requires
1837 ~20-30 bytes per function. There is also the cost of mapping from an address
1838 in a function to the corresponding FDE at runtime. An alternative unwind
1839 encoding is called <em>compact unwind</em> and requires just 4-bytes per
1840 function.</p>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1841
1842<p>The compact unwind encoding is a 32-bit value, which is encoded in an
1843 architecture-specific way. It specifies which registers to restore and from
Roman Divacky2fbb48a2011-08-01 20:38:27 +0000[diff] [blame]1844 where, and how to unwind out of the function. When the linker creates a final
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1845 linked image, it will create a <code>__TEXT,__unwind_info</code>
1846 section. This section is a small and fast way for the runtime to access
1847 unwind info for any given function. If we emit compact unwind info for the
1848 function, that compact unwind info will be encoded in
1849 the <code>__TEXT,__unwind_info</code> section. If we emit DWARF unwind info,
1850 the <code>__TEXT,__unwind_info</code> section will contain the offset of the
1851 FDE in the <code>__TEXT,__eh_frame</code> section in the final linked
1852 image.</p>
1853
1854<p>For X86, there are three modes for the compact unwind encoding:</p>
1855
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1856<dl>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1857 <dt><i>Function with a Frame Pointer (<code>EBP</code> or <code>RBP</code>)</i></dt>
1858 <dd><p><code>EBP/RBP</code>-based frame, where <code>EBP/RBP</code> is pushed
1859 onto the stack immediately after the return address,
1860 then <code>ESP/RSP</code> is moved to <code>EBP/RBP</code>. Thus to
1861 unwind, <code>ESP/RSP</code> is restored with the
1862 current <code>EBP/RBP</code> value, then <code>EBP/RBP</code> is restored
1863 by popping the stack, and the return is done by popping the stack once
1864 more into the PC. All non-volatile registers that need to be restored must
1865 have been saved in a small range on the stack that
1866 starts <code>EBP-4</code> to <code>EBP-1020</code> (<code>RBP-8</code>
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1867 to <code>RBP-1020</code>). The offset (divided by 4 in 32-bit mode and 8
1868 in 64-bit mode) is encoded in bits 16-23 (mask: <code>0x00FF0000</code>).
1869 The registers saved are encoded in bits 0-14
1870 (mask: <code>0x00007FFF</code>) as five 3-bit entries from the following
1871 table:</p>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1872<table border="1" cellspacing="0">
1873 <tr>
1874 <th>Compact Number</th>
1875 <th>i386 Register</th>
1876 <th>x86-64 Regiser</th>
1877 </tr>
1878 <tr>
1879 <td>1</td>
1880 <td><code>EBX</code></td>
1881 <td><code>RBX</code></td>
1882 </tr>
1883 <tr>
1884 <td>2</td>
1885 <td><code>ECX</code></td>
1886 <td><code>R12</code></td>
1887 </tr>
1888 <tr>
1889 <td>3</td>
1890 <td><code>EDX</code></td>
1891 <td><code>R13</code></td>
1892 </tr>
1893 <tr>
1894 <td>4</td>
1895 <td><code>EDI</code></td>
1896 <td><code>R14</code></td>
1897 </tr>
1898 <tr>
1899 <td>5</td>
1900 <td><code>ESI</code></td>
1901 <td><code>R15</code></td>
1902 </tr>
1903 <tr>
1904 <td>6</td>
1905 <td><code>EBP</code></td>
1906 <td><code>RBP</code></td>
1907 </tr>
1908</table>
1909
1910</dd>
1911
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]1912 <dt><i>Frameless with a Small Constant Stack Size (<code>EBP</code>
1913 or <code>RBP</code> is not used as a frame pointer)</i></dt>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1914 <dd><p>To return, a constant (encoded in the compact unwind encoding) is added
1915 to the <code>ESP/RSP</code>. Then the return is done by popping the stack
1916 into the PC. All non-volatile registers that need to be restored must have
1917 been saved on the stack immediately after the return address. The stack
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1918 size (divided by 4 in 32-bit mode and 8 in 64-bit mode) is encoded in bits
1919 16-23 (mask: <code>0x00FF0000</code>). There is a maximum stack size of
1920 1024 bytes in 32-bit mode and 2048 in 64-bit mode. The number of registers
1921 saved is encoded in bits 9-12 (mask: <code>0x00001C00</code>). Bits 0-9
1922 (mask: <code>0x000003FF</code>) contain which registers were saved and
1923 their order. (See
1924 the <code>encodeCompactUnwindRegistersWithoutFrame()</code> function
1925 in <code>lib/Target/X86FrameLowering.cpp</code> for the encoding
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1926 algorithm.)</p></dd>
1927
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]1928 <dt><i>Frameless with a Large Constant Stack Size (<code>EBP</code>
1929 or <code>RBP</code> is not used as a frame pointer)</i></dt>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1930 <dd><p>This case is like the "Frameless with a Small Constant Stack Size"
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]1931 case, but the stack size is too large to encode in the compact unwind
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1932 encoding. Instead it requires that the function contains "<code>subl
1933 $nnnnnn, %esp</code>" in its prolog. The compact encoding contains the
Bill Wendlinge2225052011-07-25 20:25:03 +0000[diff] [blame]1934 offset to the <code>$nnnnnn</code> value in the function in bits 9-12
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1935 (mask: <code>0x00001C00</code>).</p></dd>
Bill Wendlingdd7805a2011-07-26 07:58:09 +0000[diff] [blame]1936</dl>
Bill Wendlingc7084412011-07-25 20:19:48 +0000[diff] [blame]1937
1938</div>
1939
NAKAMURA Takumia35cdd62011-10-31 13:04:26 +0000[diff] [blame]1940</div>
1941
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1942<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1943<h3>
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1944 <a name="latemco">Late Machine Code Optimizations</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1945</h3>
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1946<div><p>To Be Written</p></div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]1947
Reid Spencer4da97842005-04-24 20:56:18 +0000[diff] [blame]1948<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1949<h3>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]1950 <a name="codeemit">Code Emission</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]1951</h3>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]1952
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]1953<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]1954
1955<p>The code emission step of code generation is responsible for lowering from
1956the code generator abstractions (like <a
1957href="#machinefunction">MachineFunction</a>, <a
1958href="#machineinstr">MachineInstr</a>, etc) down
1959to the abstractions used by the MC layer (<a href="#mcinst">MCInst</a>,
1960<a href="#mcstreamer">MCStreamer</a>, etc). This is
1961done with a combination of several different classes: the (misnamed)
1962target-independent AsmPrinter class, target-specific subclasses of AsmPrinter
1963(such as SparcAsmPrinter), and the TargetLoweringObjectFile class.</p>
1964
1965<p>Since the MC layer works at the level of abstraction of object files, it
1966doesn't have a notion of functions, global variables etc. Instead, it thinks
1967about labels, directives, and instructions. A key class used at this time is
1968the MCStreamer class. This is an abstract API that is implemented in different
1969ways (e.g. to output a .s file, output an ELF .o file, etc) that is effectively
1970an "assembler API". MCStreamer has one method per directive, such as EmitLabel,
1971EmitSymbolAttribute, SwitchSection, etc, which directly correspond to assembly
1972level directives.
1973</p>
1974
1975<p>If you are interested in implementing a code generator for a target, there
1976are three important things that you have to implement for your target:</p>
1977
1978<ol>
1979<li>First, you need a subclass of AsmPrinter for your target. This class
1980implements the general lowering process converting MachineFunction's into MC
1981label constructs. The AsmPrinter base class provides a number of useful methods
1982and routines, and also allows you to override the lowering process in some
1983important ways. You should get much of the lowering for free if you are
1984implementing an ELF, COFF, or MachO target, because the TargetLoweringObjectFile
1985class implements much of the common logic.</li>
1986
1987<li>Second, you need to implement an instruction printer for your target. The
1988instruction printer takes an <a href="#mcinst">MCInst</a> and renders it to a
1989raw_ostream as text. Most of this is automatically generated from the .td file
1990(when you specify something like "<tt>add $dst, $src1, $src2</tt>" in the
1991instructions), but you need to implement routines to print operands.</li>
1992
1993<li>Third, you need to implement code that lowers a <a
1994href="#machineinstr">MachineInstr</a> to an MCInst, usually implemented in
1995"&lt;target&gt;MCInstLower.cpp". This lowering process is often target
1996specific, and is responsible for turning jump table entries, constant pool
1997indices, global variable addresses, etc into MCLabels as appropriate. This
1998translation layer is also responsible for expanding pseudo ops used by the code
1999generator into the actual machine instructions they correspond to. The MCInsts
2000that are generated by this are fed into the instruction printer or the encoder.
2001</li>
2002
2003</ol>
2004
2005<p>Finally, at your choosing, you can also implement an subclass of
2006MCCodeEmitter which lowers MCInst's into machine code bytes and relocations.
2007This is important if you want to support direct .o file emission, or would like
2008to implement an assembler for your target.</p>
2009
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2010</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2011
Anshuman Dasguptabcfa2f82011-12-06 23:12:42 +0000[diff] [blame]2012<!-- ======================================================================= -->
2013<h3>
2014 <a name="vliw_packetizer">VLIW Packetizer</a>
2015</h3>
2016
2017<div>
2018
2019<p>In a Very Long Instruction Word (VLIW) architecture, the compiler is
2020 responsible for mapping instructions to functional-units available on
2021 the architecture. To that end, the compiler creates groups of instructions
2022 called <i>packets</i> or <i>bundles</i>. The VLIW packetizer in LLVM is
2023 a target-independent mechanism to enable the packetization of machine
2024 instructions.</p>
2025
2026<!-- _______________________________________________________________________ -->
2027
2028<h4>
2029 <a name="vliw_mapping">Mapping from instructions to functional units</a>
2030</h4>
2031
2032<div>
2033
2034<p>Instructions in a VLIW target can typically be mapped to multiple functional
2035units. During the process of packetizing, the compiler must be able to reason
2036about whether an instruction can be added to a packet. This decision can be
2037complex since the compiler has to examine all possible mappings of instructions
2038to functional units. Therefore to alleviate compilation-time complexity, the
2039VLIW packetizer parses the instruction classes of a target and generates tables
2040at compiler build time. These tables can then be queried by the provided
2041machine-independent API to determine if an instruction can be accommodated in a
2042packet.</p>
2043</div>
2044
2045<!-- ======================================================================= -->
2046<h4>
2047 <a name="vliw_repr">
2048 How the packetization tables are generated and used
2049 </a>
2050</h4>
2051
2052<div>
2053
2054<p>The packetizer reads instruction classes from a target's itineraries and
2055creates a deterministic finite automaton (DFA) to represent the state of a
2056packet. A DFA consists of three major elements: inputs, states, and
2057transitions. The set of inputs for the generated DFA represents the instruction
2058being added to a packet. The states represent the possible consumption
2059of functional units by instructions in a packet. In the DFA, transitions from
2060one state to another occur on the addition of an instruction to an existing
2061packet. If there is a legal mapping of functional units to instructions, then
2062the DFA contains a corresponding transition. The absence of a transition
2063indicates that a legal mapping does not exist and that the instruction cannot
2064be added to the packet.</p>
2065
2066<p>To generate tables for a VLIW target, add <i>Target</i>GenDFAPacketizer.inc
2067as a target to the Makefile in the target directory. The exported API provides
2068three functions: <tt>DFAPacketizer::clearResources()</tt>,
2069<tt>DFAPacketizer::reserveResources(MachineInstr *MI)</tt>, and
2070<tt>DFAPacketizer::canReserveResources(MachineInstr *MI)</tt>. These functions
2071allow a target packetizer to add an instruction to an existing packet and to
2072check whether an instruction can be added to a packet. See
2073<tt>llvm/CodeGen/DFAPacketizer.h</tt> for more information.</p>
2074
2075</div>
2076
2077</div>
2078
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2079</div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2080
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2081<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2082<h2>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2083 <a name="nativeassembler">Implementing a Native Assembler</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2084</h2>
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2085<!-- *********************************************************************** -->
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2086
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2087<div>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2088
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2089<p>Though you're probably reading this because you want to write or maintain a
2090compiler backend, LLVM also fully supports building a native assemblers too.
2091We've tried hard to automate the generation of the assembler from the .td files
2092(in particular the instruction syntax and encodings), which means that a large
2093part of the manual and repetitive data entry can be factored and shared with the
2094compiler.</p>
2095
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2096<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2097<h3 id="na_instparsing">Instruction Parsing</h3>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2098
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2099<div><p>To Be Written</p></div>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2100
2101
2102<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2103<h3 id="na_instaliases">
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2104 Instruction Alias Processing
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2105</h3>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2106
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2107<div>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2108<p>Once the instruction is parsed, it enters the MatchInstructionImpl function.
2109The MatchInstructionImpl function performs alias processing and then does
2110actual matching.</p>
2111
Chris Lattner2cb092d2010-10-30 19:23:13 +0000[diff] [blame]2112<p>Alias processing is the phase that canonicalizes different lexical forms of
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2113the same instructions down to one representation. There are several different
2114kinds of alias that are possible to implement and they are listed below in the
2115order that they are processed (which is in order from simplest/weakest to most
2116complex/powerful). Generally you want to use the first alias mechanism that
2117meets the needs of your instruction, because it will allow a more concise
2118description.</p>
2119
2120<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2121<h4>Mnemonic Aliases</h4>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2122
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2123<div>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2124
Chris Lattnerf9ec2fb2010-10-30 19:47:49 +0000[diff] [blame]2125<p>The first phase of alias processing is simple instruction mnemonic
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2126remapping for classes of instructions which are allowed with two different
Chris Lattner2cb092d2010-10-30 19:23:13 +0000[diff] [blame]2127mnemonics. This phase is a simple and unconditionally remapping from one input
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2128mnemonic to one output mnemonic. It isn't possible for this form of alias to
2129look at the operands at all, so the remapping must apply for all forms of a
2130given mnemonic. Mnemonic aliases are defined simply, for example X86 has:
2131</p>
2132
2133<div class="doc_code">
2134<pre>
2135def : MnemonicAlias&lt;"cbw", "cbtw"&gt;;
2136def : MnemonicAlias&lt;"smovq", "movsq"&gt;;
2137def : MnemonicAlias&lt;"fldcww", "fldcw"&gt;;
2138def : MnemonicAlias&lt;"fucompi", "fucomip"&gt;;
2139def : MnemonicAlias&lt;"ud2a", "ud2"&gt;;
2140</pre>
2141</div>
2142
2143<p>... and many others. With a MnemonicAlias definition, the mnemonic is
Chris Lattner2cb092d2010-10-30 19:23:13 +0000[diff] [blame]2144remapped simply and directly. Though MnemonicAlias's can't look at any aspect
2145of the instruction (such as the operands) they can depend on global modes (the
2146same ones supported by the matcher), through a Requires clause:</p>
2147
2148<div class="doc_code">
2149<pre>
2150def : MnemonicAlias&lt;"pushf", "pushfq"&gt;, Requires&lt;[In64BitMode]&gt;;
2151def : MnemonicAlias&lt;"pushf", "pushfl"&gt;, Requires&lt;[In32BitMode]&gt;;
2152</pre>
2153</div>
2154
2155<p>In this example, the mnemonic gets mapped into different a new one depending
2156on the current instruction set.</p>
Chris Lattnercb67a142010-09-11 23:02:10 +0000[diff] [blame]2157
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2158</div>
2159
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2160<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2161<h4>Instruction Aliases</h4>
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2162
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2163<div>
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2164
2165<p>The most general phase of alias processing occurs while matching is
2166happening: it provides new forms for the matcher to match along with a specific
2167instruction to generate. An instruction alias has two parts: the string to
2168match and the instruction to generate. For example:
2169</p>
2170
2171<div class="doc_code">
2172<pre>
2173def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rr8W GR16:$dst, GR8 :$src)&gt;;
2174def : InstAlias&lt;"movsx $src, $dst", (MOVSX16rm8W GR16:$dst, i8mem:$src)&gt;;
2175def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr8 GR32:$dst, GR8 :$src)&gt;;
2176def : InstAlias&lt;"movsx $src, $dst", (MOVSX32rr16 GR32:$dst, GR16 :$src)&gt;;
2177def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr8 GR64:$dst, GR8 :$src)&gt;;
2178def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr16 GR64:$dst, GR16 :$src)&gt;;
2179def : InstAlias&lt;"movsx $src, $dst", (MOVSX64rr32 GR64:$dst, GR32 :$src)&gt;;
2180</pre>
2181</div>
2182
2183<p>This shows a powerful example of the instruction aliases, matching the
2184same mnemonic in multiple different ways depending on what operands are present
2185in the assembly. The result of instruction aliases can include operands in a
2186different order than the destination instruction, and can use an input
2187multiple times, for example:</p>
2188
2189<div class="doc_code">
2190<pre>
2191def : InstAlias&lt;"clrb $reg", (XOR8rr GR8 :$reg, GR8 :$reg)&gt;;
2192def : InstAlias&lt;"clrw $reg", (XOR16rr GR16:$reg, GR16:$reg)&gt;;
2193def : InstAlias&lt;"clrl $reg", (XOR32rr GR32:$reg, GR32:$reg)&gt;;
2194def : InstAlias&lt;"clrq $reg", (XOR64rr GR64:$reg, GR64:$reg)&gt;;
2195</pre>
2196</div>
2197
2198<p>This example also shows that tied operands are only listed once. In the X86
2199backend, XOR8rr has two input GR8's and one output GR8 (where an input is tied
2200to the output). InstAliases take a flattened operand list without duplicates
Chris Lattner4869d342010-11-06 19:57:21 +0000[diff] [blame]2201for tied operands. The result of an instruction alias can also use immediates
2202and fixed physical registers which are added as simple immediate operands in the
2203result, for example:</p>
Chris Lattnerb6f8e822010-11-06 19:25:43 +0000[diff] [blame]2204
2205<div class="doc_code">
2206<pre>
Chris Lattner4869d342010-11-06 19:57:21 +0000[diff] [blame]2207// Fixed Immediate operand.
Chris Lattnerb6f8e822010-11-06 19:25:43 +0000[diff] [blame]2208def : InstAlias&lt;"aad", (AAD8i8 10)&gt;;
Chris Lattner4869d342010-11-06 19:57:21 +0000[diff] [blame]2209
2210// Fixed register operand.
2211def : InstAlias&lt;"fcomi", (COM_FIr ST1)&gt;;
2212
2213// Simple alias.
2214def : InstAlias&lt;"fcomi $reg", (COM_FIr RST:$reg)&gt;;
Chris Lattnerb6f8e822010-11-06 19:25:43 +0000[diff] [blame]2215</pre>
2216</div>
2217
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2218
2219<p>Instruction aliases can also have a Requires clause to make them
2220subtarget specific.</p>
2221
Bill Wendling260c4a92011-05-04 23:40:14 +0000[diff] [blame]2222<p>If the back-end supports it, the instruction printer can automatically emit
2223 the alias rather than what's being aliased. It typically leads to better,
2224 more readable code. If it's better to print out what's being aliased, then
2225 pass a '0' as the third parameter to the InstAlias definition.</p>
2226
Chris Lattner8b0a71f2010-11-06 08:30:26 +0000[diff] [blame]2227</div>
2228
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2229</div>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2230
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2231<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2232<h3 id="na_matching">Instruction Matching</h3>
Chris Lattnerba7b4fe2010-10-30 17:36:36 +0000[diff] [blame]2233
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2234<div><p>To Be Written</p></div>
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2235
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2236</div>
Chris Lattner191efcf2010-09-21 04:03:39 +0000[diff] [blame]2237
Chris Lattner54903b62005-01-28 17:22:53 +0000[diff] [blame]2238<!-- *********************************************************************** -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2239<h2>
Chris Lattnerd6f1a332005-10-16 18:31:08 +0000[diff] [blame]2240 <a name="targetimpls">Target-specific Implementation Notes</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2241</h2>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2242<!-- *********************************************************************** -->
2243
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2244<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2245
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2246<p>This section of the document explains features or design decisions that are
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2247 specific to the code generator for a particular target. First we start
2248 with a table that summarizes what features are supported by each target.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2249
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2250<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2251<h3>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2252 <a name="targetfeatures">Target Feature Matrix</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2253</h3>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2254
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2255<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2256
2257<p>Note that this table does not include the C backend or Cpp backends, since
2258they do not use the target independent code generator infrastructure. It also
2259doesn't list features that are not supported fully by any target yet. It
2260considers a feature to be supported if at least one subtarget supports it. A
2261feature being supported means that it is useful and works for most cases, it
2262does not indicate that there are zero known bugs in the implementation. Here
2263is the key:</p>
2264
2265
2266<table border="1" cellspacing="0">
2267 <tr>
2268 <th>Unknown</th>
2269 <th>No support</th>
2270 <th>Partial Support</th>
2271 <th>Complete Support</th>
2272 </tr>
2273 <tr>
2274 <td class="unknown"></td>
2275 <td class="no"></td>
2276 <td class="partial"></td>
2277 <td class="yes"></td>
2278 </tr>
2279</table>
2280
2281<p>Here is the table:</p>
2282
2283<table width="689" border="1" cellspacing="0">
2284<tr><td></td>
Benjamin Kramerc940bcf2010-10-30 21:07:28 +0000[diff] [blame]2285<td colspan="13" align="center" style="background-color:#ffc">Target</td>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2286</tr>
2287 <tr>
2288 <th>Feature</th>
2289 <th>ARM</th>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2290 <th>CellSPU</th>
2291 <th>MBlaze</th>
2292 <th>MSP430</th>
2293 <th>Mips</th>
2294 <th>PTX</th>
2295 <th>PowerPC</th>
2296 <th>Sparc</th>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2297 <th>X86</th>
2298 <th>XCore</th>
2299 </tr>
2300
2301<tr>
2302 <td><a href="#feat_reliable">is generally reliable</a></td>
2303 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2304 <td class="no"></td> <!-- CellSPU -->
Wesley Peck188dead2010-10-24 18:50:12 +0000[diff] [blame]2305 <td class="no"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2306 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes4f6d7d42011-10-25 20:09:31 +0000[diff] [blame]2307 <td class="yes"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2308 <td class="no"></td> <!-- PTX -->
2309 <td class="yes"></td> <!-- PowerPC -->
2310 <td class="yes"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2311 <td class="yes"></td> <!-- X86 -->
2312 <td class="unknown"></td> <!-- XCore -->
2313</tr>
2314
2315<tr>
2316 <td><a href="#feat_asmparser">assembly parser</a></td>
2317 <td class="no"></td> <!-- ARM -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2318 <td class="no"></td> <!-- CellSPU -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2319 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2320 <td class="no"></td> <!-- MSP430 -->
2321 <td class="no"></td> <!-- Mips -->
2322 <td class="no"></td> <!-- PTX -->
2323 <td class="no"></td> <!-- PowerPC -->
2324 <td class="no"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2325 <td class="yes"></td> <!-- X86 -->
2326 <td class="no"></td> <!-- XCore -->
2327</tr>
2328
2329<tr>
2330 <td><a href="#feat_disassembler">disassembler</a></td>
2331 <td class="yes"></td> <!-- ARM -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2332 <td class="no"></td> <!-- CellSPU -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2333 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2334 <td class="no"></td> <!-- MSP430 -->
2335 <td class="no"></td> <!-- Mips -->
2336 <td class="no"></td> <!-- PTX -->
2337 <td class="no"></td> <!-- PowerPC -->
2338 <td class="no"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2339 <td class="yes"></td> <!-- X86 -->
2340 <td class="no"></td> <!-- XCore -->
2341</tr>
2342
2343<tr>
2344 <td><a href="#feat_inlineasm">inline asm</a></td>
2345 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2346 <td class="no"></td> <!-- CellSPU -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2347 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2348 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes8e303e82010-12-19 22:41:43 +0000[diff] [blame]2349 <td class="no"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2350 <td class="unknown"></td> <!-- PTX -->
2351 <td class="yes"></td> <!-- PowerPC -->
2352 <td class="unknown"></td> <!-- Sparc -->
Jakob Stoklund Olesen1c483172011-09-19 18:15:46 +0000[diff] [blame]2353 <td class="yes"></td> <!-- X86 -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2354 <td class="unknown"></td> <!-- XCore -->
2355</tr>
2356
2357<tr>
2358 <td><a href="#feat_jit">jit</a></td>
2359 <td class="partial"><a href="#feat_jit_arm">*</a></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2360 <td class="no"></td> <!-- CellSPU -->
Wesley Peck188dead2010-10-24 18:50:12 +0000[diff] [blame]2361 <td class="no"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2362 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes4f6d7d42011-10-25 20:09:31 +0000[diff] [blame]2363 <td class="yes"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2364 <td class="unknown"></td> <!-- PTX -->
2365 <td class="yes"></td> <!-- PowerPC -->
2366 <td class="unknown"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2367 <td class="yes"></td> <!-- X86 -->
2368 <td class="unknown"></td> <!-- XCore -->
2369</tr>
2370
2371<tr>
2372 <td><a href="#feat_objectwrite">.o&nbsp;file writing</a></td>
2373 <td class="no"></td> <!-- ARM -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2374 <td class="no"></td> <!-- CellSPU -->
Wesley Peck671d54d2010-12-20 21:54:50 +0000[diff] [blame]2375 <td class="yes"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2376 <td class="no"></td> <!-- MSP430 -->
2377 <td class="no"></td> <!-- Mips -->
2378 <td class="no"></td> <!-- PTX -->
2379 <td class="no"></td> <!-- PowerPC -->
2380 <td class="no"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2381 <td class="yes"></td> <!-- X86 -->
2382 <td class="no"></td> <!-- XCore -->
2383</tr>
2384
2385<tr>
2386 <td><a href="#feat_tailcall">tail calls</a></td>
2387 <td class="yes"></td> <!-- ARM -->
Kalle Raiskila829b21f2010-10-25 08:57:30 +0000[diff] [blame]2388 <td class="no"></td> <!-- CellSPU -->
Wesley Peck188dead2010-10-24 18:50:12 +0000[diff] [blame]2389 <td class="no"></td> <!-- MBlaze -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2390 <td class="unknown"></td> <!-- MSP430 -->
Bruno Cardoso Lopes8e303e82010-12-19 22:41:43 +0000[diff] [blame]2391 <td class="no"></td> <!-- Mips -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2392 <td class="unknown"></td> <!-- PTX -->
2393 <td class="yes"></td> <!-- PowerPC -->
2394 <td class="unknown"></td> <!-- Sparc -->
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2395 <td class="yes"></td> <!-- X86 -->
2396 <td class="unknown"></td> <!-- XCore -->
2397</tr>
2398
Rafael Espindola799ca892011-11-27 22:05:46 +0000[diff] [blame]2399<tr>
2400 <td><a href="#feat_segstacks">segmented stacks</a></td>
2401 <td class="no"></td> <!-- ARM -->
2402 <td class="no"></td> <!-- CellSPU -->
2403 <td class="no"></td> <!-- MBlaze -->
2404 <td class="no"></td> <!-- MSP430 -->
2405 <td class="no"></td> <!-- Mips -->
2406 <td class="no"></td> <!-- PTX -->
2407 <td class="no"></td> <!-- PowerPC -->
2408 <td class="no"></td> <!-- Sparc -->
2409 <td class="partial"><a href="#feat_segstacks_x86">*</a></td> <!-- X86 -->
2410 <td class="no"></td> <!-- XCore -->
2411</tr>
2412
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2413
2414</table>
2415
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2416<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2417<h4 id="feat_reliable">Is Generally Reliable</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2418
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2419<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2420<p>This box indicates whether the target is considered to be production quality.
2421This indicates that the target has been used as a static compiler to
2422compile large amounts of code by a variety of different people and is in
2423continuous use.</p>
2424</div>
2425
2426<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2427<h4 id="feat_asmparser">Assembly Parser</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2428
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2429<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2430<p>This box indicates whether the target supports parsing target specific .s
2431files by implementing the MCAsmParser interface. This is required for llvm-mc
2432to be able to act as a native assembler and is required for inline assembly
2433support in the native .o file writer.</p>
2434
2435</div>
2436
2437
2438<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2439<h4 id="feat_disassembler">Disassembler</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2440
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2441<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2442<p>This box indicates whether the target supports the MCDisassembler API for
2443disassembling machine opcode bytes into MCInst's.</p>
2444
2445</div>
2446
2447<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2448<h4 id="feat_inlineasm">Inline Asm</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2449
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2450<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2451<p>This box indicates whether the target supports most popular inline assembly
2452constraints and modifiers.</p>
2453
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2454</div>
2455
2456<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2457<h4 id="feat_jit">JIT Support</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2458
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2459<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2460<p>This box indicates whether the target supports the JIT compiler through
2461the ExecutionEngine interface.</p>
2462
Chris Lattner60616b12010-10-24 16:24:22 +0000[diff] [blame]2463<p id="feat_jit_arm">The ARM backend has basic support for integer code
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2464in ARM codegen mode, but lacks NEON and full Thumb support.</p>
2465
2466</div>
2467
2468<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2469<h4 id="feat_objectwrite">.o File Writing</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2470
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2471<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2472
2473<p>This box indicates whether the target supports writing .o files (e.g. MachO,
2474ELF, and/or COFF) files directly from the target. Note that the target also
2475must include an assembly parser and general inline assembly support for full
2476inline assembly support in the .o writer.</p>
2477
Chris Lattner15597532010-10-28 02:22:02 +0000[diff] [blame]2478<p>Targets that don't support this feature can obviously still write out .o
2479files, they just rely on having an external assembler to translate from a .s
2480file to a .o file (as is the case for many C compilers).</p>
2481
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2482</div>
2483
2484<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2485<h4 id="feat_tailcall">Tail Calls</h4>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2486
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2487<div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2488
2489<p>This box indicates whether the target supports guaranteed tail calls. These
2490are calls marked "<a href="LangRef.html#i_call">tail</a>" and use the fastcc
2491calling convention. Please see the <a href="#tailcallopt">tail call section
2492more more details</a>.</p>
2493
2494</div>
2495
Rafael Espindola799ca892011-11-27 22:05:46 +0000[diff] [blame]2496<!-- _______________________________________________________________________ -->
2497<h4 id="feat_segstacks">Segmented Stacks</h4>
2498
2499<div>
2500
2501<p>This box indicates whether the target supports segmented stacks. This
2502replaces the traditional large C stack with many linked segments. It
2503is compatible with the <a href="http://gcc.gnu.org/wiki/SplitStacks">gcc
2504implementation</a> used by the Go front end.</p>
2505
Rafael Espindolac87cebf2011-11-28 17:06:58 +0000[diff] [blame]2506<p id="feat_segstacks_x86">Basic support exists on the X86 backend. Currently
2507vararg doesn't work and the object files are not marked the way the gold
Rafael Espindolab61cc442011-11-29 19:38:09 +0000[diff] [blame]2508linker expects, but simple Go programs can be built by dragonegg.</p>
Rafael Espindola799ca892011-11-27 22:05:46 +0000[diff] [blame]2509
2510</div>
2511
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2512</div>
Chris Lattner5427f742010-10-24 16:18:00 +0000[diff] [blame]2513
2514<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2515<h3>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2516 <a name="tailcallopt">Tail call optimization</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2517</h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2518
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2519<div>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2520
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2521<p>Tail call optimization, callee reusing the stack of the caller, is currently
2522 supported on x86/x86-64 and PowerPC. It is performed if:</p>
2523
2524<ul>
Chris Lattnera179e4d2010-03-11 00:22:57 +0000[diff] [blame]2525 <li>Caller and callee have the calling convention <tt>fastcc</tt> or
2526 <tt>cc 10</tt> (GHC call convention).</li>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2527
2528 <li>The call is a tail call - in tail position (ret immediately follows call
2529 and ret uses value of call or is void).</li>
2530
2531 <li>Option <tt>-tailcallopt</tt> is enabled.</li>
2532
2533 <li>Platform specific constraints are met.</li>
2534</ul>
2535
2536<p>x86/x86-64 constraints:</p>
2537
2538<ul>
2539 <li>No variable argument lists are used.</li>
2540
2541 <li>On x86-64 when generating GOT/PIC code only module-local calls (visibility
2542 = hidden or protected) are supported.</li>
2543</ul>
2544
2545<p>PowerPC constraints:</p>
2546
2547<ul>
2548 <li>No variable argument lists are used.</li>
2549
2550 <li>No byval parameters are used.</li>
2551
2552 <li>On ppc32/64 GOT/PIC only module-local calls (visibility = hidden or protected) are supported.</li>
2553</ul>
2554
2555<p>Example:</p>
2556
2557<p>Call as <tt>llc -tailcallopt test.ll</tt>.</p>
2558
2559<div class="doc_code">
2560<pre>
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2561declare fastcc i32 @tailcallee(i32 inreg %a1, i32 inreg %a2, i32 %a3, i32 %a4)
2562
2563define fastcc i32 @tailcaller(i32 %in1, i32 %in2) {
2564 %l1 = add i32 %in1, %in2
2565 %tmp = tail call fastcc i32 @tailcallee(i32 %in1 inreg, i32 %in2 inreg, i32 %in1, i32 %l1)
2566 ret i32 %tmp
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2567}
2568</pre>
2569</div>
2570
2571<p>Implications of <tt>-tailcallopt</tt>:</p>
2572
2573<p>To support tail call optimization in situations where the callee has more
2574 arguments than the caller a 'callee pops arguments' convention is used. This
2575 currently causes each <tt>fastcc</tt> call that is not tail call optimized
2576 (because one or more of above constraints are not met) to be followed by a
2577 readjustment of the stack. So performance might be worse in such cases.</p>
2578
Arnold Schwaighofer2c6b8882008-05-14 09:17:12 +0000[diff] [blame]2579</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2580<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2581<h3>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]2582 <a name="sibcallopt">Sibling call optimization</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2583</h3>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]2584
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2585<div>
Evan Cheng59676492010-03-08 21:05:02 +0000[diff] [blame]2586
2587<p>Sibling call optimization is a restricted form of tail call optimization.
2588 Unlike tail call optimization described in the previous section, it can be
2589 performed automatically on any tail calls when <tt>-tailcallopt</tt> option
2590 is not specified.</p>
2591
2592<p>Sibling call optimization is currently performed on x86/x86-64 when the
2593 following constraints are met:</p>
2594
2595<ul>
2596 <li>Caller and callee have the same calling convention. It can be either
2597 <tt>c</tt> or <tt>fastcc</tt>.
2598
2599 <li>The call is a tail call - in tail position (ret immediately follows call
2600 and ret uses value of call or is void).</li>
2601
2602 <li>Caller and callee have matching return type or the callee result is not
2603 used.
2604
2605 <li>If any of the callee arguments are being passed in stack, they must be
2606 available in caller's own incoming argument stack and the frame offsets
2607 must be the same.
2608</ul>
2609
2610<p>Example:</p>
2611<div class="doc_code">
2612<pre>
2613declare i32 @bar(i32, i32)
2614
2615define i32 @foo(i32 %a, i32 %b, i32 %c) {
2616entry:
2617 %0 = tail call i32 @bar(i32 %a, i32 %b)
2618 ret i32 %0
2619}
2620</pre>
2621</div>
2622
2623</div>
2624<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2625<h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2626 <a name="x86">The X86 backend</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2627</h3>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2628
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2629<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2630
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2631<p>The X86 code generator lives in the <tt>lib/Target/X86</tt> directory. This
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2632 code generator is capable of targeting a variety of x86-32 and x86-64
2633 processors, and includes support for ISA extensions such as MMX and SSE.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2634
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2635<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2636<h4>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2637 <a name="x86_tt">X86 Target Triples supported</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2638</h4>
Chris Lattnerde69bf92005-07-12 00:20:49 +0000[diff] [blame]2639
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2640<div>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2641
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2642<p>The following are the known target triples that are supported by the X86
2643 backend. This is not an exhaustive list, and it would be useful to add those
2644 that people test.</p>
Chris Lattnerde69bf92005-07-12 00:20:49 +0000[diff] [blame]2645
2646<ul>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2647 <li><b>i686-pc-linux-gnu</b> &mdash; Linux</li>
2648
2649 <li><b>i386-unknown-freebsd5.3</b> &mdash; FreeBSD 5.3</li>
2650
2651 <li><b>i686-pc-cygwin</b> &mdash; Cygwin on Win32</li>
2652
2653 <li><b>i686-pc-mingw32</b> &mdash; MingW on Win32</li>
2654
2655 <li><b>i386-pc-mingw32msvc</b> &mdash; MingW crosscompiler on Linux</li>
2656
2657 <li><b>i686-apple-darwin*</b> &mdash; Apple Darwin on X86</li>
Torok Edwin4378bf02009-06-15 12:17:44 +0000[diff] [blame]2658
2659 <li><b>x86_64-unknown-linux-gnu</b> &mdash; Linux</li>
Chris Lattnerde69bf92005-07-12 00:20:49 +0000[diff] [blame]2660</ul>
2661
2662</div>
2663
2664<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2665<h4>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2666 <a name="x86_cc">X86 Calling Conventions supported</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2667</h4>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2668
2669
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2670<div>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2671
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]2672<p>The following target-specific calling conventions are known to backend:</p>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2673
2674<ul>
Chris Lattnerf98eade2011-05-22 22:28:47 +0000[diff] [blame]2675<li><b>x86_StdCall</b> &mdash; stdcall calling convention seen on Microsoft
2676 Windows platform (CC ID = 64).</li>
2677<li><b>x86_FastCall</b> &mdash; fastcall calling convention seen on Microsoft
2678 Windows platform (CC ID = 65).</li>
2679<li><b>x86_ThisCall</b> &mdash; Similar to X86_StdCall. Passes first argument
2680 in ECX, others via stack. Callee is responsible for stack cleaning. This
2681 convention is used by MSVC by default for methods in its ABI
2682 (CC ID = 70).</li>
Anton Korobeynikov6f7072c2006-09-17 20:25:45 +0000[diff] [blame]2683</ul>
2684
2685</div>
2686
2687<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2688<h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2689 <a name="x86_memory">Representing X86 addressing modes in MachineInstrs</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2690</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2691
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2692<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2693
Misha Brukman37036852005-02-17 22:22:24 +0000[diff] [blame]2694<p>The x86 has a very flexible way of accessing memory. It is capable of
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2695 forming memory addresses of the following expression directly in integer
2696 instructions (which use ModR/M addressing):</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2697
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2698<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2699<pre>
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2700SegmentReg: Base + [1,2,4,8] * IndexReg + Disp32
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2701</pre>
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2702</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2703
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2704<p>In order to represent this, LLVM tracks no less than 5 operands for each
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2705 memory operand of this form. This means that the "load" form of
2706 '<tt>mov</tt>' has the following <tt>MachineOperand</tt>s in this order:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2707
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2708<div class="doc_code">
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2709<pre>
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2710Index: 0 | 1 2 3 4 5
2711Meaning: DestReg, | BaseReg, Scale, IndexReg, Displacement Segment
2712OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2713</pre>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2714</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2715
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2716<p>Stores, and all other instructions, treat the four memory operands in the
Chris Lattner10a5a6f2009-10-10 21:30:55 +0000[diff] [blame]2717 same way and in the same order. If the segment register is unspecified
2718 (regno = 0), then no segment override is generated. "Lea" operations do not
2719 have a segment register specified, so they only have 4 operands for their
2720 memory reference.</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2721
2722</div>
2723
2724<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2725<h4>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2726 <a name="x86_memory">X86 address spaces supported</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2727</h4>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2728
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2729<div>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2730
Jay Foad1a7cc442011-04-06 07:55:30 +0000[diff] [blame]2731<p>x86 has a feature which provides
Dan Gohmand99feb82009-05-05 20:48:47 +0000[diff] [blame]2732 the ability to perform loads and stores to different address spaces
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2733 via the x86 segment registers. A segment override prefix byte on an
2734 instruction causes the instruction's memory access to go to the specified
2735 segment. LLVM address space 0 is the default address space, which includes
2736 the stack, and any unqualified memory accesses in a program. Address spaces
2737 1-255 are currently reserved for user-defined code. The GS-segment is
Chris Lattnerbe9fa502009-05-05 18:52:19 +0000[diff] [blame]2738 represented by address space 256, while the FS-segment is represented by
2739 address space 257. Other x86 segments have yet to be allocated address space
2740 numbers.</p>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2741
Dan Gohmand99feb82009-05-05 20:48:47 +0000[diff] [blame]2742<p>While these address spaces may seem similar to TLS via the
2743 <tt>thread_local</tt> keyword, and often use the same underlying hardware,
2744 there are some fundamental differences.</p>
2745
2746<p>The <tt>thread_local</tt> keyword applies to global variables and
2747 specifies that they are to be allocated in thread-local memory. There are
2748 no type qualifiers involved, and these variables can be pointed to with
2749 normal pointers and accessed with normal loads and stores.
2750 The <tt>thread_local</tt> keyword is target-independent at the LLVM IR
2751 level (though LLVM doesn't yet have implementations of it for some
2752 configurations).<p>
2753
2754<p>Special address spaces, in contrast, apply to static types. Every
2755 load and store has a particular address space in its address operand type,
2756 and this is what determines which address space is accessed.
2757 LLVM ignores these special address space qualifiers on global variables,
2758 and does not provide a way to directly allocate storage in them.
2759 At the LLVM IR level, the behavior of these special address spaces depends
2760 in part on the underlying OS or runtime environment, and they are specific
2761 to x86 (and LLVM doesn't yet handle them correctly in some cases).</p>
2762
2763<p>Some operating systems and runtime environments use (or may in the future
2764 use) the FS/GS-segment registers for various low-level purposes, so care
2765 should be taken when considering them.</p>
Nate Begeman7ea4e862009-01-26 02:54:45 +0000[diff] [blame]2766
2767</div>
2768
2769<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2770<h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2771 <a name="x86_names">Instruction naming</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2772</h4>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2773
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2774<div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2775
Bill Wendling5c385de2006-08-28 02:26:32 +0000[diff] [blame]2776<p>An instruction name consists of the base name, a default operand size, and a
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2777 a character per operand with an optional special size. For example:</p>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2778
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2779<div class="doc_code">
2780<pre>
2781ADD8rr -&gt; add, 8-bit register, 8-bit register
2782IMUL16rmi -&gt; imul, 16-bit register, 16-bit memory, 16-bit immediate
2783IMUL16rmi8 -&gt; imul, 16-bit register, 16-bit memory, 8-bit immediate
2784MOVSX32rm16 -&gt; movsx, 32-bit register, 16-bit memory
2785</pre>
2786</div>
Chris Lattnerb4e56642004-06-04 00:16:02 +0000[diff] [blame]2787
2788</div>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]2789
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2790</div>
2791
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2792<!-- ======================================================================= -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2793<h3>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2794 <a name="ppc">The PowerPC backend</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2795</h3>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2796
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2797<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2798
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2799<p>The PowerPC code generator lives in the lib/Target/PowerPC directory. The
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2800 code generation is retargetable to several variations or <i>subtargets</i> of
2801 the PowerPC ISA; including ppc32, ppc64 and altivec.</p>
2802
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2803<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2804<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2805 <a name="ppc_abi">LLVM PowerPC ABI</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2806</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2807
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2808<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2809
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2810<p>LLVM follows the AIX PowerPC ABI, with two deviations. LLVM uses a PC
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2811 relative (PIC) or static addressing for accessing global values, so no TOC
2812 (r2) is used. Second, r31 is used as a frame pointer to allow dynamic growth
2813 of a stack frame. LLVM takes advantage of having no TOC to provide space to
2814 save the frame pointer in the PowerPC linkage area of the caller frame.
2815 Other details of PowerPC ABI can be found at <a href=
2816 "http://developer.apple.com/documentation/DeveloperTools/Conceptual/LowLevelABI/Articles/32bitPowerPC.html"
2817 >PowerPC ABI.</a> Note: This link describes the 32 bit ABI. The 64 bit ABI
2818 is similar except space for GPRs are 8 bytes wide (not 4) and r13 is reserved
2819 for system use.</p>
2820
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2821</div>
2822
2823<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2824<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2825 <a name="ppc_frame">Frame Layout</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2826</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2827
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2828<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2829
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2830<p>The size of a PowerPC frame is usually fixed for the duration of a
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2831 function's invocation. Since the frame is fixed size, all references
2832 into the frame can be accessed via fixed offsets from the stack pointer. The
2833 exception to this is when dynamic alloca or variable sized arrays are
2834 present, then a base pointer (r31) is used as a proxy for the stack pointer
2835 and stack pointer is free to grow or shrink. A base pointer is also used if
2836 llvm-gcc is not passed the -fomit-frame-pointer flag. The stack pointer is
2837 always aligned to 16 bytes, so that space allocated for altivec vectors will
2838 be properly aligned.</p>
2839
Dan Gohman1e6f5112008-11-24 16:27:17 +0000[diff] [blame]2840<p>An invocation frame is laid out as follows (low memory at top);</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2841
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2842<table class="layout">
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2843 <tr>
2844 <td>Linkage<br><br></td>
2845 </tr>
2846 <tr>
2847 <td>Parameter area<br><br></td>
2848 </tr>
2849 <tr>
2850 <td>Dynamic area<br><br></td>
2851 </tr>
2852 <tr>
2853 <td>Locals area<br><br></td>
2854 </tr>
2855 <tr>
2856 <td>Saved registers area<br><br></td>
2857 </tr>
2858 <tr style="border-style: none hidden none hidden;">
2859 <td><br></td>
2860 </tr>
2861 <tr>
2862 <td>Previous Frame<br><br></td>
2863 </tr>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2864</table>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2865
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2866<p>The <i>linkage</i> area is used by a callee to save special registers prior
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2867 to allocating its own frame. Only three entries are relevant to LLVM. The
2868 first entry is the previous stack pointer (sp), aka link. This allows
2869 probing tools like gdb or exception handlers to quickly scan the frames in
2870 the stack. A function epilog can also use the link to pop the frame from the
2871 stack. The third entry in the linkage area is used to save the return
2872 address from the lr register. Finally, as mentioned above, the last entry is
2873 used to save the previous frame pointer (r31.) The entries in the linkage
2874 area are the size of a GPR, thus the linkage area is 24 bytes long in 32 bit
2875 mode and 48 bytes in 64 bit mode.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2876
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2877<p>32 bit linkage area</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2878
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2879<table class="layout">
2880 <tr>
2881 <td>0</td>
2882 <td>Saved SP (r1)</td>
2883 </tr>
2884 <tr>
2885 <td>4</td>
2886 <td>Saved CR</td>
2887 </tr>
2888 <tr>
2889 <td>8</td>
2890 <td>Saved LR</td>
2891 </tr>
2892 <tr>
2893 <td>12</td>
2894 <td>Reserved</td>
2895 </tr>
2896 <tr>
2897 <td>16</td>
2898 <td>Reserved</td>
2899 </tr>
2900 <tr>
2901 <td>20</td>
2902 <td>Saved FP (r31)</td>
2903 </tr>
2904</table>
2905
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2906<p>64 bit linkage area</p>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2907
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2908<table class="layout">
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2909 <tr>
2910 <td>0</td>
2911 <td>Saved SP (r1)</td>
2912 </tr>
2913 <tr>
2914 <td>8</td>
2915 <td>Saved CR</td>
2916 </tr>
2917 <tr>
2918 <td>16</td>
2919 <td>Saved LR</td>
2920 </tr>
2921 <tr>
2922 <td>24</td>
2923 <td>Reserved</td>
2924 </tr>
2925 <tr>
2926 <td>32</td>
2927 <td>Reserved</td>
2928 </tr>
2929 <tr>
2930 <td>40</td>
2931 <td>Saved FP (r31)</td>
2932 </tr>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2933</table>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2934
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2935<p>The <i>parameter area</i> is used to store arguments being passed to a callee
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2936 function. Following the PowerPC ABI, the first few arguments are actually
2937 passed in registers, with the space in the parameter area unused. However,
2938 if there are not enough registers or the callee is a thunk or vararg
2939 function, these register arguments can be spilled into the parameter area.
2940 Thus, the parameter area must be large enough to store all the parameters for
2941 the largest call sequence made by the caller. The size must also be
2942 minimally large enough to spill registers r3-r10. This allows callees blind
2943 to the call signature, such as thunks and vararg functions, enough space to
2944 cache the argument registers. Therefore, the parameter area is minimally 32
2945 bytes (64 bytes in 64 bit mode.) Also note that since the parameter area is
2946 a fixed offset from the top of the frame, that a callee can access its spilt
2947 arguments using fixed offsets from the stack pointer (or base pointer.)</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2948
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2949<p>Combining the information about the linkage, parameter areas and alignment. A
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2950 stack frame is minimally 64 bytes in 32 bit mode and 128 bytes in 64 bit
2951 mode.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2952
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2953<p>The <i>dynamic area</i> starts out as size zero. If a function uses dynamic
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2954 alloca then space is added to the stack, the linkage and parameter areas are
2955 shifted to top of stack, and the new space is available immediately below the
2956 linkage and parameter areas. The cost of shifting the linkage and parameter
2957 areas is minor since only the link value needs to be copied. The link value
2958 can be easily fetched by adding the original frame size to the base pointer.
2959 Note that allocations in the dynamic space need to observe 16 byte
2960 alignment.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2961
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2962<p>The <i>locals area</i> is where the llvm compiler reserves space for local
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2963 variables.</p>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2964
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2965<p>The <i>saved registers area</i> is where the llvm compiler spills callee
2966 saved registers on entry to the callee.</p>
2967
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2968</div>
2969
2970<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2971<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2972 <a name="ppc_prolog">Prolog/Epilog</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2973</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2974
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2975<div>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2976
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2977<p>The llvm prolog and epilog are the same as described in the PowerPC ABI, with
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2978 the following exceptions. Callee saved registers are spilled after the frame
2979 is created. This allows the llvm epilog/prolog support to be common with
2980 other targets. The base pointer callee saved register r31 is saved in the
2981 TOC slot of linkage area. This simplifies allocation of space for the base
2982 pointer and makes it convenient to locate programatically and during
2983 debugging.</p>
2984
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2985</div>
2986
2987<!-- _______________________________________________________________________ -->
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2988<h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2989 <a name="ppc_dynamic">Dynamic Allocation</a>
NAKAMURA Takumifc8d9302011-04-18 23:59:50 +0000[diff] [blame]2990</h4>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2991
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2992<div>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2993
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]2994<p><i>TODO - More to come.</i></p>
Bill Wendling64602b12009-04-15 02:12:37 +0000[diff] [blame]2995
Jim Laskey57825842006-12-15 10:40:48 +0000[diff] [blame]2996</div>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]2997
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]2998</div>
2999
Justin Holewinski6c6a7fd2011-08-11 17:34:16 +0000[diff] [blame]3000<!-- ======================================================================= -->
3001<h3>
3002 <a name="ptx">The PTX backend</a>
3003</h3>
3004
3005<div>
3006
3007<p>The PTX code generator lives in the lib/Target/PTX directory. It is
3008 currently a work-in-progress, but already supports most of the code
3009 generation functionality needed to generate correct PTX kernels for
3010 CUDA devices.</p>
3011
3012<p>The code generator can target PTX 2.0+, and shader model 1.0+. The
3013 PTX ISA Reference Manual is used as the primary source of ISA
3014 information, though an effort is made to make the output of the code
3015 generator match the output of the NVidia nvcc compiler, whenever
3016 possible.</p>
3017
3018<p>Code Generator Options:</p>
3019<table border="1" cellspacing="0">
3020 <tr>
3021 <th>Option</th>
3022 <th>Description</th>
3023 </tr>
3024 <tr>
3025 <td><code>double</code></td>
3026 <td align="left">If enabled, the map_f64_to_f32 directive is
3027 disabled in the PTX output, allowing native double-precision
3028 arithmetic</td>
3029 </tr>
3030 <tr>
3031 <td><code>no-fma</code></td>
3032 <td align="left">Disable generation of Fused-Multiply Add
3033 instructions, which may be beneficial for some devices</td>
3034 </tr>
3035 <tr>
3036 <td><code>smxy / computexy</code></td>
3037 <td align="left">Set shader model/compute capability to x.y,
3038 e.g. sm20 or compute13</td>
3039 </tr>
3040</table>
3041
3042<p>Working:</p>
3043<ul>
3044 <li>Arithmetic instruction selection (including combo FMA)</li>
3045 <li>Bitwise instruction selection</li>
3046 <li>Control-flow instruction selection</li>
3047 <li>Function calls (only on SM 2.0+ and no return arguments)</li>
3048 <li>Addresses spaces (0 = global, 1 = constant, 2 = local, 4 =
3049 shared)</li>
3050 <li>Thread synchronization (bar.sync)</li>
3051 <li>Special register reads ([N]TID, [N]CTAID, PMx, CLOCK, etc.)</li>
3052</ul>
3053
3054<p>In Progress:</p>
3055<ul>
3056 <li>Robust call instruction selection</li>
3057 <li>Stack frame allocation</li>
3058 <li>Device-specific instruction scheduling optimizations</li>
3059</ul>
3060
3061
3062</div>
3063
NAKAMURA Takumiaa3d6242011-04-23 00:30:22 +0000[diff] [blame]3064</div>
Jim Laskeyef583342006-12-14 17:19:50 +0000[diff] [blame]3065
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3066<!-- *********************************************************************** -->
3067<hr>
3068<address>
3069 <a href="http://jigsaw.w3.org/css-validator/check/referer"><img
Misha Brukman86242e12008-12-11 17:34:48 +0000[diff] [blame]3070 src="http://jigsaw.w3.org/css-validator/images/vcss-blue" alt="Valid CSS"></a>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3071 <a href="http://validator.w3.org/check/referer"><img
Misha Brukman21a63702008-12-11 18:23:24 +0000[diff] [blame]3072 src="http://www.w3.org/Icons/valid-html401-blue" alt="Valid HTML 4.01"></a>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3073
3074 <a href="mailto:sabre@nondot.org">Chris Lattner</a><br>
NAKAMURA Takumica46f5a2011-04-09 02:13:37 +0000[diff] [blame]3075 <a href="http://llvm.org/">The LLVM Compiler Infrastructure</a><br>
Chris Lattner565d7d52004-06-01 06:48:00 +0000[diff] [blame]3076 Last modified: $Date$
3077</address>
3078
3079</body>
3080</html>