Simon Pilgrim | 5b2fd59 | 2017-02-06 18:57:51 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s |
| 3 | |
| 4 | ; FIXME: Various missed opportunities to simplify integer absolute instructions. |
| 5 | |
| 6 | ; fold (abs c1) -> c2 |
| 7 | define <4 x i32> @combine_v4i32_abs_constant() { |
| 8 | ; CHECK-LABEL: combine_v4i32_abs_constant: |
| 9 | ; CHECK: # BB#0: |
| 10 | ; CHECK-NEXT: vpabsd {{.*}}(%rip), %xmm0 |
| 11 | ; CHECK-NEXT: retq |
| 12 | %1 = call <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32> <i32 0, i32 -1, i32 3, i32 -2147483648>) |
| 13 | ret <4 x i32> %1 |
| 14 | } |
| 15 | |
| 16 | define <16 x i16> @combine_v16i16_abs_constant() { |
| 17 | ; CHECK-LABEL: combine_v16i16_abs_constant: |
| 18 | ; CHECK: # BB#0: |
| 19 | ; CHECK-NEXT: vpabsw {{.*}}(%rip), %ymm0 |
| 20 | ; CHECK-NEXT: retq |
| 21 | %1 = call <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16> <i16 0, i16 1, i16 -1, i16 3, i16 -3, i16 7, i16 -7, i16 255, i16 -255, i16 4096, i16 -4096, i16 32767, i16 -32767, i16 -32768, i16 32768, i16 65536>) |
| 22 | ret <16 x i16> %1 |
| 23 | } |
| 24 | |
| 25 | ; fold (abs (abs x)) -> (abs x) |
| 26 | define <8 x i16> @combine_v8i16_abs_abs(<8 x i16> %a) { |
| 27 | ; CHECK-LABEL: combine_v8i16_abs_abs: |
| 28 | ; CHECK: # BB#0: |
| 29 | ; CHECK-NEXT: vpabsw %xmm0, %xmm0 |
| 30 | ; CHECK-NEXT: vpabsw %xmm0, %xmm0 |
| 31 | ; CHECK-NEXT: retq |
Simon Pilgrim | b4a9eea | 2017-02-07 13:15:09 +0000 | [diff] [blame^] | 32 | %a1 = call <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16> %a) |
| 33 | %n2 = sub <8 x i16> zeroinitializer, %a1 |
| 34 | %c2 = icmp slt <8 x i16> %a1, zeroinitializer |
| 35 | %a2 = select <8 x i1> %c2, <8 x i16> %n2, <8 x i16> %a1 |
| 36 | ret <8 x i16> %a2 |
Simon Pilgrim | 5b2fd59 | 2017-02-06 18:57:51 +0000 | [diff] [blame] | 37 | } |
| 38 | |
| 39 | define <32 x i8> @combine_v32i8_abs_abs(<32 x i8> %a) { |
| 40 | ; CHECK-LABEL: combine_v32i8_abs_abs: |
| 41 | ; CHECK: # BB#0: |
| 42 | ; CHECK-NEXT: vpabsb %ymm0, %ymm0 |
| 43 | ; CHECK-NEXT: vpabsb %ymm0, %ymm0 |
| 44 | ; CHECK-NEXT: retq |
Simon Pilgrim | b4a9eea | 2017-02-07 13:15:09 +0000 | [diff] [blame^] | 45 | %n1 = sub <32 x i8> zeroinitializer, %a |
| 46 | %b1 = icmp slt <32 x i8> %a, zeroinitializer |
| 47 | %a1 = select <32 x i1> %b1, <32 x i8> %n1, <32 x i8> %a |
| 48 | %a2 = call <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8> %a1) |
| 49 | ret <32 x i8> %a2 |
| 50 | } |
| 51 | |
| 52 | define <4 x i64> @combine_v4i64_abs_abs(<4 x i64> %a) { |
| 53 | ; CHECK-LABEL: combine_v4i64_abs_abs: |
| 54 | ; CHECK: # BB#0: |
| 55 | ; CHECK-NEXT: vpsrad $31, %ymm0, %ymm1 |
| 56 | ; CHECK-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[1,1,3,3,5,5,7,7] |
| 57 | ; CHECK-NEXT: vpaddq %ymm1, %ymm0, %ymm0 |
| 58 | ; CHECK-NEXT: vpxor %ymm1, %ymm0, %ymm0 |
| 59 | ; CHECK-NEXT: vpsrad $31, %ymm0, %ymm1 |
| 60 | ; CHECK-NEXT: vpshufd {{.*#+}} ymm1 = ymm1[1,1,3,3,5,5,7,7] |
| 61 | ; CHECK-NEXT: vpaddq %ymm1, %ymm0, %ymm0 |
| 62 | ; CHECK-NEXT: vpxor %ymm1, %ymm0, %ymm0 |
| 63 | ; CHECK-NEXT: retq |
| 64 | %n1 = sub <4 x i64> zeroinitializer, %a |
| 65 | %b1 = icmp slt <4 x i64> %a, zeroinitializer |
| 66 | %a1 = select <4 x i1> %b1, <4 x i64> %n1, <4 x i64> %a |
| 67 | %n2 = sub <4 x i64> zeroinitializer, %a1 |
| 68 | %b2 = icmp sgt <4 x i64> %a1, zeroinitializer |
| 69 | %a2 = select <4 x i1> %b2, <4 x i64> %a1, <4 x i64> %n2 |
| 70 | ret <4 x i64> %a2 |
Simon Pilgrim | 5b2fd59 | 2017-02-06 18:57:51 +0000 | [diff] [blame] | 71 | } |
| 72 | |
| 73 | ; fold (abs x) -> x iff not-negative |
| 74 | define <16 x i8> @combine_v16i8_abs_constant(<16 x i8> %a) { |
| 75 | ; CHECK-LABEL: combine_v16i8_abs_constant: |
| 76 | ; CHECK: # BB#0: |
| 77 | ; CHECK-NEXT: vpand {{.*}}(%rip), %xmm0, %xmm0 |
| 78 | ; CHECK-NEXT: vpabsb %xmm0, %xmm0 |
| 79 | ; CHECK-NEXT: retq |
| 80 | %1 = insertelement <16 x i8> undef, i8 15, i32 0 |
| 81 | %2 = shufflevector <16 x i8> %1, <16 x i8> undef, <16 x i32> zeroinitializer |
| 82 | %3 = and <16 x i8> %a, %2 |
| 83 | %4 = call <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8> %3) |
| 84 | ret <16 x i8> %4 |
| 85 | } |
| 86 | |
| 87 | define <8 x i32> @combine_v8i32_abs_pos(<8 x i32> %a) { |
| 88 | ; CHECK-LABEL: combine_v8i32_abs_pos: |
| 89 | ; CHECK: # BB#0: |
| 90 | ; CHECK-NEXT: vpsrld $1, %ymm0, %ymm0 |
| 91 | ; CHECK-NEXT: vpabsd %ymm0, %ymm0 |
| 92 | ; CHECK-NEXT: retq |
| 93 | %1 = lshr <8 x i32> %a, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1> |
| 94 | %2 = call <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32> %1) |
| 95 | ret <8 x i32> %2 |
| 96 | } |
| 97 | |
| 98 | declare <16 x i8> @llvm.x86.ssse3.pabs.b.128(<16 x i8>) nounwind readnone |
| 99 | declare <4 x i32> @llvm.x86.ssse3.pabs.d.128(<4 x i32>) nounwind readnone |
| 100 | declare <8 x i16> @llvm.x86.ssse3.pabs.w.128(<8 x i16>) nounwind readnone |
| 101 | |
| 102 | declare <32 x i8> @llvm.x86.avx2.pabs.b(<32 x i8>) nounwind readnone |
| 103 | declare <8 x i32> @llvm.x86.avx2.pabs.d(<8 x i32>) nounwind readnone |
| 104 | declare <16 x i16> @llvm.x86.avx2.pabs.w(<16 x i16>) nounwind readnone |