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gerrit-public.fairphone.software / toolchain / llvm-project / b4adf55e0f050a494cc0c9a98b0bd46e8e30070a / . / llvm / test / CodeGen / ARM / swift-atomics.ll
blob: ca7e7fb299bf29164d765ce5d0ad677c5f0dfb4f [file] [log] [blame]
Tilmann Scheller8f79ee92013-09-02 15:48:17 +0000[diff] [blame]1; RUN: llc -mtriple=armv7-apple-ios6.0 -mcpu=swift < %s | FileCheck %s
2; RUN: llc -mtriple=armv7-apple-ios6.0 < %s | FileCheck %s --check-prefix=CHECK-STRICT-ATOMIC
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]3
4; Release operations only need the store barrier provided by a "dmb ishst",
5
6define void @test_store_release(i32* %p, i32 %v) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]7; CHECK-LABEL: test_store_release:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]8; CHECK: dmb ishst
9; CHECK: str
10
Robin Morissetdc1b2482014-09-23 23:18:01 +0000[diff] [blame]11; CHECK-STRICT-ATOMIC-LABEL: test_store_release:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]12; CHECK-STRICT-ATOMIC: dmb {{ish$}}
13 store atomic i32 %v, i32* %p release, align 4
14 ret void
15}
16
17; However, if sequential consistency is needed *something* must ensure a release
18; followed by an acquire does not get reordered. In that case a "dmb ishst" is
19; not adequate.
20define i32 @test_seq_cst(i32* %p, i32 %v) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]21; CHECK-LABEL: test_seq_cst:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]22; CHECK: dmb ishst
23; CHECK: str
24; CHECK: dmb {{ish$}}
25; CHECK: ldr
26; CHECK: dmb {{ish$}}
27
Robin Morissetdc1b2482014-09-23 23:18:01 +0000[diff] [blame]28; CHECK-STRICT-ATOMIC-LABEL: test_seq_cst:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]29; CHECK-STRICT-ATOMIC: dmb {{ish$}}
Robin Morissetdc1b2482014-09-23 23:18:01 +0000[diff] [blame]30; CHECK-STRICT-ATOMIC: str
31; CHECK-STRICT-ATOMIC: dmb {{ish$}}
32; CHECK-STRICT-ATOMIC: ldr
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]33; CHECK-STRICT-ATOMIC: dmb {{ish$}}
34
35 store atomic i32 %v, i32* %p seq_cst, align 4
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]36 %val = load atomic i32, i32* %p seq_cst, align 4
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]37 ret i32 %val
38}
39
40; Also, pure acquire operations should definitely not have an ishst barrier.
41
42define i32 @test_acq(i32* %addr) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]43; CHECK-LABEL: test_acq:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]44; CHECK: ldr
45; CHECK: dmb {{ish$}}
46
Robin Morissetdc1b2482014-09-23 23:18:01 +0000[diff] [blame]47; CHECK-STRICT-ATOMIC-LABEL: test_acq:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]48; CHECK-STRICT-ATOMIC: dmb {{ish$}}
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]49 %val = load atomic i32, i32* %addr acquire, align 4
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]50 ret i32 %val
51}