| Krzysztof Parzyszek | a0ecf07 | 2015-07-14 17:07:24 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon -hexagon-extract=0 < %s | FileCheck %s |
| Sirish Pande | f8e5e3c | 2012-05-03 21:52:53 +0000 | [diff] [blame] | 2 | ; Check that we generate fused logical and with shift instruction. |
| Krzysztof Parzyszek | a0ecf07 | 2015-07-14 17:07:24 +0000 | [diff] [blame] | 3 | ; Disable "extract" generation, since it may eliminate the and/lsr. |
| Sirish Pande | f8e5e3c | 2012-05-03 21:52:53 +0000 | [diff] [blame] | 4 | |
| 5 | ; CHECK: r{{[0-9]+}} = and(#15, lsr(r{{[0-9]+}}, #{{[0-9]+}}) |
| 6 | |
| 7 | define i32 @main(i16* %a, i16* %b) nounwind { |
| 8 | entry: |
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 9 | %0 = load i16, i16* %a, align 2 |
| Sirish Pande | f8e5e3c | 2012-05-03 21:52:53 +0000 | [diff] [blame] | 10 | %conv1 = sext i16 %0 to i32 |
| 11 | %shr1 = ashr i32 %conv1, 3 |
| 12 | %and1 = and i32 %shr1, 15 |
| 13 | %conv2 = trunc i32 %and1 to i16 |
| 14 | store i16 %conv2, i16* %b, align 2 |
| 15 | ret i32 0 |
| 16 | } |
| 17 | |