| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -O2 -march=hexagon -hexagon-expand-condsets=0 < %s |
| 2 | ; REQUIRES: asserts |
| 3 | ; Disable expand-condsets because it will assert on undefined registers. |
| 4 | |
| 5 | target triple = "hexagon-unknown--elf" |
| 6 | |
| 7 | %s.0 = type { %s.0*, %s.0* } |
| 8 | %s.1 = type { %s.1*, %s.1** } |
| 9 | |
| 10 | @g0 = external global %s.0, align 4 |
| 11 | |
| 12 | ; Function Attrs: nounwind |
| 13 | define void @f0() #0 { |
| 14 | b0: |
| 15 | br i1 undef, label %b2, label %b1 |
| 16 | |
| 17 | b1: ; preds = %b0 |
| 18 | unreachable |
| 19 | |
| 20 | b2: ; preds = %b0 |
| 21 | br i1 undef, label %b26, label %b3 |
| 22 | |
| 23 | b3: ; preds = %b2 |
| 24 | br i1 undef, label %b6, label %b4 |
| 25 | |
| 26 | b4: ; preds = %b3 |
| 27 | br i1 undef, label %b5, label %b26 |
| 28 | |
| 29 | b5: ; preds = %b4 |
| 30 | br i1 undef, label %b7, label %b26 |
| 31 | |
| 32 | b6: ; preds = %b3 |
| 33 | br label %b7 |
| 34 | |
| 35 | b7: ; preds = %b6, %b5 |
| 36 | br i1 undef, label %b11, label %b8 |
| 37 | |
| 38 | b8: ; preds = %b7 |
| 39 | br i1 undef, label %b10, label %b9 |
| 40 | |
| 41 | b9: ; preds = %b8 |
| 42 | unreachable |
| 43 | |
| 44 | b10: ; preds = %b8 |
| 45 | unreachable |
| 46 | |
| 47 | b11: ; preds = %b7 |
| 48 | br i1 undef, label %b25, label %b12 |
| 49 | |
| 50 | b12: ; preds = %b11 |
| 51 | br i1 undef, label %b14, label %b13 |
| 52 | |
| 53 | b13: ; preds = %b12 |
| 54 | br label %b14 |
| 55 | |
| 56 | b14: ; preds = %b13, %b12 |
| 57 | br i1 undef, label %b15, label %b16 |
| 58 | |
| 59 | b15: ; preds = %b14 |
| 60 | br label %b16 |
| 61 | |
| 62 | b16: ; preds = %b15, %b14 |
| 63 | br i1 undef, label %b18, label %b17 |
| 64 | |
| 65 | b17: ; preds = %b16 |
| 66 | unreachable |
| 67 | |
| 68 | b18: ; preds = %b16 |
| 69 | %v0 = load %s.0*, %s.0** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 1), align 4 |
| 70 | %v1 = load %s.0*, %s.0** getelementptr inbounds (%s.0, %s.0* @g0, i32 0, i32 0), align 4 |
| 71 | %v2 = select i1 undef, %s.0* %v0, %s.0* %v1 |
| 72 | br i1 undef, label %b22, label %b19 |
| 73 | |
| 74 | b19: ; preds = %b18 |
| 75 | %v3 = load %s.1*, %s.1** undef, align 4 |
| 76 | %v4 = icmp eq %s.1* %v3, null |
| 77 | br i1 %v4, label %b21, label %b20 |
| 78 | |
| 79 | b20: ; preds = %b19 |
| 80 | store %s.1** undef, %s.1*** undef, align 4 |
| 81 | br label %b21 |
| 82 | |
| 83 | b21: ; preds = %b20, %b19 |
| 84 | br label %b22 |
| 85 | |
| 86 | b22: ; preds = %b21, %b18 |
| 87 | br i1 undef, label %b24, label %b23 |
| 88 | |
| 89 | b23: ; preds = %b22 |
| 90 | store %s.0* %v2, %s.0** undef, align 4 |
| 91 | br label %b24 |
| 92 | |
| 93 | b24: ; preds = %b23, %b22 |
| 94 | unreachable |
| 95 | |
| 96 | b25: ; preds = %b11 |
| 97 | unreachable |
| 98 | |
| 99 | b26: ; preds = %b5, %b4, %b2 |
| 100 | ret void |
| 101 | } |
| 102 | |
| 103 | attributes #0 = { nounwind "target-cpu"="hexagonv55" } |