| Krzysztof Parzyszek | 046090d | 2018-03-12 14:01:28 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon -enable-pipeliner < %s |
| 2 | ; REQUIRES: asserts |
| 3 | |
| 4 | ; Check that the dependences are order correctly, and the list can be |
| 5 | ; updated when the instruction to insert has a def and use conflict. |
| 6 | |
| 7 | ; Function Attrs: nounwind |
| 8 | define fastcc void @f0() #0 { |
| 9 | b0: |
| 10 | br i1 undef, label %b7, label %b1 |
| 11 | |
| 12 | b1: ; preds = %b0 |
| 13 | br i1 undef, label %b2, label %b4 |
| 14 | |
| 15 | b2: ; preds = %b1 |
| 16 | %v0 = load i16, i16* undef, align 2 |
| 17 | br label %b5 |
| 18 | |
| 19 | b3: ; preds = %b5 |
| 20 | br label %b4 |
| 21 | |
| 22 | b4: ; preds = %b3, %b1 |
| 23 | %v1 = phi i16 [ %v11, %b3 ], [ 0, %b1 ] |
| 24 | br i1 false, label %b7, label %b6 |
| 25 | |
| 26 | b5: ; preds = %b5, %b2 |
| 27 | %v2 = phi i16 [ %v3, %b5 ], [ undef, %b2 ] |
| 28 | %v3 = phi i16 [ 0, %b5 ], [ %v0, %b2 ] |
| 29 | %v4 = phi i16 [ %v2, %b5 ], [ undef, %b2 ] |
| 30 | %v5 = phi i16 [ %v11, %b5 ], [ 0, %b2 ] |
| 31 | %v6 = phi i32 [ %v12, %b5 ], [ undef, %b2 ] |
| 32 | %v7 = or i16 0, %v5 |
| 33 | %v8 = lshr i16 %v4, 8 |
| 34 | %v9 = or i16 %v8, %v7 |
| 35 | %v10 = or i16 0, %v9 |
| 36 | %v11 = or i16 0, %v10 |
| 37 | %v12 = add nsw i32 %v6, -32 |
| 38 | %v13 = icmp sgt i32 %v12, 31 |
| 39 | br i1 %v13, label %b5, label %b3 |
| 40 | |
| 41 | b6: ; preds = %b4 |
| 42 | br label %b7 |
| 43 | |
| 44 | b7: ; preds = %b6, %b4, %b0 |
| 45 | ret void |
| 46 | } |
| 47 | |
| 48 | attributes #0 = { nounwind "target-cpu"="hexagonv55" } |