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gerrit-public.fairphone.software / toolchain / llvm-project / b71424fda5d8375e47946775b6687f15ec17939a / . / llvm / docs / CommandGuide / tblgen.rst
blob: a42b04dbf8be3e5290cc3ddecd0e13905683666e [file] [log] [blame]
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]1tblgen - Target Description To C++ Code Generator
2=================================================
3
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]4SYNOPSIS
5--------
6
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]7:program:`tblgen` [*options*] [*filename*]
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]8
9DESCRIPTION
10-----------
11
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]12:program:`tblgen` translates from target description (``.td``) files into C++
13code that can be included in the definition of an LLVM target library. Most
14users of LLVM will not need to use this program. It is only for assisting with
15writing an LLVM target backend.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]16
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]17The input and output of :program:`tblgen` is beyond the scope of this short
Sean Silva397ee6e2014-04-07 22:46:40 +0000[diff] [blame]18introduction; please see the :doc:`introduction to TableGen
19<../TableGen/index>`.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]20
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]21The *filename* argument specifies the name of a Target Description (``.td``)
22file to read as input.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]23
24OPTIONS
25-------
26
Dmitri Gribenko7d8b6072013-04-27 16:34:24 +0000[diff] [blame]27.. program:: tblgen
28
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]29.. option:: -help
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]30
31 Print a summary of command line options.
32
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]33.. option:: -o filename
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]34
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]35 Specify the output file name. If ``filename`` is ``-``, then
36 :program:`tblgen` sends its output to standard output.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]37
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]38.. option:: -I directory
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]39
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]40 Specify where to find other target description files for inclusion. The
41 ``directory`` value should be a full or partial path to a directory that
42 contains target description files.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]43
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]44.. option:: -asmparsernum N
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]45
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]46 Make -gen-asm-parser emit assembly writer number ``N``.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]47
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]48.. option:: -asmwriternum N
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]49
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]50 Make -gen-asm-writer emit assembly writer number ``N``.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]51
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]52.. option:: -class className
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]53
54 Print the enumeration list for this class.
55
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]56.. option:: -print-records
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]57
58 Print all records to standard output (default).
59
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]60.. option:: -print-enums
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]61
Dmitri Gribenko7d8b6072013-04-27 16:34:24 +0000[diff] [blame]62 Print enumeration values for a class.
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]63
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]64.. option:: -print-sets
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]65
66 Print expanded sets for testing DAG exprs.
67
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]68.. option:: -gen-emitter
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]69
70 Generate machine code emitter.
71
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]72.. option:: -gen-register-info
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]73
74 Generate registers and register classes info.
75
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]76.. option:: -gen-instr-info
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]77
78 Generate instruction descriptions.
79
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]80.. option:: -gen-asm-writer
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]81
82 Generate the assembly writer.
83
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]84.. option:: -gen-disassembler
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]85
86 Generate disassembler.
87
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]88.. option:: -gen-pseudo-lowering
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]89
90 Generate pseudo instruction lowering.
91
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]92.. option:: -gen-dag-isel
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]93
94 Generate a DAG (Directed Acycle Graph) instruction selector.
95
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]96.. option:: -gen-asm-matcher
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]97
98 Generate assembly instruction matcher.
99
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]100.. option:: -gen-dfa-packetizer
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]101
102 Generate DFA Packetizer for VLIW targets.
103
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]104.. option:: -gen-fast-isel
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]105
106 Generate a "fast" instruction selector.
107
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]108.. option:: -gen-subtarget
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]109
110 Generate subtarget enumerations.
111
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]112.. option:: -gen-intrinsic
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]113
114 Generate intrinsic information.
115
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]116.. option:: -gen-tgt-intrinsic
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]117
118 Generate target intrinsic information.
119
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]120.. option:: -gen-enhanced-disassembly-info
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]121
122 Generate enhanced disassembly info.
123
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]124.. option:: -version
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]125
126 Show the version number of this program.
127
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]128EXIT STATUS
129-----------
130
Dmitri Gribenkocbb07be2012-11-29 17:41:05 +0000[diff] [blame]131If :program:`tblgen` succeeds, it will exit with 0. Otherwise, if an error
Daniel Dunbar8f4a8a62012-05-08 16:50:35 +0000[diff] [blame]132occurs, it will exit with a non-zero value.