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gerrit-public.fairphone.software / toolchain / llvm-project / b7cef81fd36c85e52b115b9ed6d1fb92d63781d6 / . / llvm / test / CodeGen / RISCV / frame.ll
blob: e8a833f37f83b20d9a140594b5efebdfaac2b9b8 [file] [log] [blame]
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]3; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
Francis Visoiu Mistrihb7cef812019-01-14 10:55:55 +0000[diff] [blame^]4; RUN: llc -mtriple=riscv32 -frame-pointer=all -verify-machineinstrs < %s \
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]5; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]6
7%struct.key_t = type { i32, [16 x i8] }
8
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]9define i32 @test() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]10; RV32I-FPELIM-LABEL: test:
11; RV32I-FPELIM: # %bb.0:
12; RV32I-FPELIM-NEXT: addi sp, sp, -32
13; RV32I-FPELIM-NEXT: sw ra, 28(sp)
14; RV32I-FPELIM-NEXT: sw zero, 24(sp)
15; RV32I-FPELIM-NEXT: sw zero, 20(sp)
16; RV32I-FPELIM-NEXT: sw zero, 16(sp)
17; RV32I-FPELIM-NEXT: sw zero, 12(sp)
18; RV32I-FPELIM-NEXT: sw zero, 8(sp)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]19; RV32I-FPELIM-NEXT: addi a0, sp, 12
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]20; RV32I-FPELIM-NEXT: call test1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]21; RV32I-FPELIM-NEXT: mv a0, zero
22; RV32I-FPELIM-NEXT: lw ra, 28(sp)
23; RV32I-FPELIM-NEXT: addi sp, sp, 32
24; RV32I-FPELIM-NEXT: ret
25;
26; RV32I-WITHFP-LABEL: test:
27; RV32I-WITHFP: # %bb.0:
28; RV32I-WITHFP-NEXT: addi sp, sp, -32
29; RV32I-WITHFP-NEXT: sw ra, 28(sp)
30; RV32I-WITHFP-NEXT: sw s0, 24(sp)
31; RV32I-WITHFP-NEXT: addi s0, sp, 32
32; RV32I-WITHFP-NEXT: sw zero, -16(s0)
33; RV32I-WITHFP-NEXT: sw zero, -20(s0)
34; RV32I-WITHFP-NEXT: sw zero, -24(s0)
35; RV32I-WITHFP-NEXT: sw zero, -28(s0)
36; RV32I-WITHFP-NEXT: sw zero, -32(s0)
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]37; RV32I-WITHFP-NEXT: addi a0, s0, -28
Shiva Chend58bd8d2018-04-25 14:19:12 +0000[diff] [blame]38; RV32I-WITHFP-NEXT: call test1
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]39; RV32I-WITHFP-NEXT: mv a0, zero
40; RV32I-WITHFP-NEXT: lw s0, 24(sp)
41; RV32I-WITHFP-NEXT: lw ra, 28(sp)
42; RV32I-WITHFP-NEXT: addi sp, sp, 32
43; RV32I-WITHFP-NEXT: ret
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]44 %key = alloca %struct.key_t, align 4
45 %1 = bitcast %struct.key_t* %key to i8*
Daniel Neilson1e687242018-01-19 17:13:12 +0000[diff] [blame]46 call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 0, i64 20, i1 false)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]47 %2 = getelementptr inbounds %struct.key_t, %struct.key_t* %key, i64 0, i32 1, i64 0
48 call void @test1(i8* %2) #3
49 ret i32 0
50}
51
Daniel Neilson1e687242018-01-19 17:13:12 +0000[diff] [blame]52declare void @llvm.memset.p0i8.i64(i8* nocapture, i8, i64, i1)
Alex Bradbury660bcce2017-12-11 11:53:54 +0000[diff] [blame]53
54declare void @test1(i8*)