blob: f256d89f0cb7263182b18802fcb7505b5944ac47 [file] [log] [blame]
Matt Arsenault6689abe2016-05-05 20:07:37 +00001; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI
Matt Arsenault7aad8fd2017-01-24 22:02:15 +00002; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI
Matt Arsenault6689abe2016-05-05 20:07:37 +00003; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
Tom Stellard98f675a2013-08-01 15:23:26 +00004
Tom Stellard115a6152016-11-10 16:02:37 +00005; R600: {{^}}s_mad_zext_i32_to_i64:
Marek Olsak37cd4d02015-02-03 21:53:27 +00006; R600: MEM_RAT_CACHELESS STORE_RAW
7; R600: MEM_RAT_CACHELESS STORE_RAW
Tom Stellard98f675a2013-08-01 15:23:26 +00008
Tom Stellard115a6152016-11-10 16:02:37 +00009; SI: {{^}}s_mad_zext_i32_to_i64:
Matt Arsenault0de924b2015-11-02 23:15:42 +000010; SI: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}}
Marek Olsak37cd4d02015-02-03 21:53:27 +000011; SI: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000012define amdgpu_kernel void @s_mad_zext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) #0 {
Tom Stellard98f675a2013-08-01 15:23:26 +000013entry:
Tom Stellard115a6152016-11-10 16:02:37 +000014 %tmp0 = mul i32 %a, %b
15 %tmp1 = add i32 %tmp0, %c
16 %tmp2 = zext i32 %tmp1 to i64
17 store i64 %tmp2, i64 addrspace(1)* %out
Tom Stellard98f675a2013-08-01 15:23:26 +000018 ret void
19}
Michel Danzer5d26fdf2014-02-05 09:48:05 +000020
Tom Stellard115a6152016-11-10 16:02:37 +000021; SI-LABEL: {{^}}s_cmp_zext_i1_to_i32
Marek Olsak37cd4d02015-02-03 21:53:27 +000022; SI: v_cndmask_b32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000023define amdgpu_kernel void @s_cmp_zext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
Michel Danzer5d26fdf2014-02-05 09:48:05 +000024entry:
Tom Stellard115a6152016-11-10 16:02:37 +000025 %tmp0 = icmp eq i32 %a, %b
26 %tmp1 = zext i1 %tmp0 to i32
27 store i32 %tmp1, i32 addrspace(1)* %out
Michel Danzer5d26fdf2014-02-05 09:48:05 +000028 ret void
29}
Matt Arsenault51df0c12014-04-17 02:03:08 +000030
Tom Stellard115a6152016-11-10 16:02:37 +000031; SI-LABEL: {{^}}s_arg_zext_i1_to_i64:
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000032define amdgpu_kernel void @s_arg_zext_i1_to_i64(i64 addrspace(1)* %out, i1 zeroext %arg) #0 {
Tom Stellard115a6152016-11-10 16:02:37 +000033 %ext = zext i1 %arg to i64
34 store i64 %ext, i64 addrspace(1)* %out, align 8
35 ret void
36}
37
38; SI-LABEL: {{^}}s_cmp_zext_i1_to_i64:
Marek Olsak37cd4d02015-02-03 21:53:27 +000039; SI: s_mov_b32 s{{[0-9]+}}, 0
Matt Arsenault5d8eb252016-09-30 01:50:20 +000040; SI: v_cmp_eq_u32
Marek Olsak37cd4d02015-02-03 21:53:27 +000041; SI: v_cndmask_b32
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000042define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 {
Matt Arsenault51df0c12014-04-17 02:03:08 +000043 %cmp = icmp eq i32 %a, %b
44 %ext = zext i1 %cmp to i64
45 store i64 %ext, i64 addrspace(1)* %out, align 8
46 ret void
47}
Tom Stellard115a6152016-11-10 16:02:37 +000048
49; SI-LABEL: {{^}}s_cmp_zext_i1_to_i16
50; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc
51; SI: buffer_store_short [[RESULT]]
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000052define amdgpu_kernel void @s_cmp_zext_i1_to_i16(i16 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b) #0 {
Tom Stellard115a6152016-11-10 16:02:37 +000053 %tmp0 = icmp eq i16 %a, %b
54 %tmp1 = zext i1 %tmp0 to i16
55 store i16 %tmp1, i16 addrspace(1)* %out
56 ret void
57}
58
59attributes #0 = { nounwind }