Matt Arsenault | 6689abe | 2016-05-05 20:07:37 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -march=amdgcn -verify-machineinstrs | FileCheck %s --check-prefix=SI |
Matt Arsenault | 7aad8fd | 2017-01-24 22:02:15 +0000 | [diff] [blame] | 2 | ; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s --check-prefix=SI |
Matt Arsenault | 6689abe | 2016-05-05 20:07:37 +0000 | [diff] [blame] | 3 | ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600 |
Tom Stellard | 98f675a | 2013-08-01 15:23:26 +0000 | [diff] [blame] | 4 | |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 5 | ; R600: {{^}}s_mad_zext_i32_to_i64: |
Marek Olsak | 37cd4d0 | 2015-02-03 21:53:27 +0000 | [diff] [blame] | 6 | ; R600: MEM_RAT_CACHELESS STORE_RAW |
| 7 | ; R600: MEM_RAT_CACHELESS STORE_RAW |
Tom Stellard | 98f675a | 2013-08-01 15:23:26 +0000 | [diff] [blame] | 8 | |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 9 | ; SI: {{^}}s_mad_zext_i32_to_i64: |
Matt Arsenault | 0de924b | 2015-11-02 23:15:42 +0000 | [diff] [blame] | 10 | ; SI: v_mov_b32_e32 v[[V_ZERO:[0-9]]], 0{{$}} |
Marek Olsak | 37cd4d0 | 2015-02-03 21:53:27 +0000 | [diff] [blame] | 11 | ; SI: buffer_store_dwordx2 v[0:[[V_ZERO]]{{\]}} |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 12 | define amdgpu_kernel void @s_mad_zext_i32_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) #0 { |
Tom Stellard | 98f675a | 2013-08-01 15:23:26 +0000 | [diff] [blame] | 13 | entry: |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 14 | %tmp0 = mul i32 %a, %b |
| 15 | %tmp1 = add i32 %tmp0, %c |
| 16 | %tmp2 = zext i32 %tmp1 to i64 |
| 17 | store i64 %tmp2, i64 addrspace(1)* %out |
Tom Stellard | 98f675a | 2013-08-01 15:23:26 +0000 | [diff] [blame] | 18 | ret void |
| 19 | } |
Michel Danzer | 5d26fdf | 2014-02-05 09:48:05 +0000 | [diff] [blame] | 20 | |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 21 | ; SI-LABEL: {{^}}s_cmp_zext_i1_to_i32 |
Marek Olsak | 37cd4d0 | 2015-02-03 21:53:27 +0000 | [diff] [blame] | 22 | ; SI: v_cndmask_b32 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 23 | define amdgpu_kernel void @s_cmp_zext_i1_to_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { |
Michel Danzer | 5d26fdf | 2014-02-05 09:48:05 +0000 | [diff] [blame] | 24 | entry: |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 25 | %tmp0 = icmp eq i32 %a, %b |
| 26 | %tmp1 = zext i1 %tmp0 to i32 |
| 27 | store i32 %tmp1, i32 addrspace(1)* %out |
Michel Danzer | 5d26fdf | 2014-02-05 09:48:05 +0000 | [diff] [blame] | 28 | ret void |
| 29 | } |
Matt Arsenault | 51df0c1 | 2014-04-17 02:03:08 +0000 | [diff] [blame] | 30 | |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 31 | ; SI-LABEL: {{^}}s_arg_zext_i1_to_i64: |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 32 | define amdgpu_kernel void @s_arg_zext_i1_to_i64(i64 addrspace(1)* %out, i1 zeroext %arg) #0 { |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 33 | %ext = zext i1 %arg to i64 |
| 34 | store i64 %ext, i64 addrspace(1)* %out, align 8 |
| 35 | ret void |
| 36 | } |
| 37 | |
| 38 | ; SI-LABEL: {{^}}s_cmp_zext_i1_to_i64: |
Marek Olsak | 37cd4d0 | 2015-02-03 21:53:27 +0000 | [diff] [blame] | 39 | ; SI: s_mov_b32 s{{[0-9]+}}, 0 |
Matt Arsenault | 5d8eb25 | 2016-09-30 01:50:20 +0000 | [diff] [blame] | 40 | ; SI: v_cmp_eq_u32 |
Marek Olsak | 37cd4d0 | 2015-02-03 21:53:27 +0000 | [diff] [blame] | 41 | ; SI: v_cndmask_b32 |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 42 | define amdgpu_kernel void @s_cmp_zext_i1_to_i64(i64 addrspace(1)* %out, i32 %a, i32 %b) #0 { |
Matt Arsenault | 51df0c1 | 2014-04-17 02:03:08 +0000 | [diff] [blame] | 43 | %cmp = icmp eq i32 %a, %b |
| 44 | %ext = zext i1 %cmp to i64 |
| 45 | store i64 %ext, i64 addrspace(1)* %out, align 8 |
| 46 | ret void |
| 47 | } |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 48 | |
| 49 | ; SI-LABEL: {{^}}s_cmp_zext_i1_to_i16 |
| 50 | ; SI: v_cndmask_b32_e64 [[RESULT:v[0-9]+]], 0, 1, vcc |
| 51 | ; SI: buffer_store_short [[RESULT]] |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 52 | define amdgpu_kernel void @s_cmp_zext_i1_to_i16(i16 addrspace(1)* %out, i16 zeroext %a, i16 zeroext %b) #0 { |
Tom Stellard | 115a615 | 2016-11-10 16:02:37 +0000 | [diff] [blame] | 53 | %tmp0 = icmp eq i16 %a, %b |
| 54 | %tmp1 = zext i1 %tmp0 to i16 |
| 55 | store i16 %tmp1, i16 addrspace(1)* %out |
| 56 | ret void |
| 57 | } |
| 58 | |
| 59 | attributes #0 = { nounwind } |