Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / b99c2eb0f0a1413df3f81f7f47b35e78c74d989f / . / llvm / test / CodeGen / PowerPC / fma-assoc.ll
blob: 3044dd09128c5b9e3016aa4fe38c46ad9976bcfc [file] [log] [blame]
Olivier Sallenave04515322015-01-07 20:54:17 +0000[diff] [blame]1; RUN: llc < %s -march=ppc32 -fp-contract=fast -mattr=-vsx | FileCheck %s
2; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -fp-contract=fast -mattr=+vsx -mcpu=pwr7 | FileCheck -check-prefix=CHECK-VSX %s
3
4define double @test_FMADD_ASSOC1(double %A, double %B, double %C,
5 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +0000[diff] [blame^]6 %F = fmul double %A, %B ; <double> [#uses=1]
7 %G = fmul double %C, %D ; <double> [#uses=1]
8 %H = fadd double %F, %G ; <double> [#uses=1]
9 %I = fadd double %H, %E ; <double> [#uses=1]
10 ret double %I
Olivier Sallenave04515322015-01-07 20:54:17 +0000[diff] [blame]11; CHECK-LABEL: test_FMADD_ASSOC1:
12; CHECK: fmadd
13; CHECK-NEXT: fmadd
14; CHECK-NEXT: blr
15
16; CHECK-VSX-LABEL: test_FMADD_ASSOC1:
17; CHECK-VSX: xsmaddmdp
18; CHECK-VSX-NEXT: xsmaddadp
19; CHECK-VSX-NEXT: fmr
20; CHECK-VSX-NEXT: blr
21}
22
23define double @test_FMADD_ASSOC2(double %A, double %B, double %C,
24 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +0000[diff] [blame^]25 %F = fmul double %A, %B ; <double> [#uses=1]
26 %G = fmul double %C, %D ; <double> [#uses=1]
27 %H = fadd double %F, %G ; <double> [#uses=1]
28 %I = fadd double %E, %H ; <double> [#uses=1]
29 ret double %I
Olivier Sallenave04515322015-01-07 20:54:17 +0000[diff] [blame]30; CHECK-LABEL: test_FMADD_ASSOC2:
31; CHECK: fmadd
32; CHECK-NEXT: fmadd
33; CHECK-NEXT: blr
34
35; CHECK-VSX-LABEL: test_FMADD_ASSOC2:
36; CHECK-VSX: xsmaddmdp
37; CHECK-VSX-NEXT: xsmaddadp
38; CHECK-VSX-NEXT: fmr
39; CHECK-VSX-NEXT: blr
40}
41
42define double @test_FMSUB_ASSOC1(double %A, double %B, double %C,
43 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +0000[diff] [blame^]44 %F = fmul double %A, %B ; <double> [#uses=1]
45 %G = fmul double %C, %D ; <double> [#uses=1]
46 %H = fadd double %F, %G ; <double> [#uses=1]
47 %I = fsub double %H, %E ; <double> [#uses=1]
48 ret double %I
Olivier Sallenave04515322015-01-07 20:54:17 +0000[diff] [blame]49; CHECK-LABEL: test_FMSUB_ASSOC1:
50; CHECK: fmsub
51; CHECK-NEXT: fmadd
52; CHECK-NEXT: blr
53
54; CHECK-VSX-LABEL: test_FMSUB_ASSOC1:
55; CHECK-VSX: xsmsubmdp
56; CHECK-VSX-NEXT: xsmaddadp
57; CHECK-VSX-NEXT: fmr
58; CHECK-VSX-NEXT: blr
59}
60
61define double @test_FMSUB_ASSOC2(double %A, double %B, double %C,
62 double %D, double %E) {
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +0000[diff] [blame^]63 %F = fmul double %A, %B ; <double> [#uses=1]
64 %G = fmul double %C, %D ; <double> [#uses=1]
65 %H = fadd double %F, %G ; <double> [#uses=1]
66 %I = fsub double %E, %H ; <double> [#uses=1]
67 ret double %I
Olivier Sallenave04515322015-01-07 20:54:17 +0000[diff] [blame]68; CHECK-LABEL: test_FMSUB_ASSOC2:
69; CHECK: fnmsub
70; CHECK-NEXT: fnmsub
71; CHECK-NEXT: blr
72
73; CHECK-VSX-LABEL: test_FMSUB_ASSOC2:
74; CHECK-VSX: xsnmsubmdp
75; CHECK-VSX-NEXT: xsnmsubadp
76; CHECK-VSX-NEXT: fmr
77; CHECK-VSX-NEXT: blr
78}
79
Olivier Sallenaveb99c2eb2015-04-20 20:29:40 +0000[diff] [blame^]80define double @test_FMADD_ASSOC_EXT1(float %A, float %B, double %C,
81 double %D, double %E) {
82 %F = fmul float %A, %B ; <float> [#uses=1]
83 %G = fpext float %F to double ; <double> [#uses=1]
84 %H = fmul double %C, %D ; <double> [#uses=1]
85 %I = fadd double %H, %G ; <double> [#uses=1]
86 %J = fadd double %I, %E ; <double> [#uses=1]
87 ret double %J
88; CHECK-LABEL: test_FMADD_ASSOC_EXT1:
89; CHECK: fmadd
90; CHECK-NEXT: fmadd
91; CHECK-NEXT: blr
92
93; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT1:
94; CHECK-VSX: xsmaddmdp
95; CHECK-VSX-NEXT: xsmaddadp
96; CHECK-VSX-NEXT: blr
97}
98
99define double @test_FMADD_ASSOC_EXT2(float %A, float %B, float %C,
100 float %D, double %E) {
101 %F = fmul float %A, %B ; <float> [#uses=1]
102 %G = fmul float %C, %D ; <float> [#uses=1]
103 %H = fadd float %F, %G ; <float> [#uses=1]
104 %I = fpext float %H to double ; <double> [#uses=1]
105 %J = fadd double %I, %E ; <double> [#uses=1]
106 ret double %J
107; CHECK-LABEL: test_FMADD_ASSOC_EXT2:
108; CHECK: fmadd
109; CHECK-NEXT: fmadd
110; CHECK-NEXT: blr
111
112; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT2:
113; CHECK-VSX: xsmaddmdp
114; CHECK-VSX-NEXT: xsmaddadp
115; CHECK-VSX-NEXT: fmr
116; CHECK-VSX-NEXT: blr
117}
118
119define double @test_FMADD_ASSOC_EXT3(float %A, float %B, double %C,
120 double %D, double %E) {
121 %F = fmul float %A, %B ; <float> [#uses=1]
122 %G = fpext float %F to double ; <double> [#uses=1]
123 %H = fmul double %C, %D ; <double> [#uses=1]
124 %I = fadd double %H, %G ; <double> [#uses=1]
125 %J = fadd double %E, %I ; <double> [#uses=1]
126 ret double %J
127; CHECK-LABEL: test_FMADD_ASSOC_EXT3:
128; CHECK: fmadd
129; CHECK-NEXT: fmadd
130; CHECK-NEXT: blr
131
132; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT3:
133; CHECK-VSX: xsmaddmdp
134; CHECK-VSX-NEXT: xsmaddadp
135; CHECK-VSX-NEXT: blr
136}
137
138define double @test_FMADD_ASSOC_EXT4(float %A, float %B, float %C,
139 float %D, double %E) {
140 %F = fmul float %A, %B ; <float> [#uses=1]
141 %G = fmul float %C, %D ; <float> [#uses=1]
142 %H = fadd float %F, %G ; <float> [#uses=1]
143 %I = fpext float %H to double ; <double> [#uses=1]
144 %J = fadd double %E, %I ; <double> [#uses=1]
145 ret double %J
146; CHECK-LABEL: test_FMADD_ASSOC_EXT4:
147; CHECK: fmadd
148; CHECK-NEXT: fmadd
149; CHECK-NEXT: blr
150
151; CHECK-VSX-LABEL: test_FMADD_ASSOC_EXT4:
152; CHECK-VSX: xsmaddmdp
153; CHECK-VSX-NEXT: xsmaddadp
154; CHECK-VSX-NEXT: fmr
155; CHECK-VSX-NEXT: blr
156}
157
158define double @test_FMSUB_ASSOC_EXT1(float %A, float %B, double %C,
159 double %D, double %E) {
160 %F = fmul float %A, %B ; <float> [#uses=1]
161 %G = fpext float %F to double ; <double> [#uses=1]
162 %H = fmul double %C, %D ; <double> [#uses=1]
163 %I = fadd double %H, %G ; <double> [#uses=1]
164 %J = fsub double %I, %E ; <double> [#uses=1]
165 ret double %J
166; CHECK-LABEL: test_FMSUB_ASSOC_EXT1:
167; CHECK: fmsub
168; CHECK-NEXT: fmadd
169; CHECK-NEXT: blr
170
171; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT1:
172; CHECK-VSX: xsmsubmdp
173; CHECK-VSX-NEXT: xsmaddadp
174; CHECK-VSX-NEXT: blr
175}
176
177define double @test_FMSUB_ASSOC_EXT2(float %A, float %B, float %C,
178 float %D, double %E) {
179 %F = fmul float %A, %B ; <float> [#uses=1]
180 %G = fmul float %C, %D ; <float> [#uses=1]
181 %H = fadd float %F, %G ; <float> [#uses=1]
182 %I = fpext float %H to double ; <double> [#uses=1]
183 %J = fsub double %I, %E ; <double> [#uses=1]
184 ret double %J
185; CHECK-LABEL: test_FMSUB_ASSOC_EXT2:
186; CHECK: fmsub
187; CHECK-NEXT: fmadd
188; CHECK-NEXT: blr
189
190; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT2:
191; CHECK-VSX: xsmsubmdp
192; CHECK-VSX-NEXT: xsmaddadp
193; CHECK-VSX-NEXT: fmr
194; CHECK-VSX-NEXT: blr
195}
196
197define double @test_FMSUB_ASSOC_EXT3(float %A, float %B, double %C,
198 double %D, double %E) {
199 %F = fmul float %A, %B ; <float> [#uses=1]
200 %G = fpext float %F to double ; <double> [#uses=1]
201 %H = fmul double %C, %D ; <double> [#uses=1]
202 %I = fadd double %H, %G ; <double> [#uses=1]
203 %J = fsub double %E, %I ; <double> [#uses=1]
204 ret double %J
205; CHECK-LABEL: test_FMSUB_ASSOC_EXT3:
206; CHECK: fnmsub
207; CHECK-NEXT: fnmsub
208; CHECK-NEXT: blr
209
210; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT3:
211; CHECK-VSX: xsnmsubmdp
212; CHECK-VSX-NEXT: xsnmsubadp
213; CHECK-VSX-NEXT: fmr
214; CHECK-VSX-NEXT: blr
215}
216
217define double @test_FMSUB_ASSOC_EXT4(float %A, float %B, float %C,
218 float %D, double %E) {
219 %F = fmul float %A, %B ; <float> [#uses=1]
220 %G = fmul float %C, %D ; <float> [#uses=1]
221 %H = fadd float %F, %G ; <float> [#uses=1]
222 %I = fpext float %H to double ; <double> [#uses=1]
223 %J = fsub double %E, %I ; <double> [#uses=1]
224 ret double %J
225; CHECK-LABEL: test_FMSUB_ASSOC_EXT4:
226; CHECK: fnmsub
227; CHECK-NEXT: fnmsub
228; CHECK-NEXT: blr
229
230; CHECK-VSX-LABEL: test_FMSUB_ASSOC_EXT4:
231; CHECK-VSX: xsnmsubmdp
232; CHECK-VSX-NEXT: xsnmsubadp
233; CHECK-VSX-NEXT: fmr
234; CHECK-VSX-NEXT: blr
235}