blob: d8d28223adaba3c807f99b49481bc2404f042bd6 [file] [log] [blame]
Ehsan Amiria538b0f2016-08-03 18:17:35 +00001; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s
2; RUN: llc -verify-machineinstrs < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s
Hal Finkelf6d45f22013-04-01 17:52:07 +00003target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
4target triple = "powerpc64-unknown-linux-gnu"
5
6define float @foo(i64 %a) nounwind {
7entry:
8 %x = sitofp i64 %a to float
9 ret float %x
10
11; CHECK: @foo
12; CHECK: std 3,
13; CHECK: lfd [[REG:[0-9]+]],
14; CHECK: fcfids 1, [[REG]]
15; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +000016
17; CHECK-VSX: @foo
18; CHECK-VSX: std 3,
19; CHECK-VSX: lxsdx [[REG:[0-9]+]],
20; CHECK-VSX: fcfids 1, [[REG]]
21; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +000022}
23
24define double @goo(i64 %a) nounwind {
25entry:
26 %x = sitofp i64 %a to double
27 ret double %x
28
29; CHECK: @goo
30; CHECK: std 3,
31; CHECK: lfd [[REG:[0-9]+]],
32; CHECK: fcfid 1, [[REG]]
33; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +000034
35; CHECK-VSX: @goo
36; CHECK-VSX: std 3,
37; CHECK-VSX: lxsdx [[REG:[0-9]+]],
38; CHECK-VSX: xscvsxddp 1, [[REG]]
39; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +000040}
41
42define float @foou(i64 %a) nounwind {
43entry:
44 %x = uitofp i64 %a to float
45 ret float %x
46
47; CHECK: @foou
48; CHECK: std 3,
49; CHECK: lfd [[REG:[0-9]+]],
50; CHECK: fcfidus 1, [[REG]]
51; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +000052
53; CHECK-VSX: @foou
54; CHECK-VSX: std 3,
55; CHECK-VSX: lxsdx [[REG:[0-9]+]],
56; CHECK-VSX: fcfidus 1, [[REG]]
57; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +000058}
59
60define double @goou(i64 %a) nounwind {
61entry:
62 %x = uitofp i64 %a to double
63 ret double %x
64
65; CHECK: @goou
66; CHECK: std 3,
67; CHECK: lfd [[REG:[0-9]+]],
68; CHECK: fcfidu 1, [[REG]]
69; CHECK: blr
Hal Finkel4a912252014-03-23 05:35:00 +000070
71; CHECK-VSX: @goou
72; CHECK-VSX: std 3,
73; CHECK-VSX: lxsdx [[REG:[0-9]+]],
74; CHECK-VSX: xscvuxddp 1, [[REG]]
75; CHECK-VSX: blr
Hal Finkelf6d45f22013-04-01 17:52:07 +000076}
77