blob: 053210650d10749cf02fb3f3d6834f5210b68954 [file] [log] [blame]
Sanjay Patelb193fe92016-05-02 15:06:55 +00001; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
Evan Cheng32c7cc82012-06-21 22:52:49 +00002; RUN: opt < %s -instcombine -S | FileCheck %s
3
Sanjay Patelb193fe92016-05-02 15:06:55 +00004define i32 @t1(i16 zeroext %x, i32 %y) {
5; CHECK-LABEL: @t1(
6; CHECK-NEXT: entry:
7; CHECK-NEXT: [[CONV:%.*]] = zext i16 %x to i32
8; CHECK-NEXT: [[TMP0:%.*]] = add i32 %y, 1
9; CHECK-NEXT: [[D:%.*]] = lshr i32 [[CONV]], [[TMP0]]
10; CHECK-NEXT: ret i32 [[D]]
11;
Evan Cheng32c7cc82012-06-21 22:52:49 +000012entry:
Evan Cheng32c7cc82012-06-21 22:52:49 +000013 %conv = zext i16 %x to i32
14 %s = shl i32 2, %y
15 %d = sdiv i32 %conv, %s
16 ret i32 %d
17}
18
19; rdar://11721329
Sanjay Patelb193fe92016-05-02 15:06:55 +000020define i64 @t2(i64 %x, i32 %y) {
21; CHECK-LABEL: @t2(
22; CHECK-NEXT: [[TMP1:%.*]] = zext i32 %y to i64
23; CHECK-NEXT: [[TMP2:%.*]] = lshr i64 %x, [[TMP1]]
24; CHECK-NEXT: ret i64 [[TMP2]]
25;
Evan Cheng32c7cc82012-06-21 22:52:49 +000026 %1 = shl i32 1, %y
27 %2 = zext i32 %1 to i64
28 %3 = udiv i64 %x, %2
29 ret i64 %3
30}
Benjamin Kramerefb4d342012-09-21 16:26:41 +000031
32; PR13250
Sanjay Patelb193fe92016-05-02 15:06:55 +000033define i64 @t3(i64 %x, i32 %y) {
34; CHECK-LABEL: @t3(
35; CHECK-NEXT: [[TMP1:%.*]] = add i32 %y, 2
36; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
37; CHECK-NEXT: [[TMP3:%.*]] = lshr i64 %x, [[TMP2]]
38; CHECK-NEXT: ret i64 [[TMP3]]
39;
Benjamin Kramerefb4d342012-09-21 16:26:41 +000040 %1 = shl i32 4, %y
41 %2 = zext i32 %1 to i64
42 %3 = udiv i64 %x, %2
43 ret i64 %3
44}
David Majnemer797227e2013-06-29 08:40:07 +000045
Sanjay Patelb193fe92016-05-02 15:06:55 +000046define i32 @t4(i32 %x, i32 %y) {
47; CHECK-LABEL: @t4(
48; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 %y, 5
49; CHECK-NEXT: [[DOTV:%.*]] = select i1 [[TMP1]], i32 5, i32 %y
50; CHECK-NEXT: [[TMP2:%.*]] = lshr i32 %x, [[DOTV]]
51; CHECK-NEXT: ret i32 [[TMP2]]
52;
David Majnemer797227e2013-06-29 08:40:07 +000053 %1 = shl i32 1, %y
54 %2 = icmp ult i32 %1, 32
55 %3 = select i1 %2, i32 32, i32 %1
56 %4 = udiv i32 %x, %3
57 ret i32 %4
58}
59
Sanjay Patelb193fe92016-05-02 15:06:55 +000060define i32 @t5(i1 %x, i1 %y, i32 %V) {
61; CHECK-LABEL: @t5(
62; CHECK-NEXT: [[DOTV:%.*]] = select i1 %x, i32 5, i32 6
63; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 %V, [[DOTV]]
64; CHECK-NEXT: [[TMP2:%.*]] = select i1 %y, i32 [[TMP1]], i32 0
65; CHECK-NEXT: ret i32 [[TMP2]]
66;
David Majnemer797227e2013-06-29 08:40:07 +000067 %1 = shl i32 1, %V
68 %2 = select i1 %x, i32 32, i32 64
69 %3 = select i1 %y, i32 %2, i32 %1
70 %4 = udiv i32 %V, %3
71 ret i32 %4
72}
73
Sanjay Patelb193fe92016-05-02 15:06:55 +000074define i32 @t6(i32 %x, i32 %z) {
75; CHECK-LABEL: @t6(
76; CHECK-NEXT: [[X_IS_ZERO:%.*]] = icmp eq i32 %x, 0
77; CHECK-NEXT: [[DIVISOR:%.*]] = select i1 [[X_IS_ZERO]], i32 1, i32 %x
78; CHECK-NEXT: [[Y:%.*]] = udiv i32 %z, [[DIVISOR]]
79; CHECK-NEXT: ret i32 [[Y]]
80;
David Majnemer797227e2013-06-29 08:40:07 +000081 %x_is_zero = icmp eq i32 %x, 0
82 %divisor = select i1 %x_is_zero, i32 1, i32 %x
83 %y = udiv i32 %z, %divisor
84 ret i32 %y
85}