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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / . / llvm / lib / Target / AArch64 / InstPrinter / AArch64InstPrinter.h
blob: ea68d9848b427e8a6fccf80bf2db40b029e57843 [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//===-- AArch64InstPrinter.h - Convert AArch64 MCInst to assembly syntax --===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This class prints an AArch64 MCInst to a .s file.
11//
12//===----------------------------------------------------------------------===//
13
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame]14#ifndef LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
15#define LLVM_LIB_TARGET_AARCH64_INSTPRINTER_AARCH64INSTPRINTER_H
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]16
17#include "MCTargetDesc/AArch64MCTargetDesc.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]18#include "llvm/MC/MCInstPrinter.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]19
20namespace llvm {
21
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]22class AArch64InstPrinter : public MCInstPrinter {
23public:
24 AArch64InstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
Eric Christopher2226c722015-03-30 21:52:26 +0000[diff] [blame]25 const MCRegisterInfo &MRI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]27 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
28 const MCSubtargetInfo &STI) override;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]29 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
30
31 // Autogenerated by tblgen.
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]32 virtual void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
33 raw_ostream &O);
34 virtual bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
35 raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]36 virtual void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]37 unsigned PrintMethodIdx,
38 const MCSubtargetInfo &STI,
39 raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]40 virtual StringRef getRegName(unsigned RegNo) const {
41 return getRegisterName(RegNo);
42 }
43 static const char *getRegisterName(unsigned RegNo,
44 unsigned AltIdx = AArch64::NoRegAltName);
45
46protected:
Oliver Stannard1a81cc9f2015-11-26 15:28:47 +0000[diff] [blame]47 bool printSysAlias(const MCInst *MI, const MCSubtargetInfo &STI,
48 raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]49 // Operand printers
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]50 void printOperand(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
51 raw_ostream &O);
52 void printHexImm(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
53 raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]54 void printPostIncOperand(const MCInst *MI, unsigned OpNo, unsigned Imm,
55 raw_ostream &O);
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]56 template <int Amount>
57 void printPostIncOperand(const MCInst *MI, unsigned OpNo,
58 const MCSubtargetInfo &STI, raw_ostream &O) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]59 printPostIncOperand(MI, OpNo, Amount, O);
60 }
61
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]62 void printVRegOperand(const MCInst *MI, unsigned OpNo,
63 const MCSubtargetInfo &STI, raw_ostream &O);
64 void printSysCROperand(const MCInst *MI, unsigned OpNo,
65 const MCSubtargetInfo &STI, raw_ostream &O);
66 void printAddSubImm(const MCInst *MI, unsigned OpNum,
67 const MCSubtargetInfo &STI, raw_ostream &O);
68 void printLogicalImm32(const MCInst *MI, unsigned OpNum,
69 const MCSubtargetInfo &STI, raw_ostream &O);
70 void printLogicalImm64(const MCInst *MI, unsigned OpNum,
71 const MCSubtargetInfo &STI, raw_ostream &O);
72 void printShifter(const MCInst *MI, unsigned OpNum,
73 const MCSubtargetInfo &STI, raw_ostream &O);
74 void printShiftedRegister(const MCInst *MI, unsigned OpNum,
75 const MCSubtargetInfo &STI, raw_ostream &O);
76 void printExtendedRegister(const MCInst *MI, unsigned OpNum,
77 const MCSubtargetInfo &STI, raw_ostream &O);
78 void printArithExtend(const MCInst *MI, unsigned OpNum,
79 const MCSubtargetInfo &STI, raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]80
81 void printMemExtend(const MCInst *MI, unsigned OpNum, raw_ostream &O,
82 char SrcRegKind, unsigned Width);
83 template <char SrcRegKind, unsigned Width>
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]84 void printMemExtend(const MCInst *MI, unsigned OpNum,
85 const MCSubtargetInfo &STI, raw_ostream &O) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86 printMemExtend(MI, OpNum, O, SrcRegKind, Width);
87 }
88
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]89 void printCondCode(const MCInst *MI, unsigned OpNum,
90 const MCSubtargetInfo &STI, raw_ostream &O);
91 void printInverseCondCode(const MCInst *MI, unsigned OpNum,
92 const MCSubtargetInfo &STI, raw_ostream &O);
93 void printAlignedLabel(const MCInst *MI, unsigned OpNum,
94 const MCSubtargetInfo &STI, raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]95 void printUImm12Offset(const MCInst *MI, unsigned OpNum, unsigned Scale,
96 raw_ostream &O);
97 void printAMIndexedWB(const MCInst *MI, unsigned OpNum, unsigned Scale,
98 raw_ostream &O);
99
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]100 template <int Scale>
101 void printUImm12Offset(const MCInst *MI, unsigned OpNum,
102 const MCSubtargetInfo &STI, raw_ostream &O) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]103 printUImm12Offset(MI, OpNum, Scale, O);
104 }
105
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]106 template <int BitWidth>
107 void printAMIndexedWB(const MCInst *MI, unsigned OpNum,
108 const MCSubtargetInfo &STI, raw_ostream &O) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]109 printAMIndexedWB(MI, OpNum, BitWidth / 8, O);
110 }
111
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]112 void printAMNoIndex(const MCInst *MI, unsigned OpNum,
113 const MCSubtargetInfo &STI, raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]114
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]115 template <int Scale>
116 void printImmScale(const MCInst *MI, unsigned OpNum,
117 const MCSubtargetInfo &STI, raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]118
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]119 void printPrefetchOp(const MCInst *MI, unsigned OpNum,
120 const MCSubtargetInfo &STI, raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]121
Oliver Stannarda34e4702015-12-01 10:48:51 +0000[diff] [blame]122 void printPSBHintOp(const MCInst *MI, unsigned OpNum,
123 const MCSubtargetInfo &STI, raw_ostream &O);
124
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]125 void printFPImmOperand(const MCInst *MI, unsigned OpNum,
126 const MCSubtargetInfo &STI, raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]127
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]128 void printVectorList(const MCInst *MI, unsigned OpNum,
129 const MCSubtargetInfo &STI, raw_ostream &O,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]130 StringRef LayoutSuffix);
131
132 /// Print a list of vector registers where the type suffix is implicit
133 /// (i.e. attached to the instruction rather than the registers).
134 void printImplicitlyTypedVectorList(const MCInst *MI, unsigned OpNum,
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]135 const MCSubtargetInfo &STI,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]136 raw_ostream &O);
137
138 template <unsigned NumLanes, char LaneKind>
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]139 void printTypedVectorList(const MCInst *MI, unsigned OpNum,
140 const MCSubtargetInfo &STI, raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]141
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]142 void printVectorIndex(const MCInst *MI, unsigned OpNum,
143 const MCSubtargetInfo &STI, raw_ostream &O);
144 void printAdrpLabel(const MCInst *MI, unsigned OpNum,
145 const MCSubtargetInfo &STI, raw_ostream &O);
146 void printBarrierOption(const MCInst *MI, unsigned OpNum,
147 const MCSubtargetInfo &STI, raw_ostream &O);
148 void printMSRSystemRegister(const MCInst *MI, unsigned OpNum,
149 const MCSubtargetInfo &STI, raw_ostream &O);
150 void printMRSSystemRegister(const MCInst *MI, unsigned OpNum,
151 const MCSubtargetInfo &STI, raw_ostream &O);
152 void printSystemPStateField(const MCInst *MI, unsigned OpNum,
153 const MCSubtargetInfo &STI, raw_ostream &O);
154 void printSIMDType10Operand(const MCInst *MI, unsigned OpNum,
155 const MCSubtargetInfo &STI, raw_ostream &O);
Vladimir Sukharev5f6f60d2015-06-02 10:58:41 +0000[diff] [blame]156 template<unsigned size>
157 void printGPRSeqPairsClassOperand(const MCInst *MI, unsigned OpNum,
158 const MCSubtargetInfo &STI,
159 raw_ostream &O);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]160};
161
162class AArch64AppleInstPrinter : public AArch64InstPrinter {
163public:
164 AArch64AppleInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
Eric Christopher2226c722015-03-30 21:52:26 +0000[diff] [blame]165 const MCRegisterInfo &MRI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]166
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]167 void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot,
168 const MCSubtargetInfo &STI) override;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]170 void printInstruction(const MCInst *MI, const MCSubtargetInfo &STI,
171 raw_ostream &O) override;
172 bool printAliasInstr(const MCInst *MI, const MCSubtargetInfo &STI,
173 raw_ostream &O) override;
Benjamin Kramer8c90fd72014-09-03 11:41:21 +0000[diff] [blame]174 void printCustomAliasOperand(const MCInst *MI, unsigned OpIdx,
175 unsigned PrintMethodIdx,
Akira Hatanakab46d0232015-03-27 20:36:02 +0000[diff] [blame]176 const MCSubtargetInfo &STI,
Benjamin Kramer8c90fd72014-09-03 11:41:21 +0000[diff] [blame]177 raw_ostream &O) override;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 StringRef getRegName(unsigned RegNo) const override {
179 return getRegisterName(RegNo);
180 }
181 static const char *getRegisterName(unsigned RegNo,
182 unsigned AltIdx = AArch64::NoRegAltName);
183};
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]184}
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]185
186#endif