| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=amdgcn -mcpu=SI < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s |
| 2 | ; RUN: llc -march=amdgcn -mcpu=tonga < %s -verify-machineinstrs | FileCheck -check-prefix=SI %s |
| 3 | |
| 4 | ; If this occurs it is likely due to reordering and the restore was |
| 5 | ; originally supposed to happen before SI_END_CF. |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 6 | |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 7 | ; SI: s_or_b64 exec, exec, [[SAVED:s\[[0-9]+:[0-9]+\]|[a-z]+]] |
| 8 | ; SI-NOT: v_readlane_b32 [[SAVED]] |
| Nicolai Haehnle | df3a20c | 2016-04-06 19:40:20 +0000 | [diff] [blame] | 9 | define amdgpu_ps void @main() { |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 10 | main_body: |
| 11 | %0 = call float @llvm.SI.load.const(<16 x i8> undef, i32 16) |
| 12 | %1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 32) |
| 13 | %2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 80) |
| 14 | %3 = call float @llvm.SI.load.const(<16 x i8> undef, i32 84) |
| 15 | %4 = call float @llvm.SI.load.const(<16 x i8> undef, i32 88) |
| 16 | %5 = call float @llvm.SI.load.const(<16 x i8> undef, i32 96) |
| 17 | %6 = call float @llvm.SI.load.const(<16 x i8> undef, i32 100) |
| 18 | %7 = call float @llvm.SI.load.const(<16 x i8> undef, i32 104) |
| 19 | %8 = call float @llvm.SI.load.const(<16 x i8> undef, i32 112) |
| 20 | %9 = call float @llvm.SI.load.const(<16 x i8> undef, i32 116) |
| 21 | %10 = call float @llvm.SI.load.const(<16 x i8> undef, i32 120) |
| 22 | %11 = call float @llvm.SI.load.const(<16 x i8> undef, i32 128) |
| 23 | %12 = call float @llvm.SI.load.const(<16 x i8> undef, i32 132) |
| 24 | %13 = call float @llvm.SI.load.const(<16 x i8> undef, i32 136) |
| 25 | %14 = call float @llvm.SI.load.const(<16 x i8> undef, i32 144) |
| 26 | %15 = call float @llvm.SI.load.const(<16 x i8> undef, i32 148) |
| 27 | %16 = call float @llvm.SI.load.const(<16 x i8> undef, i32 152) |
| 28 | %17 = call float @llvm.SI.load.const(<16 x i8> undef, i32 160) |
| 29 | %18 = call float @llvm.SI.load.const(<16 x i8> undef, i32 164) |
| 30 | %19 = call float @llvm.SI.load.const(<16 x i8> undef, i32 168) |
| 31 | %20 = call float @llvm.SI.load.const(<16 x i8> undef, i32 176) |
| 32 | %21 = call float @llvm.SI.load.const(<16 x i8> undef, i32 180) |
| 33 | %22 = call float @llvm.SI.load.const(<16 x i8> undef, i32 184) |
| 34 | %23 = call float @llvm.SI.load.const(<16 x i8> undef, i32 192) |
| 35 | %24 = call float @llvm.SI.load.const(<16 x i8> undef, i32 196) |
| 36 | %25 = call float @llvm.SI.load.const(<16 x i8> undef, i32 200) |
| 37 | %26 = call float @llvm.SI.load.const(<16 x i8> undef, i32 208) |
| 38 | %27 = call float @llvm.SI.load.const(<16 x i8> undef, i32 212) |
| 39 | %28 = call float @llvm.SI.load.const(<16 x i8> undef, i32 216) |
| 40 | %29 = call float @llvm.SI.load.const(<16 x i8> undef, i32 224) |
| 41 | %30 = call float @llvm.SI.load.const(<16 x i8> undef, i32 228) |
| 42 | %31 = call float @llvm.SI.load.const(<16 x i8> undef, i32 232) |
| 43 | %32 = call float @llvm.SI.load.const(<16 x i8> undef, i32 240) |
| 44 | %33 = call float @llvm.SI.load.const(<16 x i8> undef, i32 244) |
| 45 | %34 = call float @llvm.SI.load.const(<16 x i8> undef, i32 248) |
| 46 | %35 = call float @llvm.SI.load.const(<16 x i8> undef, i32 256) |
| 47 | %36 = call float @llvm.SI.load.const(<16 x i8> undef, i32 260) |
| 48 | %37 = call float @llvm.SI.load.const(<16 x i8> undef, i32 264) |
| 49 | %38 = call float @llvm.SI.load.const(<16 x i8> undef, i32 272) |
| 50 | %39 = call float @llvm.SI.load.const(<16 x i8> undef, i32 276) |
| 51 | %40 = call float @llvm.SI.load.const(<16 x i8> undef, i32 280) |
| 52 | %41 = call float @llvm.SI.load.const(<16 x i8> undef, i32 288) |
| 53 | %42 = call float @llvm.SI.load.const(<16 x i8> undef, i32 292) |
| 54 | %43 = call float @llvm.SI.load.const(<16 x i8> undef, i32 296) |
| 55 | %44 = call float @llvm.SI.load.const(<16 x i8> undef, i32 304) |
| 56 | %45 = call float @llvm.SI.load.const(<16 x i8> undef, i32 308) |
| 57 | %46 = call float @llvm.SI.load.const(<16 x i8> undef, i32 312) |
| 58 | %47 = call float @llvm.SI.load.const(<16 x i8> undef, i32 320) |
| 59 | %48 = call float @llvm.SI.load.const(<16 x i8> undef, i32 324) |
| 60 | %49 = call float @llvm.SI.load.const(<16 x i8> undef, i32 328) |
| 61 | %50 = call float @llvm.SI.load.const(<16 x i8> undef, i32 336) |
| 62 | %51 = call float @llvm.SI.load.const(<16 x i8> undef, i32 340) |
| 63 | %52 = call float @llvm.SI.load.const(<16 x i8> undef, i32 344) |
| 64 | %53 = call float @llvm.SI.load.const(<16 x i8> undef, i32 352) |
| 65 | %54 = call float @llvm.SI.load.const(<16 x i8> undef, i32 356) |
| 66 | %55 = call float @llvm.SI.load.const(<16 x i8> undef, i32 360) |
| 67 | %56 = call float @llvm.SI.load.const(<16 x i8> undef, i32 368) |
| 68 | %57 = call float @llvm.SI.load.const(<16 x i8> undef, i32 372) |
| 69 | %58 = call float @llvm.SI.load.const(<16 x i8> undef, i32 376) |
| 70 | %59 = call float @llvm.SI.load.const(<16 x i8> undef, i32 384) |
| 71 | %60 = call float @llvm.SI.load.const(<16 x i8> undef, i32 388) |
| 72 | %61 = call float @llvm.SI.load.const(<16 x i8> undef, i32 392) |
| 73 | %62 = call float @llvm.SI.load.const(<16 x i8> undef, i32 400) |
| 74 | %63 = call float @llvm.SI.load.const(<16 x i8> undef, i32 404) |
| 75 | %64 = call float @llvm.SI.load.const(<16 x i8> undef, i32 408) |
| 76 | %65 = call float @llvm.SI.load.const(<16 x i8> undef, i32 416) |
| 77 | %66 = call float @llvm.SI.load.const(<16 x i8> undef, i32 420) |
| 78 | br label %LOOP |
| 79 | |
| 80 | LOOP: ; preds = %ENDIF2795, %main_body |
| 81 | %temp894.0 = phi float [ 0.000000e+00, %main_body ], [ %temp894.1, %ENDIF2795 ] |
| 82 | %temp18.0 = phi float [ undef, %main_body ], [ %temp18.1, %ENDIF2795 ] |
| Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 83 | %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 |
| 84 | %67 = icmp sgt i32 %tid, 4 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 85 | br i1 %67, label %ENDLOOP, label %ENDIF |
| 86 | |
| 87 | ENDLOOP: ; preds = %ELSE2566, %LOOP |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 88 | %one.sub.a.i = fsub float 1.000000e+00, %0 |
| 89 | %one.sub.ac.i = fmul float %one.sub.a.i, undef |
| 90 | %result.i = fadd float fmul (float undef, float undef), %one.sub.ac.i |
| 91 | call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float undef, float %result.i, float undef, float 1.000000e+00) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 92 | ret void |
| 93 | |
| 94 | ENDIF: ; preds = %LOOP |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 95 | %68 = fsub float %2, undef |
| 96 | %69 = fsub float %3, undef |
| 97 | %70 = fsub float %4, undef |
| 98 | %71 = fmul float %68, 0.000000e+00 |
| 99 | %72 = fmul float %69, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 100 | %73 = fmul float %70, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 101 | %74 = fsub float %6, undef |
| 102 | %75 = fsub float %7, undef |
| 103 | %76 = fmul float %74, undef |
| 104 | %77 = fmul float %75, 0.000000e+00 |
| 105 | %78 = call float @llvm.minnum.f32(float %73, float %77) |
| 106 | %79 = call float @llvm.maxnum.f32(float %71, float 0.000000e+00) |
| 107 | %80 = call float @llvm.maxnum.f32(float %72, float %76) |
| 108 | %81 = call float @llvm.maxnum.f32(float undef, float %78) |
| 109 | %82 = call float @llvm.minnum.f32(float %79, float %80) |
| 110 | %83 = call float @llvm.minnum.f32(float %82, float undef) |
| 111 | %84 = fsub float %14, undef |
| 112 | %85 = fsub float %15, undef |
| 113 | %86 = fsub float %16, undef |
| 114 | %87 = fmul float %84, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 115 | %88 = fmul float %85, undef |
| 116 | %89 = fmul float %86, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 117 | %90 = fsub float %17, undef |
| 118 | %91 = fsub float %18, undef |
| 119 | %92 = fsub float %19, undef |
| 120 | %93 = fmul float %90, 0.000000e+00 |
| 121 | %94 = fmul float %91, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 122 | %95 = fmul float %92, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 123 | %96 = call float @llvm.minnum.f32(float %88, float %94) |
| 124 | %97 = call float @llvm.maxnum.f32(float %87, float %93) |
| 125 | %98 = call float @llvm.maxnum.f32(float %89, float %95) |
| 126 | %99 = call float @llvm.maxnum.f32(float undef, float %96) |
| 127 | %100 = call float @llvm.maxnum.f32(float %99, float undef) |
| 128 | %101 = call float @llvm.minnum.f32(float %97, float undef) |
| 129 | %102 = call float @llvm.minnum.f32(float %101, float %98) |
| 130 | %103 = fsub float %30, undef |
| 131 | %104 = fsub float %31, undef |
| 132 | %105 = fmul float %103, 0.000000e+00 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 133 | %106 = fmul float %104, 0.000000e+00 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 134 | %107 = call float @llvm.minnum.f32(float undef, float %105) |
| 135 | %108 = call float @llvm.maxnum.f32(float undef, float %106) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 136 | %109 = call float @llvm.maxnum.f32(float undef, float %107) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 137 | %110 = call float @llvm.maxnum.f32(float %109, float undef) |
| 138 | %111 = call float @llvm.minnum.f32(float undef, float %108) |
| 139 | %112 = fsub float %32, undef |
| 140 | %113 = fsub float %33, undef |
| 141 | %114 = fsub float %34, undef |
| 142 | %115 = fmul float %112, 0.000000e+00 |
| 143 | %116 = fmul float %113, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 144 | %117 = fmul float %114, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 145 | %118 = fsub float %35, undef |
| 146 | %119 = fsub float %36, undef |
| 147 | %120 = fsub float %37, undef |
| 148 | %121 = fmul float %118, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 149 | %122 = fmul float %119, undef |
| 150 | %123 = fmul float %120, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 151 | %124 = call float @llvm.minnum.f32(float %115, float %121) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 152 | %125 = call float @llvm.minnum.f32(float %116, float %122) |
| 153 | %126 = call float @llvm.minnum.f32(float %117, float %123) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 154 | %127 = call float @llvm.maxnum.f32(float %124, float %125) |
| 155 | %128 = call float @llvm.maxnum.f32(float %127, float %126) |
| 156 | %129 = fsub float %38, undef |
| 157 | %130 = fsub float %39, undef |
| 158 | %131 = fsub float %40, undef |
| 159 | %132 = fmul float %129, 0.000000e+00 |
| 160 | %133 = fmul float %130, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 161 | %134 = fmul float %131, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 162 | %135 = fsub float %41, undef |
| 163 | %136 = fsub float %42, undef |
| 164 | %137 = fsub float %43, undef |
| 165 | %138 = fmul float %135, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 166 | %139 = fmul float %136, undef |
| 167 | %140 = fmul float %137, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 168 | %141 = call float @llvm.minnum.f32(float %132, float %138) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 169 | %142 = call float @llvm.minnum.f32(float %133, float %139) |
| 170 | %143 = call float @llvm.minnum.f32(float %134, float %140) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 171 | %144 = call float @llvm.maxnum.f32(float %141, float %142) |
| 172 | %145 = call float @llvm.maxnum.f32(float %144, float %143) |
| 173 | %146 = fsub float %44, undef |
| 174 | %147 = fsub float %45, undef |
| 175 | %148 = fsub float %46, undef |
| 176 | %149 = fmul float %146, 0.000000e+00 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 177 | %150 = fmul float %147, 0.000000e+00 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 178 | %151 = fmul float %148, undef |
| 179 | %152 = fsub float %47, undef |
| 180 | %153 = fsub float %48, undef |
| 181 | %154 = fsub float %49, undef |
| 182 | %155 = fmul float %152, undef |
| 183 | %156 = fmul float %153, 0.000000e+00 |
| 184 | %157 = fmul float %154, undef |
| 185 | %158 = call float @llvm.minnum.f32(float %149, float %155) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 186 | %159 = call float @llvm.minnum.f32(float %150, float %156) |
| 187 | %160 = call float @llvm.minnum.f32(float %151, float %157) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 188 | %161 = call float @llvm.maxnum.f32(float %158, float %159) |
| 189 | %162 = call float @llvm.maxnum.f32(float %161, float %160) |
| 190 | %163 = fsub float %50, undef |
| 191 | %164 = fsub float %51, undef |
| 192 | %165 = fsub float %52, undef |
| 193 | %166 = fmul float %163, undef |
| 194 | %167 = fmul float %164, 0.000000e+00 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 195 | %168 = fmul float %165, 0.000000e+00 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 196 | %169 = fsub float %53, undef |
| 197 | %170 = fsub float %54, undef |
| 198 | %171 = fsub float %55, undef |
| 199 | %172 = fdiv float 1.000000e+00, %temp18.0 |
| 200 | %173 = fmul float %169, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 201 | %174 = fmul float %170, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 202 | %175 = fmul float %171, %172 |
| 203 | %176 = call float @llvm.minnum.f32(float %166, float %173) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 204 | %177 = call float @llvm.minnum.f32(float %167, float %174) |
| 205 | %178 = call float @llvm.minnum.f32(float %168, float %175) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 206 | %179 = call float @llvm.maxnum.f32(float %176, float %177) |
| 207 | %180 = call float @llvm.maxnum.f32(float %179, float %178) |
| 208 | %181 = fsub float %62, undef |
| 209 | %182 = fsub float %63, undef |
| 210 | %183 = fsub float %64, undef |
| 211 | %184 = fmul float %181, 0.000000e+00 |
| 212 | %185 = fmul float %182, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 213 | %186 = fmul float %183, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 214 | %187 = fsub float %65, undef |
| 215 | %188 = fsub float %66, undef |
| 216 | %189 = fmul float %187, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 217 | %190 = fmul float %188, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 218 | %191 = call float @llvm.maxnum.f32(float %184, float %189) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 219 | %192 = call float @llvm.maxnum.f32(float %185, float %190) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 220 | %193 = call float @llvm.maxnum.f32(float %186, float undef) |
| 221 | %194 = call float @llvm.minnum.f32(float %191, float %192) |
| 222 | %195 = call float @llvm.minnum.f32(float %194, float %193) |
| 223 | %.temp292.7 = select i1 undef, float %162, float undef |
| 224 | %temp292.9 = select i1 false, float %180, float %.temp292.7 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 225 | %.temp292.9 = select i1 undef, float undef, float %temp292.9 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 226 | %196 = fcmp ogt float undef, 0.000000e+00 |
| 227 | %197 = fcmp olt float undef, %195 |
| 228 | %198 = and i1 %196, %197 |
| 229 | %199 = fcmp olt float undef, %.temp292.9 |
| 230 | %200 = and i1 %198, %199 |
| 231 | %temp292.11 = select i1 %200, float undef, float %.temp292.9 |
| Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 232 | %tid0 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 |
| 233 | %cmp0 = icmp eq i32 %tid0, 0 |
| 234 | br i1 %cmp0, label %IF2565, label %ELSE2566 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 235 | |
| 236 | IF2565: ; preds = %ENDIF |
| Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 237 | %tid1 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 |
| 238 | %cmp1 = icmp eq i32 %tid1, 0 |
| 239 | br i1 %cmp1, label %ENDIF2582, label %ELSE2584 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 240 | |
| 241 | ELSE2566: ; preds = %ENDIF |
| Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 242 | %tid2 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 |
| 243 | %tidf = bitcast i32 %tid2 to float |
| 244 | %201 = fcmp oeq float %temp292.11, %tidf |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 245 | br i1 %201, label %ENDLOOP, label %ELSE2593 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 246 | |
| 247 | ENDIF2564: ; preds = %ENDIF2594, %ENDIF2588 |
| 248 | %temp894.1 = phi float [ undef, %ENDIF2588 ], [ %temp894.2, %ENDIF2594 ] |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 249 | %temp18.1 = phi float [ %218, %ENDIF2588 ], [ undef, %ENDIF2594 ] |
| 250 | %202 = fsub float %5, undef |
| 251 | %203 = fmul float %202, undef |
| 252 | %204 = call float @llvm.maxnum.f32(float undef, float %203) |
| 253 | %205 = call float @llvm.minnum.f32(float %204, float undef) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 254 | %206 = call float @llvm.minnum.f32(float %205, float undef) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 255 | %207 = fcmp ogt float undef, 0.000000e+00 |
| 256 | %208 = fcmp olt float undef, 1.000000e+00 |
| 257 | %209 = and i1 %207, %208 |
| Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 258 | %tid3 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 |
| 259 | %tidf3 = bitcast i32 %tid3 to float |
| 260 | %210 = fcmp olt float %tidf3, %206 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 261 | %211 = and i1 %209, %210 |
| 262 | br i1 %211, label %ENDIF2795, label %ELSE2797 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 263 | |
| 264 | ELSE2584: ; preds = %IF2565 |
| 265 | br label %ENDIF2582 |
| 266 | |
| 267 | ENDIF2582: ; preds = %ELSE2584, %IF2565 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 268 | %212 = fadd float %1, undef |
| 269 | %213 = fadd float 0.000000e+00, %212 |
| 270 | %floor = call float @llvm.floor.f32(float %213) |
| 271 | %214 = fsub float %213, %floor |
| Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 272 | %tid4 = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #2 |
| 273 | %cmp4 = icmp eq i32 %tid4, 0 |
| 274 | br i1 %cmp4, label %IF2589, label %ELSE2590 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 275 | |
| 276 | IF2589: ; preds = %ENDIF2582 |
| 277 | br label %ENDIF2588 |
| 278 | |
| 279 | ELSE2590: ; preds = %ENDIF2582 |
| 280 | br label %ENDIF2588 |
| 281 | |
| 282 | ENDIF2588: ; preds = %ELSE2590, %IF2589 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 283 | %215 = fsub float 1.000000e+00, %214 |
| 284 | %216 = call float @llvm.sqrt.f32(float %215) |
| 285 | %217 = fmul float %216, undef |
| 286 | %218 = fadd float %217, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 287 | br label %ENDIF2564 |
| 288 | |
| 289 | ELSE2593: ; preds = %ELSE2566 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 290 | %219 = fcmp oeq float %temp292.11, %81 |
| 291 | %220 = fcmp olt float %81, %83 |
| 292 | %221 = and i1 %219, %220 |
| 293 | br i1 %221, label %ENDIF2594, label %ELSE2596 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 294 | |
| 295 | ELSE2596: ; preds = %ELSE2593 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 296 | %222 = fcmp oeq float %temp292.11, %100 |
| 297 | %223 = fcmp olt float %100, %102 |
| 298 | %224 = and i1 %222, %223 |
| 299 | br i1 %224, label %ENDIF2594, label %ELSE2632 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 300 | |
| 301 | ENDIF2594: ; preds = %ELSE2788, %ELSE2785, %ELSE2782, %ELSE2779, %IF2775, %ELSE2761, %ELSE2758, %IF2757, %ELSE2704, %ELSE2686, %ELSE2671, %ELSE2668, %IF2667, %ELSE2632, %ELSE2596, %ELSE2593 |
| 302 | %temp894.2 = phi float [ 0.000000e+00, %IF2667 ], [ 0.000000e+00, %ELSE2671 ], [ 0.000000e+00, %IF2757 ], [ 0.000000e+00, %ELSE2761 ], [ %temp894.0, %ELSE2758 ], [ 0.000000e+00, %IF2775 ], [ 0.000000e+00, %ELSE2779 ], [ 0.000000e+00, %ELSE2782 ], [ %.2848, %ELSE2788 ], [ 0.000000e+00, %ELSE2785 ], [ 0.000000e+00, %ELSE2593 ], [ 0.000000e+00, %ELSE2632 ], [ 0.000000e+00, %ELSE2704 ], [ 0.000000e+00, %ELSE2686 ], [ 0.000000e+00, %ELSE2668 ], [ 0.000000e+00, %ELSE2596 ] |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 303 | %225 = fmul float %temp894.2, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 304 | br label %ENDIF2564 |
| 305 | |
| 306 | ELSE2632: ; preds = %ELSE2596 |
| 307 | br i1 undef, label %ENDIF2594, label %ELSE2650 |
| 308 | |
| 309 | ELSE2650: ; preds = %ELSE2632 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 310 | %226 = fcmp oeq float %temp292.11, %110 |
| 311 | %227 = fcmp olt float %110, %111 |
| 312 | %228 = and i1 %226, %227 |
| 313 | br i1 %228, label %IF2667, label %ELSE2668 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 314 | |
| 315 | IF2667: ; preds = %ELSE2650 |
| 316 | br i1 undef, label %ENDIF2594, label %ELSE2671 |
| 317 | |
| 318 | ELSE2668: ; preds = %ELSE2650 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 319 | %229 = fcmp oeq float %temp292.11, %128 |
| 320 | %230 = fcmp olt float %128, undef |
| 321 | %231 = and i1 %229, %230 |
| 322 | br i1 %231, label %ENDIF2594, label %ELSE2686 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 323 | |
| 324 | ELSE2671: ; preds = %IF2667 |
| 325 | br label %ENDIF2594 |
| 326 | |
| 327 | ELSE2686: ; preds = %ELSE2668 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 328 | %232 = fcmp oeq float %temp292.11, %145 |
| 329 | %233 = fcmp olt float %145, undef |
| 330 | %234 = and i1 %232, %233 |
| 331 | br i1 %234, label %ENDIF2594, label %ELSE2704 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 332 | |
| 333 | ELSE2704: ; preds = %ELSE2686 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 334 | %235 = fcmp oeq float %temp292.11, %180 |
| 335 | %236 = fcmp olt float %180, undef |
| 336 | %237 = and i1 %235, %236 |
| 337 | br i1 %237, label %ENDIF2594, label %ELSE2740 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 338 | |
| 339 | ELSE2740: ; preds = %ELSE2704 |
| 340 | br i1 undef, label %IF2757, label %ELSE2758 |
| 341 | |
| 342 | IF2757: ; preds = %ELSE2740 |
| 343 | br i1 undef, label %ENDIF2594, label %ELSE2761 |
| 344 | |
| 345 | ELSE2758: ; preds = %ELSE2740 |
| 346 | br i1 undef, label %IF2775, label %ENDIF2594 |
| 347 | |
| 348 | ELSE2761: ; preds = %IF2757 |
| 349 | br label %ENDIF2594 |
| 350 | |
| 351 | IF2775: ; preds = %ELSE2758 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 352 | %238 = fcmp olt float undef, undef |
| 353 | br i1 %238, label %ENDIF2594, label %ELSE2779 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 354 | |
| 355 | ELSE2779: ; preds = %IF2775 |
| 356 | br i1 undef, label %ENDIF2594, label %ELSE2782 |
| 357 | |
| 358 | ELSE2782: ; preds = %ELSE2779 |
| 359 | br i1 undef, label %ENDIF2594, label %ELSE2785 |
| 360 | |
| 361 | ELSE2785: ; preds = %ELSE2782 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 362 | %239 = fcmp olt float undef, 0.000000e+00 |
| 363 | br i1 %239, label %ENDIF2594, label %ELSE2788 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 364 | |
| 365 | ELSE2788: ; preds = %ELSE2785 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 366 | %240 = fcmp olt float 0.000000e+00, undef |
| 367 | %.2848 = select i1 %240, float -1.000000e+00, float 1.000000e+00 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 368 | br label %ENDIF2594 |
| 369 | |
| 370 | ELSE2797: ; preds = %ENDIF2564 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 371 | %241 = fsub float %8, undef |
| 372 | %242 = fsub float %9, undef |
| 373 | %243 = fsub float %10, undef |
| 374 | %244 = fmul float %241, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 375 | %245 = fmul float %242, undef |
| 376 | %246 = fmul float %243, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 377 | %247 = fsub float %11, undef |
| 378 | %248 = fsub float %12, undef |
| 379 | %249 = fsub float %13, undef |
| 380 | %250 = fmul float %247, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 381 | %251 = fmul float %248, undef |
| 382 | %252 = fmul float %249, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 383 | %253 = call float @llvm.minnum.f32(float %244, float %250) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 384 | %254 = call float @llvm.minnum.f32(float %245, float %251) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 385 | %255 = call float @llvm.maxnum.f32(float %246, float %252) |
| 386 | %256 = call float @llvm.maxnum.f32(float %253, float %254) |
| 387 | %257 = call float @llvm.maxnum.f32(float %256, float undef) |
| 388 | %258 = call float @llvm.minnum.f32(float undef, float %255) |
| 389 | %259 = fcmp ogt float %257, 0.000000e+00 |
| 390 | %260 = fcmp olt float %257, 1.000000e+00 |
| 391 | %261 = and i1 %259, %260 |
| 392 | %262 = fcmp olt float %257, %258 |
| 393 | %263 = and i1 %261, %262 |
| 394 | br i1 %263, label %ENDIF2795, label %ELSE2800 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 395 | |
| 396 | ENDIF2795: ; preds = %ELSE2824, %ELSE2821, %ELSE2818, %ELSE2815, %ELSE2812, %ELSE2809, %ELSE2806, %ELSE2803, %ELSE2800, %ELSE2797, %ENDIF2564 |
| 397 | br label %LOOP |
| 398 | |
| 399 | ELSE2800: ; preds = %ELSE2797 |
| 400 | br i1 undef, label %ENDIF2795, label %ELSE2803 |
| 401 | |
| 402 | ELSE2803: ; preds = %ELSE2800 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 403 | %264 = fsub float %20, undef |
| 404 | %265 = fsub float %21, undef |
| 405 | %266 = fsub float %22, undef |
| 406 | %267 = fmul float %264, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 407 | %268 = fmul float %265, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 408 | %269 = fmul float %266, 0.000000e+00 |
| 409 | %270 = fsub float %23, undef |
| 410 | %271 = fsub float %24, undef |
| 411 | %272 = fsub float %25, undef |
| 412 | %273 = fmul float %270, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 413 | %274 = fmul float %271, undef |
| 414 | %275 = fmul float %272, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 415 | %276 = call float @llvm.minnum.f32(float %267, float %273) |
| 416 | %277 = call float @llvm.maxnum.f32(float %268, float %274) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 417 | %278 = call float @llvm.maxnum.f32(float %269, float %275) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 418 | %279 = call float @llvm.maxnum.f32(float %276, float undef) |
| 419 | %280 = call float @llvm.maxnum.f32(float %279, float undef) |
| 420 | %281 = call float @llvm.minnum.f32(float undef, float %277) |
| 421 | %282 = call float @llvm.minnum.f32(float %281, float %278) |
| 422 | %283 = fcmp ogt float %280, 0.000000e+00 |
| 423 | %284 = fcmp olt float %280, 1.000000e+00 |
| 424 | %285 = and i1 %283, %284 |
| 425 | %286 = fcmp olt float %280, %282 |
| 426 | %287 = and i1 %285, %286 |
| 427 | br i1 %287, label %ENDIF2795, label %ELSE2806 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 428 | |
| 429 | ELSE2806: ; preds = %ELSE2803 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 430 | %288 = fsub float %26, undef |
| 431 | %289 = fsub float %27, undef |
| 432 | %290 = fsub float %28, undef |
| 433 | %291 = fmul float %288, undef |
| 434 | %292 = fmul float %289, 0.000000e+00 |
| 435 | %293 = fmul float %290, undef |
| 436 | %294 = fsub float %29, undef |
| 437 | %295 = fmul float %294, undef |
| 438 | %296 = call float @llvm.minnum.f32(float %291, float %295) |
| 439 | %297 = call float @llvm.minnum.f32(float %292, float undef) |
| 440 | %298 = call float @llvm.maxnum.f32(float %293, float undef) |
| 441 | %299 = call float @llvm.maxnum.f32(float %296, float %297) |
| 442 | %300 = call float @llvm.maxnum.f32(float %299, float undef) |
| 443 | %301 = call float @llvm.minnum.f32(float undef, float %298) |
| 444 | %302 = fcmp ogt float %300, 0.000000e+00 |
| 445 | %303 = fcmp olt float %300, 1.000000e+00 |
| 446 | %304 = and i1 %302, %303 |
| 447 | %305 = fcmp olt float %300, %301 |
| 448 | %306 = and i1 %304, %305 |
| 449 | br i1 %306, label %ENDIF2795, label %ELSE2809 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 450 | |
| 451 | ELSE2809: ; preds = %ELSE2806 |
| 452 | br i1 undef, label %ENDIF2795, label %ELSE2812 |
| 453 | |
| 454 | ELSE2812: ; preds = %ELSE2809 |
| 455 | br i1 undef, label %ENDIF2795, label %ELSE2815 |
| 456 | |
| 457 | ELSE2815: ; preds = %ELSE2812 |
| 458 | br i1 undef, label %ENDIF2795, label %ELSE2818 |
| 459 | |
| 460 | ELSE2818: ; preds = %ELSE2815 |
| 461 | br i1 undef, label %ENDIF2795, label %ELSE2821 |
| 462 | |
| 463 | ELSE2821: ; preds = %ELSE2818 |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 464 | %307 = fsub float %56, undef |
| 465 | %308 = fsub float %57, undef |
| 466 | %309 = fsub float %58, undef |
| 467 | %310 = fmul float %307, undef |
| 468 | %311 = fmul float %308, 0.000000e+00 |
| 469 | %312 = fmul float %309, undef |
| 470 | %313 = fsub float %59, undef |
| 471 | %314 = fsub float %60, undef |
| 472 | %315 = fsub float %61, undef |
| 473 | %316 = fmul float %313, undef |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 474 | %317 = fmul float %314, undef |
| 475 | %318 = fmul float %315, undef |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 476 | %319 = call float @llvm.maxnum.f32(float %310, float %316) |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 477 | %320 = call float @llvm.maxnum.f32(float %311, float %317) |
| 478 | %321 = call float @llvm.maxnum.f32(float %312, float %318) |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 479 | %322 = call float @llvm.minnum.f32(float %319, float %320) |
| 480 | %323 = call float @llvm.minnum.f32(float %322, float %321) |
| 481 | %324 = fcmp ogt float undef, 0.000000e+00 |
| 482 | %325 = fcmp olt float undef, 1.000000e+00 |
| 483 | %326 = and i1 %324, %325 |
| 484 | %327 = fcmp olt float undef, %323 |
| 485 | %328 = and i1 %326, %327 |
| 486 | br i1 %328, label %ENDIF2795, label %ELSE2824 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 487 | |
| 488 | ELSE2824: ; preds = %ELSE2821 |
| 489 | %.2849 = select i1 undef, float 0.000000e+00, float 1.000000e+00 |
| 490 | br label %ENDIF2795 |
| 491 | } |
| 492 | |
| Tom Stellard | bc4497b | 2016-02-12 23:45:29 +0000 | [diff] [blame] | 493 | declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #2 |
| 494 | |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 495 | ; Function Attrs: nounwind readnone |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 496 | declare float @llvm.SI.load.const(<16 x i8>, i32) #2 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 497 | |
| Matt Arsenault | 15fbe49 | 2016-01-20 21:05:49 +0000 | [diff] [blame] | 498 | ; Function Attrs: nounwind readnone |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 499 | declare float @llvm.floor.f32(float) #2 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 500 | |
| 501 | ; Function Attrs: nounwind readnone |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 502 | declare float @llvm.sqrt.f32(float) #2 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 503 | |
| 504 | ; Function Attrs: nounwind readnone |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 505 | declare float @llvm.minnum.f32(float, float) #2 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 506 | |
| 507 | ; Function Attrs: nounwind readnone |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 508 | declare float @llvm.maxnum.f32(float, float) #2 |
| Tom Stellard | 28d13a4 | 2015-05-12 17:13:02 +0000 | [diff] [blame] | 509 | |
| 510 | declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) |
| 511 | |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 512 | attributes #0 = { alwaysinline nounwind readnone } |
| Nicolai Haehnle | df3a20c | 2016-04-06 19:40:20 +0000 | [diff] [blame] | 513 | attributes #1 = { "enable-no-nans-fp-math"="true" } |
| Matt Arsenault | 7713162 | 2016-01-23 05:42:38 +0000 | [diff] [blame] | 514 | attributes #2 = { nounwind readnone } |