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gerrit-public.fairphone.software / toolchain / llvm-project / bc041b82d44b51a3b7da79c38e4052e28ff8011c / . / llvm / test / CodeGen / X86 / merge-store-partially-alias-loads.ll
blob: 735e64a076d00aa26b3f8068be24fb84676dcdef [file] [log] [blame]
Matt Arsenaultc721df02015-09-24 07:22:38 +0000[diff] [blame]1; REQUIRES: asserts
2; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck -check-prefix=X86 %s
3; RUN: llc -march=x86-64 -mtriple=x86_64-unknown-linux-gnu -debug-only=isel < %s 2>&1 | FileCheck -check-prefix=DBGDAG %s
4
5; It's OK to merge the load / store of the first 2 components, but
6; they must not be placed on the same chain after merging.
7
8; X86-LABEL: {{^}}merge_store_partial_overlap_load:
Kevin B. Smithe0a6fc32016-04-08 18:58:29 +0000[diff] [blame]9; X86-DAG: movzwl ([[BASEREG:%[a-z]+]]), %e[[LO2:[a-z]+]]
Matt Arsenaultc721df02015-09-24 07:22:38 +0000[diff] [blame]10; X86-DAG: movb 2([[BASEREG]]), [[HI1:%[a-z]+]]
11
Kevin B. Smithe0a6fc32016-04-08 18:58:29 +0000[diff] [blame]12; X86-NEXT: movw %[[LO2]], 1([[BASEREG]])
Matt Arsenaultc721df02015-09-24 07:22:38 +0000[diff] [blame]13; X86-NEXT: movb [[HI1]], 3([[BASEREG]])
14; X86-NEXT: retq
15
16; DBGDAG-LABEL: Optimized lowered selection DAG: BB#0 'merge_store_partial_overlap_load:'
17; DBGDAG: [[ENTRYTOKEN:t[0-9]+]]: ch = EntryToken
Matt Arsenaultc721df02015-09-24 07:22:38 +0000[diff] [blame]18; DBGDAG-DAG: [[BASEPTR:t[0-9]+]]: i64,ch = CopyFromReg [[ENTRYTOKEN]],
Matthias Brauna3b701f2015-09-25 22:27:02 +0000[diff] [blame]19; DBGDAG-DAG: [[ADDPTR:t[0-9]+]]: i64 = add [[BASEPTR]], Constant:i64<2>
Matt Arsenaultc721df02015-09-24 07:22:38 +0000[diff] [blame]20
Matthias Brauna3b701f2015-09-25 22:27:02 +0000[diff] [blame]21; DBGDAG-DAG: [[LD2:t[0-9]+]]: i16,ch = load<LD2[%tmp81](align=1)> [[ENTRYTOKEN]], [[BASEPTR]], undef:i64
22; DBGDAG-DAG: [[LD1:t[0-9]+]]: i8,ch = load<LD1[%tmp12]> [[ENTRYTOKEN]], [[ADDPTR]], undef:i64
Matt Arsenaultc721df02015-09-24 07:22:38 +0000[diff] [blame]23
24; DBGDAG: [[LOADTOKEN:t[0-9]+]]: ch = TokenFactor [[LD2]]:1, [[LD1]]:1
25
Matthias Brauna3b701f2015-09-25 22:27:02 +0000[diff] [blame]26; DBGDAG-DAG: [[ST2:t[0-9]+]]: ch = store<ST2[%tmp10](align=1)> [[LOADTOKEN]], [[LD2]], t{{[0-9]+}}, undef:i64
27; DBGDAG-DAG: [[ST1:t[0-9]+]]: ch = store<ST1[%tmp14]> [[ST2]], [[LD1]], t{{[0-9]+}}, undef:i64
Matt Arsenaultc721df02015-09-24 07:22:38 +0000[diff] [blame]28; DBGDAG: X86ISD::RET_FLAG [[ST1]],
29
30; DBGDAG: Type-legalized selection DAG: BB#0 'merge_store_partial_overlap_load:'
31define void @merge_store_partial_overlap_load([4 x i8]* %tmp) {
32 %tmp8 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 0
33 %tmp10 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 1
34 %tmp12 = getelementptr inbounds [4 x i8], [4 x i8]* %tmp, i32 0, i8 2
35 %tmp14 = getelementptr [4 x i8], [4 x i8]* %tmp, i32 0, i8 3
36
37 %tmp9 = load i8, i8* %tmp8, align 1 ; base + 0
38 %tmp11 = load i8, i8* %tmp10, align 1 ; base + 1
39 %tmp13 = load i8, i8* %tmp12, align 1 ; base + 2
40
41 store i8 %tmp9, i8* %tmp10, align 1 ; base + 1
42 store i8 %tmp11, i8* %tmp12, align 1 ; base + 2
43 store i8 %tmp13, i8* %tmp14, align 1 ; base + 3
44
45; Should emit
46; load base + 0, base + 1
47; store base + 1, base + 2
48; load base + 2
49; store base + 3
50
51 ret void
52}