Simon Pilgrim | aab59b7 | 2016-03-31 20:26:30 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE2 |
| 3 | ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+ssse3 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSSE3 |
| 4 | ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+sse4.1 | FileCheck %s --check-prefix=ALL --check-prefix=SSE --check-prefix=SSE41 |
| 5 | ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX1 |
| 6 | ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 -mattr=+avx2 | FileCheck %s --check-prefix=ALL --check-prefix=AVX --check-prefix=AVX2 |
| 7 | |
| 8 | ; |
| 9 | ; Unary shuffle indices from registers |
| 10 | ; |
| 11 | |
| 12 | define <2 x double> @var_shuffle_v2f64_v2f64_xx_i64(<2 x double> %x, i64 %i0, i64 %i1) nounwind { |
| 13 | ; SSE-LABEL: var_shuffle_v2f64_v2f64_xx_i64: |
| 14 | ; SSE: # BB#0: |
| 15 | ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 16 | ; SSE-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero |
| 17 | ; SSE-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0] |
| 18 | ; SSE-NEXT: retq |
| 19 | ; |
| 20 | ; AVX-LABEL: var_shuffle_v2f64_v2f64_xx_i64: |
| 21 | ; AVX: # BB#0: |
| 22 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 23 | ; AVX-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero |
| 24 | ; AVX-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0] |
| 25 | ; AVX-NEXT: retq |
| 26 | %x0 = extractelement <2 x double> %x, i64 %i0 |
| 27 | %x1 = extractelement <2 x double> %x, i64 %i1 |
| 28 | %r0 = insertelement <2 x double> undef, double %x0, i32 0 |
| 29 | %r1 = insertelement <2 x double> %r0, double %x1, i32 1 |
| 30 | ret <2 x double> %r1 |
| 31 | } |
| 32 | |
| 33 | define <2 x i64> @var_shuffle_v2i64_v2i64_xx_i64(<2 x i64> %x, i32 %i0, i32 %i1) nounwind { |
| 34 | ; SSE-LABEL: var_shuffle_v2i64_v2i64_xx_i64: |
| 35 | ; SSE: # BB#0: |
| 36 | ; SSE-NEXT: movslq %edi, %rax |
| 37 | ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 38 | ; SSE-NEXT: movslq %esi, %rcx |
| 39 | ; SSE-NEXT: movq {{.*#+}} xmm0 = mem[0],zero |
| 40 | ; SSE-NEXT: movq {{.*#+}} xmm1 = mem[0],zero |
| 41 | ; SSE-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] |
| 42 | ; SSE-NEXT: retq |
| 43 | ; |
| 44 | ; AVX-LABEL: var_shuffle_v2i64_v2i64_xx_i64: |
| 45 | ; AVX: # BB#0: |
| 46 | ; AVX-NEXT: movslq %edi, %rax |
| 47 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 48 | ; AVX-NEXT: movslq %esi, %rcx |
| 49 | ; AVX-NEXT: vmovq {{.*#+}} xmm0 = mem[0],zero |
| 50 | ; AVX-NEXT: vmovq {{.*#+}} xmm1 = mem[0],zero |
| 51 | ; AVX-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] |
| 52 | ; AVX-NEXT: retq |
| 53 | %x0 = extractelement <2 x i64> %x, i32 %i0 |
| 54 | %x1 = extractelement <2 x i64> %x, i32 %i1 |
| 55 | %r0 = insertelement <2 x i64> undef, i64 %x0, i32 0 |
| 56 | %r1 = insertelement <2 x i64> %r0, i64 %x1, i32 1 |
| 57 | ret <2 x i64> %r1 |
| 58 | } |
| 59 | |
| 60 | define <4 x float> @var_shuffle_v4f32_v4f32_xxxx_i32(<4 x float> %x, i32 %i0, i32 %i1, i32 %i2, i32 %i3) nounwind { |
| 61 | ; SSE2-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: |
| 62 | ; SSE2: # BB#0: |
| 63 | ; SSE2-NEXT: movslq %edi, %rax |
| 64 | ; SSE2-NEXT: movslq %esi, %rsi |
| 65 | ; SSE2-NEXT: movslq %edx, %rdx |
| 66 | ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 67 | ; SSE2-NEXT: movslq %ecx, %rcx |
| 68 | ; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 69 | ; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 70 | ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 71 | ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 72 | ; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 73 | ; SSE2-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] |
| 74 | ; SSE2-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] |
| 75 | ; SSE2-NEXT: retq |
| 76 | ; |
| 77 | ; SSSE3-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: |
| 78 | ; SSSE3: # BB#0: |
| 79 | ; SSSE3-NEXT: movslq %edi, %rax |
| 80 | ; SSSE3-NEXT: movslq %esi, %rsi |
| 81 | ; SSSE3-NEXT: movslq %edx, %rdx |
| 82 | ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 83 | ; SSSE3-NEXT: movslq %ecx, %rcx |
| 84 | ; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 85 | ; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 86 | ; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 87 | ; SSSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 88 | ; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 89 | ; SSSE3-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] |
| 90 | ; SSSE3-NEXT: unpcklps {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] |
| 91 | ; SSSE3-NEXT: retq |
| 92 | ; |
| 93 | ; SSE41-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: |
| 94 | ; SSE41: # BB#0: |
| 95 | ; SSE41-NEXT: movslq %edi, %rax |
| 96 | ; SSE41-NEXT: movslq %esi, %rsi |
| 97 | ; SSE41-NEXT: movslq %edx, %rdx |
| 98 | ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 99 | ; SSE41-NEXT: movslq %ecx, %rcx |
| 100 | ; SSE41-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 101 | ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] |
| 102 | ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] |
| 103 | ; SSE41-NEXT: insertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] |
| 104 | ; SSE41-NEXT: retq |
| 105 | ; |
| 106 | ; AVX-LABEL: var_shuffle_v4f32_v4f32_xxxx_i32: |
| 107 | ; AVX: # BB#0: |
| 108 | ; AVX-NEXT: movslq %edi, %rax |
| 109 | ; AVX-NEXT: movslq %esi, %rsi |
| 110 | ; AVX-NEXT: movslq %edx, %rdx |
| 111 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 112 | ; AVX-NEXT: movslq %ecx, %rcx |
| 113 | ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 114 | ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0],mem[0],xmm0[2,3] |
| 115 | ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1],mem[0],xmm0[3] |
| 116 | ; AVX-NEXT: vinsertps {{.*#+}} xmm0 = xmm0[0,1,2],mem[0] |
| 117 | ; AVX-NEXT: retq |
| 118 | %x0 = extractelement <4 x float> %x, i32 %i0 |
| 119 | %x1 = extractelement <4 x float> %x, i32 %i1 |
| 120 | %x2 = extractelement <4 x float> %x, i32 %i2 |
| 121 | %x3 = extractelement <4 x float> %x, i32 %i3 |
| 122 | %r0 = insertelement <4 x float> undef, float %x0, i32 0 |
| 123 | %r1 = insertelement <4 x float> %r0, float %x1, i32 1 |
| 124 | %r2 = insertelement <4 x float> %r1, float %x2, i32 2 |
| 125 | %r3 = insertelement <4 x float> %r2, float %x3, i32 3 |
| 126 | ret <4 x float> %r3 |
| 127 | } |
| 128 | |
| 129 | define <4 x i32> @var_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32 %i0, i32 %i1, i32 %i2, i32 %i3) nounwind { |
| 130 | ; SSE2-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: |
| 131 | ; SSE2: # BB#0: |
| 132 | ; SSE2-NEXT: movslq %edi, %rax |
| 133 | ; SSE2-NEXT: movslq %esi, %rsi |
| 134 | ; SSE2-NEXT: movslq %edx, %rdx |
| 135 | ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 136 | ; SSE2-NEXT: movslq %ecx, %rcx |
| 137 | ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 138 | ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 139 | ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 140 | ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 141 | ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 142 | ; SSE2-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] |
| 143 | ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] |
| 144 | ; SSE2-NEXT: retq |
| 145 | ; |
| 146 | ; SSSE3-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: |
| 147 | ; SSSE3: # BB#0: |
| 148 | ; SSSE3-NEXT: movslq %edi, %rax |
| 149 | ; SSSE3-NEXT: movslq %esi, %rsi |
| 150 | ; SSSE3-NEXT: movslq %edx, %rdx |
| 151 | ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 152 | ; SSSE3-NEXT: movslq %ecx, %rcx |
| 153 | ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 154 | ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 155 | ; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 156 | ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 157 | ; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 158 | ; SSSE3-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] |
| 159 | ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] |
| 160 | ; SSSE3-NEXT: retq |
| 161 | ; |
| 162 | ; SSE41-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: |
| 163 | ; SSE41: # BB#0: |
| 164 | ; SSE41-NEXT: movslq %edi, %rax |
| 165 | ; SSE41-NEXT: movslq %esi, %rsi |
| 166 | ; SSE41-NEXT: movslq %edx, %rdx |
| 167 | ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 168 | ; SSE41-NEXT: movslq %ecx, %rcx |
| 169 | ; SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 170 | ; SSE41-NEXT: pinsrd $1, -24(%rsp,%rsi,4), %xmm0 |
| 171 | ; SSE41-NEXT: pinsrd $2, -24(%rsp,%rdx,4), %xmm0 |
| 172 | ; SSE41-NEXT: pinsrd $3, -24(%rsp,%rcx,4), %xmm0 |
| 173 | ; SSE41-NEXT: retq |
| 174 | ; |
| 175 | ; AVX-LABEL: var_shuffle_v4i32_v4i32_xxxx_i32: |
| 176 | ; AVX: # BB#0: |
| 177 | ; AVX-NEXT: movslq %edi, %rax |
| 178 | ; AVX-NEXT: movslq %esi, %rsi |
| 179 | ; AVX-NEXT: movslq %edx, %rdx |
| 180 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 181 | ; AVX-NEXT: movslq %ecx, %rcx |
| 182 | ; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 183 | ; AVX-NEXT: vpinsrd $1, -24(%rsp,%rsi,4), %xmm0, %xmm0 |
| 184 | ; AVX-NEXT: vpinsrd $2, -24(%rsp,%rdx,4), %xmm0, %xmm0 |
| 185 | ; AVX-NEXT: vpinsrd $3, -24(%rsp,%rcx,4), %xmm0, %xmm0 |
| 186 | ; AVX-NEXT: retq |
| 187 | %x0 = extractelement <4 x i32> %x, i32 %i0 |
| 188 | %x1 = extractelement <4 x i32> %x, i32 %i1 |
| 189 | %x2 = extractelement <4 x i32> %x, i32 %i2 |
| 190 | %x3 = extractelement <4 x i32> %x, i32 %i3 |
| 191 | %r0 = insertelement <4 x i32> undef, i32 %x0, i32 0 |
| 192 | %r1 = insertelement <4 x i32> %r0, i32 %x1, i32 1 |
| 193 | %r2 = insertelement <4 x i32> %r1, i32 %x2, i32 2 |
| 194 | %r3 = insertelement <4 x i32> %r2, i32 %x3, i32 3 |
| 195 | ret <4 x i32> %r3 |
| 196 | } |
| 197 | |
| 198 | define <8 x i16> @var_shuffle_v8i16_v8i16_xxxxxxxx_i16(<8 x i16> %x, i16 %i0, i16 %i1, i16 %i2, i16 %i3, i16 %i4, i16 %i5, i16 %i6, i16 %i7) nounwind { |
| 199 | ; SSE2-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: |
| 200 | ; SSE2: # BB#0: |
| 201 | ; SSE2-NEXT: movswq %di, %rax |
| 202 | ; SSE2-NEXT: movswq %si, %rsi |
| 203 | ; SSE2-NEXT: movswq %dx, %rdx |
| 204 | ; SSE2-NEXT: movswq %cx, %r10 |
| 205 | ; SSE2-NEXT: movswq %r8w, %r11 |
| 206 | ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 207 | ; SSE2-NEXT: movswq %r9w, %r8 |
| 208 | ; SSE2-NEXT: movswq {{[0-9]+}}(%rsp), %rcx |
| 209 | ; SSE2-NEXT: movswq {{[0-9]+}}(%rsp), %rdi |
| 210 | ; SSE2-NEXT: movzwl -24(%rsp,%rcx,2), %ecx |
| 211 | ; SSE2-NEXT: movzwl -24(%rsp,%rdi,2), %edi |
| 212 | ; SSE2-NEXT: movzwl -24(%rsp,%rax,2), %eax |
| 213 | ; SSE2-NEXT: movzwl -24(%rsp,%rsi,2), %esi |
| 214 | ; SSE2-NEXT: movd %ecx, %xmm0 |
| 215 | ; SSE2-NEXT: movzwl -24(%rsp,%rdx,2), %ecx |
| 216 | ; SSE2-NEXT: movd %ecx, %xmm1 |
| 217 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] |
| 218 | ; SSE2-NEXT: movzwl -24(%rsp,%r10,2), %ecx |
| 219 | ; SSE2-NEXT: movd %eax, %xmm0 |
| 220 | ; SSE2-NEXT: movzwl -24(%rsp,%r11,2), %eax |
| 221 | ; SSE2-NEXT: movd %eax, %xmm2 |
| 222 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] |
| 223 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] |
| 224 | ; SSE2-NEXT: movd %edi, %xmm1 |
| 225 | ; SSE2-NEXT: movd %ecx, %xmm2 |
| 226 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] |
| 227 | ; SSE2-NEXT: movd %esi, %xmm1 |
| 228 | ; SSE2-NEXT: movzwl -24(%rsp,%r8,2), %eax |
| 229 | ; SSE2-NEXT: movd %eax, %xmm3 |
| 230 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3] |
| 231 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] |
| 232 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] |
| 233 | ; SSE2-NEXT: retq |
| 234 | ; |
| 235 | ; SSSE3-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: |
| 236 | ; SSSE3: # BB#0: |
| 237 | ; SSSE3-NEXT: movswq %di, %rax |
| 238 | ; SSSE3-NEXT: movswq %si, %rsi |
| 239 | ; SSSE3-NEXT: movswq %dx, %rdx |
| 240 | ; SSSE3-NEXT: movswq %cx, %r10 |
| 241 | ; SSSE3-NEXT: movswq %r8w, %r11 |
| 242 | ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 243 | ; SSSE3-NEXT: movswq %r9w, %r8 |
| 244 | ; SSSE3-NEXT: movswq {{[0-9]+}}(%rsp), %rcx |
| 245 | ; SSSE3-NEXT: movswq {{[0-9]+}}(%rsp), %rdi |
| 246 | ; SSSE3-NEXT: movzwl -24(%rsp,%rcx,2), %ecx |
| 247 | ; SSSE3-NEXT: movzwl -24(%rsp,%rdi,2), %edi |
| 248 | ; SSSE3-NEXT: movzwl -24(%rsp,%rax,2), %eax |
| 249 | ; SSSE3-NEXT: movzwl -24(%rsp,%rsi,2), %esi |
| 250 | ; SSSE3-NEXT: movd %ecx, %xmm0 |
| 251 | ; SSSE3-NEXT: movzwl -24(%rsp,%rdx,2), %ecx |
| 252 | ; SSSE3-NEXT: movd %ecx, %xmm1 |
| 253 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] |
| 254 | ; SSSE3-NEXT: movzwl -24(%rsp,%r10,2), %ecx |
| 255 | ; SSSE3-NEXT: movd %eax, %xmm0 |
| 256 | ; SSSE3-NEXT: movzwl -24(%rsp,%r11,2), %eax |
| 257 | ; SSSE3-NEXT: movd %eax, %xmm2 |
| 258 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] |
| 259 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] |
| 260 | ; SSSE3-NEXT: movd %edi, %xmm1 |
| 261 | ; SSSE3-NEXT: movd %ecx, %xmm2 |
| 262 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] |
| 263 | ; SSSE3-NEXT: movd %esi, %xmm1 |
| 264 | ; SSSE3-NEXT: movzwl -24(%rsp,%r8,2), %eax |
| 265 | ; SSSE3-NEXT: movd %eax, %xmm3 |
| 266 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1],xmm1[2],xmm3[2],xmm1[3],xmm3[3] |
| 267 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3] |
| 268 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] |
| 269 | ; SSSE3-NEXT: retq |
| 270 | ; |
| 271 | ; SSE41-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: |
| 272 | ; SSE41: # BB#0: |
| 273 | ; SSE41-NEXT: pushq %rbx |
| 274 | ; SSE41-NEXT: movswq %di, %rax |
| 275 | ; SSE41-NEXT: movswq %si, %rbx |
| 276 | ; SSE41-NEXT: movswq %dx, %r11 |
| 277 | ; SSE41-NEXT: movswq %cx, %r10 |
| 278 | ; SSE41-NEXT: movswq %r8w, %rdi |
| 279 | ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 280 | ; SSE41-NEXT: movswq %r9w, %rcx |
| 281 | ; SSE41-NEXT: movswq {{[0-9]+}}(%rsp), %rdx |
| 282 | ; SSE41-NEXT: movswq {{[0-9]+}}(%rsp), %rsi |
| 283 | ; SSE41-NEXT: movzwl -16(%rsp,%rdx,2), %edx |
| 284 | ; SSE41-NEXT: movzwl -16(%rsp,%rsi,2), %esi |
| 285 | ; SSE41-NEXT: movzwl -16(%rsp,%rax,2), %eax |
| 286 | ; SSE41-NEXT: movd %eax, %xmm0 |
| 287 | ; SSE41-NEXT: pinsrw $1, -16(%rsp,%rbx,2), %xmm0 |
| 288 | ; SSE41-NEXT: pinsrw $2, -16(%rsp,%r11,2), %xmm0 |
| 289 | ; SSE41-NEXT: pinsrw $3, -16(%rsp,%r10,2), %xmm0 |
| 290 | ; SSE41-NEXT: pinsrw $4, -16(%rsp,%rdi,2), %xmm0 |
| 291 | ; SSE41-NEXT: pinsrw $5, -16(%rsp,%rcx,2), %xmm0 |
| 292 | ; SSE41-NEXT: pinsrw $6, %edx, %xmm0 |
| 293 | ; SSE41-NEXT: pinsrw $7, %esi, %xmm0 |
| 294 | ; SSE41-NEXT: popq %rbx |
| 295 | ; SSE41-NEXT: retq |
| 296 | ; |
| 297 | ; AVX-LABEL: var_shuffle_v8i16_v8i16_xxxxxxxx_i16: |
| 298 | ; AVX: # BB#0: |
| 299 | ; AVX-NEXT: pushq %r14 |
| 300 | ; AVX-NEXT: pushq %rbx |
| 301 | ; AVX-NEXT: movswq %di, %r10 |
| 302 | ; AVX-NEXT: movswq %si, %r11 |
| 303 | ; AVX-NEXT: movswq %dx, %r14 |
| 304 | ; AVX-NEXT: movswq %cx, %rcx |
| 305 | ; AVX-NEXT: movswq %r8w, %rdi |
| 306 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 307 | ; AVX-NEXT: movswq %r9w, %rax |
| 308 | ; AVX-NEXT: movswq {{[0-9]+}}(%rsp), %rsi |
| 309 | ; AVX-NEXT: movswq {{[0-9]+}}(%rsp), %rdx |
| 310 | ; AVX-NEXT: movzwl -24(%rsp,%rsi,2), %esi |
| 311 | ; AVX-NEXT: movzwl -24(%rsp,%rdx,2), %edx |
| 312 | ; AVX-NEXT: movzwl -24(%rsp,%r10,2), %ebx |
| 313 | ; AVX-NEXT: vmovd %ebx, %xmm0 |
| 314 | ; AVX-NEXT: vpinsrw $1, -24(%rsp,%r11,2), %xmm0, %xmm0 |
| 315 | ; AVX-NEXT: vpinsrw $2, -24(%rsp,%r14,2), %xmm0, %xmm0 |
| 316 | ; AVX-NEXT: vpinsrw $3, -24(%rsp,%rcx,2), %xmm0, %xmm0 |
| 317 | ; AVX-NEXT: vpinsrw $4, -24(%rsp,%rdi,2), %xmm0, %xmm0 |
| 318 | ; AVX-NEXT: vpinsrw $5, -24(%rsp,%rax,2), %xmm0, %xmm0 |
| 319 | ; AVX-NEXT: vpinsrw $6, %esi, %xmm0, %xmm0 |
| 320 | ; AVX-NEXT: vpinsrw $7, %edx, %xmm0, %xmm0 |
| 321 | ; AVX-NEXT: popq %rbx |
| 322 | ; AVX-NEXT: popq %r14 |
| 323 | ; AVX-NEXT: retq |
| 324 | %x0 = extractelement <8 x i16> %x, i16 %i0 |
| 325 | %x1 = extractelement <8 x i16> %x, i16 %i1 |
| 326 | %x2 = extractelement <8 x i16> %x, i16 %i2 |
| 327 | %x3 = extractelement <8 x i16> %x, i16 %i3 |
| 328 | %x4 = extractelement <8 x i16> %x, i16 %i4 |
| 329 | %x5 = extractelement <8 x i16> %x, i16 %i5 |
| 330 | %x6 = extractelement <8 x i16> %x, i16 %i6 |
| 331 | %x7 = extractelement <8 x i16> %x, i16 %i7 |
| 332 | %r0 = insertelement <8 x i16> undef, i16 %x0, i32 0 |
| 333 | %r1 = insertelement <8 x i16> %r0, i16 %x1, i32 1 |
| 334 | %r2 = insertelement <8 x i16> %r1, i16 %x2, i32 2 |
| 335 | %r3 = insertelement <8 x i16> %r2, i16 %x3, i32 3 |
| 336 | %r4 = insertelement <8 x i16> %r3, i16 %x4, i32 4 |
| 337 | %r5 = insertelement <8 x i16> %r4, i16 %x5, i32 5 |
| 338 | %r6 = insertelement <8 x i16> %r5, i16 %x6, i32 6 |
| 339 | %r7 = insertelement <8 x i16> %r6, i16 %x7, i32 7 |
| 340 | ret <8 x i16> %r7 |
| 341 | } |
| 342 | |
| 343 | define <16 x i8> @var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8 %i0, i8 %i1, i8 %i2, i8 %i3, i8 %i4, i8 %i5, i8 %i6, i8 %i7, i8 %i8, i8 %i9, i8 %i10, i8 %i11, i8 %i12, i8 %i13, i8 %i14, i8 %i15) nounwind { |
| 344 | ; SSE2-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 345 | ; SSE2: # BB#0: |
| 346 | ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 347 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %r10 |
| 348 | ; SSE2-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 |
| 349 | ; SSE2-NEXT: movzbl (%r10,%r11), %eax |
| 350 | ; SSE2-NEXT: movd %eax, %xmm15 |
| 351 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 352 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 353 | ; SSE2-NEXT: movd %eax, %xmm8 |
| 354 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 355 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 356 | ; SSE2-NEXT: movd %eax, %xmm9 |
| 357 | ; SSE2-NEXT: movsbq %dl, %rax |
| 358 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 359 | ; SSE2-NEXT: movd %eax, %xmm3 |
| 360 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 361 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 362 | ; SSE2-NEXT: movd %eax, %xmm10 |
| 363 | ; SSE2-NEXT: movsbq %dil, %rax |
| 364 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 365 | ; SSE2-NEXT: movd %eax, %xmm0 |
| 366 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 367 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 368 | ; SSE2-NEXT: movd %eax, %xmm11 |
| 369 | ; SSE2-NEXT: movsbq %r8b, %rax |
| 370 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 371 | ; SSE2-NEXT: movd %eax, %xmm7 |
| 372 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 373 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 374 | ; SSE2-NEXT: movd %eax, %xmm2 |
| 375 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 376 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 377 | ; SSE2-NEXT: movd %eax, %xmm12 |
| 378 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 379 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 380 | ; SSE2-NEXT: movd %eax, %xmm13 |
| 381 | ; SSE2-NEXT: movsbq %cl, %rax |
| 382 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 383 | ; SSE2-NEXT: movd %eax, %xmm6 |
| 384 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 385 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 386 | ; SSE2-NEXT: movd %eax, %xmm14 |
| 387 | ; SSE2-NEXT: movsbq %sil, %rax |
| 388 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 389 | ; SSE2-NEXT: movd %eax, %xmm5 |
| 390 | ; SSE2-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 391 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 392 | ; SSE2-NEXT: movd %eax, %xmm4 |
| 393 | ; SSE2-NEXT: movsbq %r9b, %rax |
| 394 | ; SSE2-NEXT: movzbl (%rax,%r11), %eax |
| 395 | ; SSE2-NEXT: movd %eax, %xmm1 |
| 396 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7] |
| 397 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7] |
| 398 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3],xmm3[4],xmm15[4],xmm3[5],xmm15[5],xmm3[6],xmm15[6],xmm3[7],xmm15[7] |
| 399 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm10[0],xmm0[1],xmm10[1],xmm0[2],xmm10[2],xmm0[3],xmm10[3],xmm0[4],xmm10[4],xmm0[5],xmm10[5],xmm0[6],xmm10[6],xmm0[7],xmm10[7] |
| 400 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3],xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] |
| 401 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3],xmm0[4],xmm7[4],xmm0[5],xmm7[5],xmm0[6],xmm7[6],xmm0[7],xmm7[7] |
| 402 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] |
| 403 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],xmm12[1],xmm2[2],xmm12[2],xmm2[3],xmm12[3],xmm2[4],xmm12[4],xmm2[5],xmm12[5],xmm2[6],xmm12[6],xmm2[7],xmm12[7] |
| 404 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],xmm13[1],xmm6[2],xmm13[2],xmm6[3],xmm13[3],xmm6[4],xmm13[4],xmm6[5],xmm13[5],xmm6[6],xmm13[6],xmm6[7],xmm13[7] |
| 405 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3],xmm6[4],xmm2[4],xmm6[5],xmm2[5],xmm6[6],xmm2[6],xmm6[7],xmm2[7] |
| 406 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm14[0],xmm5[1],xmm14[1],xmm5[2],xmm14[2],xmm5[3],xmm14[3],xmm5[4],xmm14[4],xmm5[5],xmm14[5],xmm5[6],xmm14[6],xmm5[7],xmm14[7] |
| 407 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] |
| 408 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3],xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] |
| 409 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3],xmm5[4],xmm6[4],xmm5[5],xmm6[5],xmm5[6],xmm6[6],xmm5[7],xmm6[7] |
| 410 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3],xmm0[4],xmm5[4],xmm0[5],xmm5[5],xmm0[6],xmm5[6],xmm0[7],xmm5[7] |
| 411 | ; SSE2-NEXT: retq |
| 412 | ; |
| 413 | ; SSSE3-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 414 | ; SSSE3: # BB#0: |
| 415 | ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 416 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %r10 |
| 417 | ; SSSE3-NEXT: leaq -{{[0-9]+}}(%rsp), %r11 |
| 418 | ; SSSE3-NEXT: movzbl (%r10,%r11), %eax |
| 419 | ; SSSE3-NEXT: movd %eax, %xmm15 |
| 420 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 421 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 422 | ; SSSE3-NEXT: movd %eax, %xmm8 |
| 423 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 424 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 425 | ; SSSE3-NEXT: movd %eax, %xmm9 |
| 426 | ; SSSE3-NEXT: movsbq %dl, %rax |
| 427 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 428 | ; SSSE3-NEXT: movd %eax, %xmm3 |
| 429 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 430 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 431 | ; SSSE3-NEXT: movd %eax, %xmm10 |
| 432 | ; SSSE3-NEXT: movsbq %dil, %rax |
| 433 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 434 | ; SSSE3-NEXT: movd %eax, %xmm0 |
| 435 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 436 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 437 | ; SSSE3-NEXT: movd %eax, %xmm11 |
| 438 | ; SSSE3-NEXT: movsbq %r8b, %rax |
| 439 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 440 | ; SSSE3-NEXT: movd %eax, %xmm7 |
| 441 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 442 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 443 | ; SSSE3-NEXT: movd %eax, %xmm2 |
| 444 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 445 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 446 | ; SSSE3-NEXT: movd %eax, %xmm12 |
| 447 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 448 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 449 | ; SSSE3-NEXT: movd %eax, %xmm13 |
| 450 | ; SSSE3-NEXT: movsbq %cl, %rax |
| 451 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 452 | ; SSSE3-NEXT: movd %eax, %xmm6 |
| 453 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 454 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 455 | ; SSSE3-NEXT: movd %eax, %xmm14 |
| 456 | ; SSSE3-NEXT: movsbq %sil, %rax |
| 457 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 458 | ; SSSE3-NEXT: movd %eax, %xmm5 |
| 459 | ; SSSE3-NEXT: movsbq {{[0-9]+}}(%rsp), %rax |
| 460 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 461 | ; SSSE3-NEXT: movd %eax, %xmm4 |
| 462 | ; SSSE3-NEXT: movsbq %r9b, %rax |
| 463 | ; SSSE3-NEXT: movzbl (%rax,%r11), %eax |
| 464 | ; SSSE3-NEXT: movd %eax, %xmm1 |
| 465 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm15 = xmm15[0],xmm8[0],xmm15[1],xmm8[1],xmm15[2],xmm8[2],xmm15[3],xmm8[3],xmm15[4],xmm8[4],xmm15[5],xmm8[5],xmm15[6],xmm8[6],xmm15[7],xmm8[7] |
| 466 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7] |
| 467 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm15[0],xmm3[1],xmm15[1],xmm3[2],xmm15[2],xmm3[3],xmm15[3],xmm3[4],xmm15[4],xmm3[5],xmm15[5],xmm3[6],xmm15[6],xmm3[7],xmm15[7] |
| 468 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm10[0],xmm0[1],xmm10[1],xmm0[2],xmm10[2],xmm0[3],xmm10[3],xmm0[4],xmm10[4],xmm0[5],xmm10[5],xmm0[6],xmm10[6],xmm0[7],xmm10[7] |
| 469 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3],xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] |
| 470 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3],xmm0[4],xmm7[4],xmm0[5],xmm7[5],xmm0[6],xmm7[6],xmm0[7],xmm7[7] |
| 471 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] |
| 472 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],xmm12[1],xmm2[2],xmm12[2],xmm2[3],xmm12[3],xmm2[4],xmm12[4],xmm2[5],xmm12[5],xmm2[6],xmm12[6],xmm2[7],xmm12[7] |
| 473 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],xmm13[1],xmm6[2],xmm13[2],xmm6[3],xmm13[3],xmm6[4],xmm13[4],xmm6[5],xmm13[5],xmm6[6],xmm13[6],xmm6[7],xmm13[7] |
| 474 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3],xmm6[4],xmm2[4],xmm6[5],xmm2[5],xmm6[6],xmm2[6],xmm6[7],xmm2[7] |
| 475 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm14[0],xmm5[1],xmm14[1],xmm5[2],xmm14[2],xmm5[3],xmm14[3],xmm5[4],xmm14[4],xmm5[5],xmm14[5],xmm5[6],xmm14[6],xmm5[7],xmm14[7] |
| 476 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] |
| 477 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm1[0],xmm5[1],xmm1[1],xmm5[2],xmm1[2],xmm5[3],xmm1[3],xmm5[4],xmm1[4],xmm5[5],xmm1[5],xmm5[6],xmm1[6],xmm5[7],xmm1[7] |
| 478 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm6[0],xmm5[1],xmm6[1],xmm5[2],xmm6[2],xmm5[3],xmm6[3],xmm5[4],xmm6[4],xmm5[5],xmm6[5],xmm5[6],xmm6[6],xmm5[7],xmm6[7] |
| 479 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm5[0],xmm0[1],xmm5[1],xmm0[2],xmm5[2],xmm0[3],xmm5[3],xmm0[4],xmm5[4],xmm0[5],xmm5[5],xmm0[6],xmm5[6],xmm0[7],xmm5[7] |
| 480 | ; SSSE3-NEXT: retq |
| 481 | ; |
| 482 | ; SSE41-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 483 | ; SSE41: # BB#0: |
| 484 | ; SSE41-NEXT: pushq %rbp |
| 485 | ; SSE41-NEXT: pushq %r15 |
| 486 | ; SSE41-NEXT: pushq %r14 |
| 487 | ; SSE41-NEXT: pushq %r13 |
| 488 | ; SSE41-NEXT: pushq %r12 |
| 489 | ; SSE41-NEXT: pushq %rbx |
| 490 | ; SSE41-NEXT: movsbq %dil, %r15 |
| 491 | ; SSE41-NEXT: movsbq %sil, %r14 |
| 492 | ; SSE41-NEXT: movsbq %dl, %r11 |
| 493 | ; SSE41-NEXT: movsbq %cl, %r10 |
| 494 | ; SSE41-NEXT: movsbq %r8b, %r8 |
| 495 | ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 496 | ; SSE41-NEXT: movsbq %r9b, %r9 |
| 497 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %r12 |
| 498 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %r13 |
| 499 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %rbp |
| 500 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %rbx |
| 501 | ; SSE41-NEXT: leaq -{{[0-9]+}}(%rsp), %rax |
| 502 | ; SSE41-NEXT: movzbl (%r15,%rax), %ecx |
| 503 | ; SSE41-NEXT: movd %ecx, %xmm0 |
| 504 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %r15 |
| 505 | ; SSE41-NEXT: pinsrb $1, (%r14,%rax), %xmm0 |
| 506 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %r14 |
| 507 | ; SSE41-NEXT: pinsrb $2, (%r11,%rax), %xmm0 |
| 508 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %r11 |
| 509 | ; SSE41-NEXT: pinsrb $3, (%r10,%rax), %xmm0 |
| 510 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %r10 |
| 511 | ; SSE41-NEXT: pinsrb $4, (%r8,%rax), %xmm0 |
| 512 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %rcx |
| 513 | ; SSE41-NEXT: pinsrb $5, (%r9,%rax), %xmm0 |
| 514 | ; SSE41-NEXT: movsbq {{[0-9]+}}(%rsp), %rdx |
| 515 | ; SSE41-NEXT: movzbl (%r12,%rax), %esi |
| 516 | ; SSE41-NEXT: movzbl (%r13,%rax), %edi |
| 517 | ; SSE41-NEXT: movzbl (%rbp,%rax), %ebp |
| 518 | ; SSE41-NEXT: movzbl (%rbx,%rax), %ebx |
| 519 | ; SSE41-NEXT: movzbl (%r15,%rax), %r8d |
| 520 | ; SSE41-NEXT: movzbl (%r14,%rax), %r9d |
| 521 | ; SSE41-NEXT: movzbl (%r11,%rax), %r11d |
| 522 | ; SSE41-NEXT: movzbl (%r10,%rax), %r10d |
| 523 | ; SSE41-NEXT: movzbl (%rcx,%rax), %ecx |
| 524 | ; SSE41-NEXT: movzbl (%rdx,%rax), %eax |
| 525 | ; SSE41-NEXT: pinsrb $6, %esi, %xmm0 |
| 526 | ; SSE41-NEXT: pinsrb $7, %edi, %xmm0 |
| 527 | ; SSE41-NEXT: pinsrb $8, %ebp, %xmm0 |
| 528 | ; SSE41-NEXT: pinsrb $9, %ebx, %xmm0 |
| 529 | ; SSE41-NEXT: pinsrb $10, %r8d, %xmm0 |
| 530 | ; SSE41-NEXT: pinsrb $11, %r9d, %xmm0 |
| 531 | ; SSE41-NEXT: pinsrb $12, %r11d, %xmm0 |
| 532 | ; SSE41-NEXT: pinsrb $13, %r10d, %xmm0 |
| 533 | ; SSE41-NEXT: pinsrb $14, %ecx, %xmm0 |
| 534 | ; SSE41-NEXT: pinsrb $15, %eax, %xmm0 |
| 535 | ; SSE41-NEXT: popq %rbx |
| 536 | ; SSE41-NEXT: popq %r12 |
| 537 | ; SSE41-NEXT: popq %r13 |
| 538 | ; SSE41-NEXT: popq %r14 |
| 539 | ; SSE41-NEXT: popq %r15 |
| 540 | ; SSE41-NEXT: popq %rbp |
| 541 | ; SSE41-NEXT: retq |
| 542 | ; |
| 543 | ; AVX-LABEL: var_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 544 | ; AVX: # BB#0: |
| 545 | ; AVX-NEXT: pushq %rbp |
| 546 | ; AVX-NEXT: pushq %r15 |
| 547 | ; AVX-NEXT: pushq %r14 |
| 548 | ; AVX-NEXT: pushq %r13 |
| 549 | ; AVX-NEXT: pushq %r12 |
| 550 | ; AVX-NEXT: pushq %rbx |
| 551 | ; AVX-NEXT: movsbq %dil, %r10 |
| 552 | ; AVX-NEXT: movsbq %sil, %r11 |
| 553 | ; AVX-NEXT: movsbq %dl, %r14 |
| 554 | ; AVX-NEXT: movsbq %cl, %r15 |
| 555 | ; AVX-NEXT: movsbq %r8b, %r8 |
| 556 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 557 | ; AVX-NEXT: movsbq %r9b, %r9 |
| 558 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %r12 |
| 559 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %r13 |
| 560 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %rbp |
| 561 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %rcx |
| 562 | ; AVX-NEXT: leaq -{{[0-9]+}}(%rsp), %rdi |
| 563 | ; AVX-NEXT: movzbl (%r10,%rdi), %eax |
| 564 | ; AVX-NEXT: vmovd %eax, %xmm0 |
| 565 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %r10 |
| 566 | ; AVX-NEXT: vpinsrb $1, (%r11,%rdi), %xmm0, %xmm0 |
| 567 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %r11 |
| 568 | ; AVX-NEXT: vpinsrb $2, (%r14,%rdi), %xmm0, %xmm0 |
| 569 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %r14 |
| 570 | ; AVX-NEXT: vpinsrb $3, (%r15,%rdi), %xmm0, %xmm0 |
| 571 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %r15 |
| 572 | ; AVX-NEXT: vpinsrb $4, (%r8,%rdi), %xmm0, %xmm0 |
| 573 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %r8 |
| 574 | ; AVX-NEXT: vpinsrb $5, (%r9,%rdi), %xmm0, %xmm0 |
| 575 | ; AVX-NEXT: movsbq {{[0-9]+}}(%rsp), %rsi |
| 576 | ; AVX-NEXT: movzbl (%r12,%rdi), %edx |
| 577 | ; AVX-NEXT: movzbl (%r13,%rdi), %ebx |
| 578 | ; AVX-NEXT: movzbl (%rbp,%rdi), %ebp |
| 579 | ; AVX-NEXT: movzbl (%rcx,%rdi), %ecx |
| 580 | ; AVX-NEXT: movzbl (%r10,%rdi), %eax |
| 581 | ; AVX-NEXT: movzbl (%r11,%rdi), %r9d |
| 582 | ; AVX-NEXT: movzbl (%r14,%rdi), %r10d |
| 583 | ; AVX-NEXT: movzbl (%r15,%rdi), %r11d |
| 584 | ; AVX-NEXT: movzbl (%r8,%rdi), %r8d |
| 585 | ; AVX-NEXT: movzbl (%rsi,%rdi), %esi |
| 586 | ; AVX-NEXT: vpinsrb $6, %edx, %xmm0, %xmm0 |
| 587 | ; AVX-NEXT: vpinsrb $7, %ebx, %xmm0, %xmm0 |
| 588 | ; AVX-NEXT: vpinsrb $8, %ebp, %xmm0, %xmm0 |
| 589 | ; AVX-NEXT: vpinsrb $9, %ecx, %xmm0, %xmm0 |
| 590 | ; AVX-NEXT: vpinsrb $10, %eax, %xmm0, %xmm0 |
| 591 | ; AVX-NEXT: vpinsrb $11, %r9d, %xmm0, %xmm0 |
| 592 | ; AVX-NEXT: vpinsrb $12, %r10d, %xmm0, %xmm0 |
| 593 | ; AVX-NEXT: vpinsrb $13, %r11d, %xmm0, %xmm0 |
| 594 | ; AVX-NEXT: vpinsrb $14, %r8d, %xmm0, %xmm0 |
| 595 | ; AVX-NEXT: vpinsrb $15, %esi, %xmm0, %xmm0 |
| 596 | ; AVX-NEXT: popq %rbx |
| 597 | ; AVX-NEXT: popq %r12 |
| 598 | ; AVX-NEXT: popq %r13 |
| 599 | ; AVX-NEXT: popq %r14 |
| 600 | ; AVX-NEXT: popq %r15 |
| 601 | ; AVX-NEXT: popq %rbp |
| 602 | ; AVX-NEXT: retq |
| 603 | %x0 = extractelement <16 x i8> %x, i8 %i0 |
| 604 | %x1 = extractelement <16 x i8> %x, i8 %i1 |
| 605 | %x2 = extractelement <16 x i8> %x, i8 %i2 |
| 606 | %x3 = extractelement <16 x i8> %x, i8 %i3 |
| 607 | %x4 = extractelement <16 x i8> %x, i8 %i4 |
| 608 | %x5 = extractelement <16 x i8> %x, i8 %i5 |
| 609 | %x6 = extractelement <16 x i8> %x, i8 %i6 |
| 610 | %x7 = extractelement <16 x i8> %x, i8 %i7 |
| 611 | %x8 = extractelement <16 x i8> %x, i8 %i8 |
| 612 | %x9 = extractelement <16 x i8> %x, i8 %i9 |
| 613 | %x10 = extractelement <16 x i8> %x, i8 %i10 |
| 614 | %x11 = extractelement <16 x i8> %x, i8 %i11 |
| 615 | %x12 = extractelement <16 x i8> %x, i8 %i12 |
| 616 | %x13 = extractelement <16 x i8> %x, i8 %i13 |
| 617 | %x14 = extractelement <16 x i8> %x, i8 %i14 |
| 618 | %x15 = extractelement <16 x i8> %x, i8 %i15 |
| 619 | %r0 = insertelement <16 x i8> undef, i8 %x0 , i32 0 |
| 620 | %r1 = insertelement <16 x i8> %r0 , i8 %x1 , i32 1 |
| 621 | %r2 = insertelement <16 x i8> %r1 , i8 %x2 , i32 2 |
| 622 | %r3 = insertelement <16 x i8> %r2 , i8 %x3 , i32 3 |
| 623 | %r4 = insertelement <16 x i8> %r3 , i8 %x4 , i32 4 |
| 624 | %r5 = insertelement <16 x i8> %r4 , i8 %x5 , i32 5 |
| 625 | %r6 = insertelement <16 x i8> %r5 , i8 %x6 , i32 6 |
| 626 | %r7 = insertelement <16 x i8> %r6 , i8 %x7 , i32 7 |
| 627 | %r8 = insertelement <16 x i8> %r7 , i8 %x8 , i32 8 |
| 628 | %r9 = insertelement <16 x i8> %r8 , i8 %x9 , i32 9 |
| 629 | %r10 = insertelement <16 x i8> %r9 , i8 %x10, i32 10 |
| 630 | %r11 = insertelement <16 x i8> %r10, i8 %x11, i32 11 |
| 631 | %r12 = insertelement <16 x i8> %r11, i8 %x12, i32 12 |
| 632 | %r13 = insertelement <16 x i8> %r12, i8 %x13, i32 13 |
| 633 | %r14 = insertelement <16 x i8> %r13, i8 %x14, i32 14 |
| 634 | %r15 = insertelement <16 x i8> %r14, i8 %x15, i32 15 |
| 635 | ret <16 x i8> %r15 |
| 636 | } |
| 637 | |
| 638 | ; |
| 639 | ; Unary shuffle indices from memory |
| 640 | ; |
| 641 | |
| 642 | define <4 x i32> @mem_shuffle_v4i32_v4i32_xxxx_i32(<4 x i32> %x, i32* %i) nounwind { |
| 643 | ; SSE2-LABEL: mem_shuffle_v4i32_v4i32_xxxx_i32: |
| 644 | ; SSE2: # BB#0: |
| 645 | ; SSE2-NEXT: movslq (%rdi), %rax |
| 646 | ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 647 | ; SSE2-NEXT: movslq 4(%rdi), %rcx |
| 648 | ; SSE2-NEXT: movslq 8(%rdi), %rdx |
| 649 | ; SSE2-NEXT: movslq 12(%rdi), %rsi |
| 650 | ; SSE2-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 651 | ; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 652 | ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 653 | ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 654 | ; SSE2-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 655 | ; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] |
| 656 | ; SSE2-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 657 | ; SSE2-NEXT: retq |
| 658 | ; |
| 659 | ; SSSE3-LABEL: mem_shuffle_v4i32_v4i32_xxxx_i32: |
| 660 | ; SSSE3: # BB#0: |
| 661 | ; SSSE3-NEXT: movslq (%rdi), %rax |
| 662 | ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 663 | ; SSSE3-NEXT: movslq 4(%rdi), %rcx |
| 664 | ; SSSE3-NEXT: movslq 8(%rdi), %rdx |
| 665 | ; SSSE3-NEXT: movslq 12(%rdi), %rsi |
| 666 | ; SSSE3-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 667 | ; SSSE3-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 668 | ; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 669 | ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 670 | ; SSSE3-NEXT: movd {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 671 | ; SSSE3-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1] |
| 672 | ; SSSE3-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] |
| 673 | ; SSSE3-NEXT: retq |
| 674 | ; |
| 675 | ; SSE41-LABEL: mem_shuffle_v4i32_v4i32_xxxx_i32: |
| 676 | ; SSE41: # BB#0: |
| 677 | ; SSE41-NEXT: movslq (%rdi), %rax |
| 678 | ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 679 | ; SSE41-NEXT: movslq 4(%rdi), %rcx |
| 680 | ; SSE41-NEXT: movslq 8(%rdi), %rdx |
| 681 | ; SSE41-NEXT: movslq 12(%rdi), %rsi |
| 682 | ; SSE41-NEXT: movd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 683 | ; SSE41-NEXT: pinsrd $1, -24(%rsp,%rcx,4), %xmm0 |
| 684 | ; SSE41-NEXT: pinsrd $2, -24(%rsp,%rdx,4), %xmm0 |
| 685 | ; SSE41-NEXT: pinsrd $3, -24(%rsp,%rsi,4), %xmm0 |
| 686 | ; SSE41-NEXT: retq |
| 687 | ; |
| 688 | ; AVX-LABEL: mem_shuffle_v4i32_v4i32_xxxx_i32: |
| 689 | ; AVX: # BB#0: |
| 690 | ; AVX-NEXT: movslq (%rdi), %rax |
| 691 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 692 | ; AVX-NEXT: movslq 4(%rdi), %rcx |
| 693 | ; AVX-NEXT: movslq 8(%rdi), %rdx |
| 694 | ; AVX-NEXT: movslq 12(%rdi), %rsi |
| 695 | ; AVX-NEXT: vmovd {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 696 | ; AVX-NEXT: vpinsrd $1, -24(%rsp,%rcx,4), %xmm0, %xmm0 |
| 697 | ; AVX-NEXT: vpinsrd $2, -24(%rsp,%rdx,4), %xmm0, %xmm0 |
| 698 | ; AVX-NEXT: vpinsrd $3, -24(%rsp,%rsi,4), %xmm0, %xmm0 |
| 699 | ; AVX-NEXT: retq |
| 700 | %p0 = getelementptr inbounds i32, i32* %i, i64 0 |
| 701 | %p1 = getelementptr inbounds i32, i32* %i, i64 1 |
| 702 | %p2 = getelementptr inbounds i32, i32* %i, i64 2 |
| 703 | %p3 = getelementptr inbounds i32, i32* %i, i64 3 |
| 704 | %i0 = load i32, i32* %p0, align 4 |
| 705 | %i1 = load i32, i32* %p1, align 4 |
| 706 | %i2 = load i32, i32* %p2, align 4 |
| 707 | %i3 = load i32, i32* %p3, align 4 |
| 708 | %x0 = extractelement <4 x i32> %x, i32 %i0 |
| 709 | %x1 = extractelement <4 x i32> %x, i32 %i1 |
| 710 | %x2 = extractelement <4 x i32> %x, i32 %i2 |
| 711 | %x3 = extractelement <4 x i32> %x, i32 %i3 |
| 712 | %r0 = insertelement <4 x i32> undef, i32 %x0, i32 0 |
| 713 | %r1 = insertelement <4 x i32> %r0, i32 %x1, i32 1 |
| 714 | %r2 = insertelement <4 x i32> %r1, i32 %x2, i32 2 |
| 715 | %r3 = insertelement <4 x i32> %r2, i32 %x3, i32 3 |
| 716 | ret <4 x i32> %r3 |
| 717 | } |
| 718 | |
| 719 | define <16 x i8> @mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8(<16 x i8> %x, i8* %i) nounwind { |
| 720 | ; SSE2-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 721 | ; SSE2: # BB#0: |
| 722 | ; SSE2-NEXT: movsbq (%rdi), %rcx |
| 723 | ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 724 | ; SSE2-NEXT: leaq -{{[0-9]+}}(%rsp), %rax |
| 725 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 726 | ; SSE2-NEXT: movd %ecx, %xmm0 |
| 727 | ; SSE2-NEXT: movsbq 8(%rdi), %rcx |
| 728 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 729 | ; SSE2-NEXT: movd %ecx, %xmm8 |
| 730 | ; SSE2-NEXT: movsbq 12(%rdi), %rcx |
| 731 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 732 | ; SSE2-NEXT: movd %ecx, %xmm9 |
| 733 | ; SSE2-NEXT: movsbq 4(%rdi), %rcx |
| 734 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 735 | ; SSE2-NEXT: movd %ecx, %xmm3 |
| 736 | ; SSE2-NEXT: movsbq 14(%rdi), %rcx |
| 737 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 738 | ; SSE2-NEXT: movd %ecx, %xmm10 |
| 739 | ; SSE2-NEXT: movsbq 6(%rdi), %rcx |
| 740 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 741 | ; SSE2-NEXT: movd %ecx, %xmm5 |
| 742 | ; SSE2-NEXT: movsbq 10(%rdi), %rcx |
| 743 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 744 | ; SSE2-NEXT: movd %ecx, %xmm11 |
| 745 | ; SSE2-NEXT: movsbq 2(%rdi), %rcx |
| 746 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 747 | ; SSE2-NEXT: movd %ecx, %xmm7 |
| 748 | ; SSE2-NEXT: movsbq 15(%rdi), %rcx |
| 749 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 750 | ; SSE2-NEXT: movd %ecx, %xmm12 |
| 751 | ; SSE2-NEXT: movsbq 7(%rdi), %rcx |
| 752 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 753 | ; SSE2-NEXT: movd %ecx, %xmm2 |
| 754 | ; SSE2-NEXT: movsbq 11(%rdi), %rcx |
| 755 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 756 | ; SSE2-NEXT: movd %ecx, %xmm13 |
| 757 | ; SSE2-NEXT: movsbq 3(%rdi), %rcx |
| 758 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 759 | ; SSE2-NEXT: movd %ecx, %xmm6 |
| 760 | ; SSE2-NEXT: movsbq 13(%rdi), %rcx |
| 761 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 762 | ; SSE2-NEXT: movd %ecx, %xmm14 |
| 763 | ; SSE2-NEXT: movsbq 5(%rdi), %rcx |
| 764 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 765 | ; SSE2-NEXT: movd %ecx, %xmm4 |
| 766 | ; SSE2-NEXT: movsbq 9(%rdi), %rcx |
| 767 | ; SSE2-NEXT: movzbl (%rcx,%rax), %ecx |
| 768 | ; SSE2-NEXT: movd %ecx, %xmm15 |
| 769 | ; SSE2-NEXT: movsbq 1(%rdi), %rcx |
| 770 | ; SSE2-NEXT: movzbl (%rcx,%rax), %eax |
| 771 | ; SSE2-NEXT: movd %eax, %xmm1 |
| 772 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm8[0],xmm0[1],xmm8[1],xmm0[2],xmm8[2],xmm0[3],xmm8[3],xmm0[4],xmm8[4],xmm0[5],xmm8[5],xmm0[6],xmm8[6],xmm0[7],xmm8[7] |
| 773 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7] |
| 774 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] |
| 775 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm10[0],xmm5[1],xmm10[1],xmm5[2],xmm10[2],xmm5[3],xmm10[3],xmm5[4],xmm10[4],xmm5[5],xmm10[5],xmm5[6],xmm10[6],xmm5[7],xmm10[7] |
| 776 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3],xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] |
| 777 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3],xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7] |
| 778 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3],xmm0[4],xmm7[4],xmm0[5],xmm7[5],xmm0[6],xmm7[6],xmm0[7],xmm7[7] |
| 779 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],xmm12[1],xmm2[2],xmm12[2],xmm2[3],xmm12[3],xmm2[4],xmm12[4],xmm2[5],xmm12[5],xmm2[6],xmm12[6],xmm2[7],xmm12[7] |
| 780 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],xmm13[1],xmm6[2],xmm13[2],xmm6[3],xmm13[3],xmm6[4],xmm13[4],xmm6[5],xmm13[5],xmm6[6],xmm13[6],xmm6[7],xmm13[7] |
| 781 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3],xmm6[4],xmm2[4],xmm6[5],xmm2[5],xmm6[6],xmm2[6],xmm6[7],xmm2[7] |
| 782 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm14[0],xmm4[1],xmm14[1],xmm4[2],xmm14[2],xmm4[3],xmm14[3],xmm4[4],xmm14[4],xmm4[5],xmm14[5],xmm4[6],xmm14[6],xmm4[7],xmm14[7] |
| 783 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm15[0],xmm1[1],xmm15[1],xmm1[2],xmm15[2],xmm1[3],xmm15[3],xmm1[4],xmm15[4],xmm1[5],xmm15[5],xmm1[6],xmm15[6],xmm1[7],xmm15[7] |
| 784 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] |
| 785 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1],xmm1[2],xmm6[2],xmm1[3],xmm6[3],xmm1[4],xmm6[4],xmm1[5],xmm6[5],xmm1[6],xmm6[6],xmm1[7],xmm6[7] |
| 786 | ; SSE2-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] |
| 787 | ; SSE2-NEXT: retq |
| 788 | ; |
| 789 | ; SSSE3-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 790 | ; SSSE3: # BB#0: |
| 791 | ; SSSE3-NEXT: movsbq (%rdi), %rcx |
| 792 | ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 793 | ; SSSE3-NEXT: leaq -{{[0-9]+}}(%rsp), %rax |
| 794 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 795 | ; SSSE3-NEXT: movd %ecx, %xmm0 |
| 796 | ; SSSE3-NEXT: movsbq 8(%rdi), %rcx |
| 797 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 798 | ; SSSE3-NEXT: movd %ecx, %xmm8 |
| 799 | ; SSSE3-NEXT: movsbq 12(%rdi), %rcx |
| 800 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 801 | ; SSSE3-NEXT: movd %ecx, %xmm9 |
| 802 | ; SSSE3-NEXT: movsbq 4(%rdi), %rcx |
| 803 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 804 | ; SSSE3-NEXT: movd %ecx, %xmm3 |
| 805 | ; SSSE3-NEXT: movsbq 14(%rdi), %rcx |
| 806 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 807 | ; SSSE3-NEXT: movd %ecx, %xmm10 |
| 808 | ; SSSE3-NEXT: movsbq 6(%rdi), %rcx |
| 809 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 810 | ; SSSE3-NEXT: movd %ecx, %xmm5 |
| 811 | ; SSSE3-NEXT: movsbq 10(%rdi), %rcx |
| 812 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 813 | ; SSSE3-NEXT: movd %ecx, %xmm11 |
| 814 | ; SSSE3-NEXT: movsbq 2(%rdi), %rcx |
| 815 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 816 | ; SSSE3-NEXT: movd %ecx, %xmm7 |
| 817 | ; SSSE3-NEXT: movsbq 15(%rdi), %rcx |
| 818 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 819 | ; SSSE3-NEXT: movd %ecx, %xmm12 |
| 820 | ; SSSE3-NEXT: movsbq 7(%rdi), %rcx |
| 821 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 822 | ; SSSE3-NEXT: movd %ecx, %xmm2 |
| 823 | ; SSSE3-NEXT: movsbq 11(%rdi), %rcx |
| 824 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 825 | ; SSSE3-NEXT: movd %ecx, %xmm13 |
| 826 | ; SSSE3-NEXT: movsbq 3(%rdi), %rcx |
| 827 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 828 | ; SSSE3-NEXT: movd %ecx, %xmm6 |
| 829 | ; SSSE3-NEXT: movsbq 13(%rdi), %rcx |
| 830 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 831 | ; SSSE3-NEXT: movd %ecx, %xmm14 |
| 832 | ; SSSE3-NEXT: movsbq 5(%rdi), %rcx |
| 833 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 834 | ; SSSE3-NEXT: movd %ecx, %xmm4 |
| 835 | ; SSSE3-NEXT: movsbq 9(%rdi), %rcx |
| 836 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %ecx |
| 837 | ; SSSE3-NEXT: movd %ecx, %xmm15 |
| 838 | ; SSSE3-NEXT: movsbq 1(%rdi), %rcx |
| 839 | ; SSSE3-NEXT: movzbl (%rcx,%rax), %eax |
| 840 | ; SSSE3-NEXT: movd %eax, %xmm1 |
| 841 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm8[0],xmm0[1],xmm8[1],xmm0[2],xmm8[2],xmm0[3],xmm8[3],xmm0[4],xmm8[4],xmm0[5],xmm8[5],xmm0[6],xmm8[6],xmm0[7],xmm8[7] |
| 842 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm3 = xmm3[0],xmm9[0],xmm3[1],xmm9[1],xmm3[2],xmm9[2],xmm3[3],xmm9[3],xmm3[4],xmm9[4],xmm3[5],xmm9[5],xmm3[6],xmm9[6],xmm3[7],xmm9[7] |
| 843 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3],xmm0[4],xmm3[4],xmm0[5],xmm3[5],xmm0[6],xmm3[6],xmm0[7],xmm3[7] |
| 844 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm5 = xmm5[0],xmm10[0],xmm5[1],xmm10[1],xmm5[2],xmm10[2],xmm5[3],xmm10[3],xmm5[4],xmm10[4],xmm5[5],xmm10[5],xmm5[6],xmm10[6],xmm5[7],xmm10[7] |
| 845 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm11[0],xmm7[1],xmm11[1],xmm7[2],xmm11[2],xmm7[3],xmm11[3],xmm7[4],xmm11[4],xmm7[5],xmm11[5],xmm7[6],xmm11[6],xmm7[7],xmm11[7] |
| 846 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm7 = xmm7[0],xmm5[0],xmm7[1],xmm5[1],xmm7[2],xmm5[2],xmm7[3],xmm5[3],xmm7[4],xmm5[4],xmm7[5],xmm5[5],xmm7[6],xmm5[6],xmm7[7],xmm5[7] |
| 847 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm7[0],xmm0[1],xmm7[1],xmm0[2],xmm7[2],xmm0[3],xmm7[3],xmm0[4],xmm7[4],xmm0[5],xmm7[5],xmm0[6],xmm7[6],xmm0[7],xmm7[7] |
| 848 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm12[0],xmm2[1],xmm12[1],xmm2[2],xmm12[2],xmm2[3],xmm12[3],xmm2[4],xmm12[4],xmm2[5],xmm12[5],xmm2[6],xmm12[6],xmm2[7],xmm12[7] |
| 849 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm13[0],xmm6[1],xmm13[1],xmm6[2],xmm13[2],xmm6[3],xmm13[3],xmm6[4],xmm13[4],xmm6[5],xmm13[5],xmm6[6],xmm13[6],xmm6[7],xmm13[7] |
| 850 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm6 = xmm6[0],xmm2[0],xmm6[1],xmm2[1],xmm6[2],xmm2[2],xmm6[3],xmm2[3],xmm6[4],xmm2[4],xmm6[5],xmm2[5],xmm6[6],xmm2[6],xmm6[7],xmm2[7] |
| 851 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm14[0],xmm4[1],xmm14[1],xmm4[2],xmm14[2],xmm4[3],xmm14[3],xmm4[4],xmm14[4],xmm4[5],xmm14[5],xmm4[6],xmm14[6],xmm4[7],xmm14[7] |
| 852 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm15[0],xmm1[1],xmm15[1],xmm1[2],xmm15[2],xmm1[3],xmm15[3],xmm1[4],xmm15[4],xmm1[5],xmm15[5],xmm1[6],xmm15[6],xmm1[7],xmm15[7] |
| 853 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm4[0],xmm1[1],xmm4[1],xmm1[2],xmm4[2],xmm1[3],xmm4[3],xmm1[4],xmm4[4],xmm1[5],xmm4[5],xmm1[6],xmm4[6],xmm1[7],xmm4[7] |
| 854 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm6[0],xmm1[1],xmm6[1],xmm1[2],xmm6[2],xmm1[3],xmm6[3],xmm1[4],xmm6[4],xmm1[5],xmm6[5],xmm1[6],xmm6[6],xmm1[7],xmm6[7] |
| 855 | ; SSSE3-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3],xmm0[4],xmm1[4],xmm0[5],xmm1[5],xmm0[6],xmm1[6],xmm0[7],xmm1[7] |
| 856 | ; SSSE3-NEXT: retq |
| 857 | ; |
| 858 | ; SSE41-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 859 | ; SSE41: # BB#0: |
| 860 | ; SSE41-NEXT: pushq %rbp |
| 861 | ; SSE41-NEXT: pushq %r15 |
| 862 | ; SSE41-NEXT: pushq %r14 |
| 863 | ; SSE41-NEXT: pushq %r13 |
| 864 | ; SSE41-NEXT: pushq %r12 |
| 865 | ; SSE41-NEXT: pushq %rbx |
| 866 | ; SSE41-NEXT: movsbq (%rdi), %rax |
| 867 | ; SSE41-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 868 | ; SSE41-NEXT: movsbq 1(%rdi), %r15 |
| 869 | ; SSE41-NEXT: movsbq 2(%rdi), %r8 |
| 870 | ; SSE41-NEXT: movsbq 3(%rdi), %r9 |
| 871 | ; SSE41-NEXT: movsbq 4(%rdi), %r10 |
| 872 | ; SSE41-NEXT: movsbq 5(%rdi), %r11 |
| 873 | ; SSE41-NEXT: movsbq 6(%rdi), %r14 |
| 874 | ; SSE41-NEXT: movsbq 7(%rdi), %r12 |
| 875 | ; SSE41-NEXT: movsbq 8(%rdi), %r13 |
| 876 | ; SSE41-NEXT: movsbq 9(%rdi), %rdx |
| 877 | ; SSE41-NEXT: movsbq 10(%rdi), %rcx |
| 878 | ; SSE41-NEXT: movsbq 11(%rdi), %rsi |
| 879 | ; SSE41-NEXT: movsbq 12(%rdi), %rbx |
| 880 | ; SSE41-NEXT: leaq -{{[0-9]+}}(%rsp), %rbp |
| 881 | ; SSE41-NEXT: movzbl (%rax,%rbp), %eax |
| 882 | ; SSE41-NEXT: movd %eax, %xmm0 |
| 883 | ; SSE41-NEXT: movsbq 13(%rdi), %rax |
| 884 | ; SSE41-NEXT: pinsrb $1, (%r15,%rbp), %xmm0 |
| 885 | ; SSE41-NEXT: movsbq 14(%rdi), %r15 |
| 886 | ; SSE41-NEXT: movsbq 15(%rdi), %rdi |
| 887 | ; SSE41-NEXT: movzbl (%rdi,%rbp), %edi |
| 888 | ; SSE41-NEXT: movzbl (%r15,%rbp), %r15d |
| 889 | ; SSE41-NEXT: movzbl (%rax,%rbp), %eax |
| 890 | ; SSE41-NEXT: movzbl (%rbx,%rbp), %ebx |
| 891 | ; SSE41-NEXT: movzbl (%rsi,%rbp), %esi |
| 892 | ; SSE41-NEXT: movzbl (%rcx,%rbp), %ecx |
| 893 | ; SSE41-NEXT: movzbl (%rdx,%rbp), %edx |
| 894 | ; SSE41-NEXT: movzbl (%r13,%rbp), %r13d |
| 895 | ; SSE41-NEXT: movzbl (%r12,%rbp), %r12d |
| 896 | ; SSE41-NEXT: movzbl (%r14,%rbp), %r14d |
| 897 | ; SSE41-NEXT: movzbl (%r11,%rbp), %r11d |
| 898 | ; SSE41-NEXT: movzbl (%r10,%rbp), %r10d |
| 899 | ; SSE41-NEXT: movzbl (%r9,%rbp), %r9d |
| 900 | ; SSE41-NEXT: movzbl (%r8,%rbp), %ebp |
| 901 | ; SSE41-NEXT: pinsrb $2, %ebp, %xmm0 |
| 902 | ; SSE41-NEXT: pinsrb $3, %r9d, %xmm0 |
| 903 | ; SSE41-NEXT: pinsrb $4, %r10d, %xmm0 |
| 904 | ; SSE41-NEXT: pinsrb $5, %r11d, %xmm0 |
| 905 | ; SSE41-NEXT: pinsrb $6, %r14d, %xmm0 |
| 906 | ; SSE41-NEXT: pinsrb $7, %r12d, %xmm0 |
| 907 | ; SSE41-NEXT: pinsrb $8, %r13d, %xmm0 |
| 908 | ; SSE41-NEXT: pinsrb $9, %edx, %xmm0 |
| 909 | ; SSE41-NEXT: pinsrb $10, %ecx, %xmm0 |
| 910 | ; SSE41-NEXT: pinsrb $11, %esi, %xmm0 |
| 911 | ; SSE41-NEXT: pinsrb $12, %ebx, %xmm0 |
| 912 | ; SSE41-NEXT: pinsrb $13, %eax, %xmm0 |
| 913 | ; SSE41-NEXT: pinsrb $14, %r15d, %xmm0 |
| 914 | ; SSE41-NEXT: pinsrb $15, %edi, %xmm0 |
| 915 | ; SSE41-NEXT: popq %rbx |
| 916 | ; SSE41-NEXT: popq %r12 |
| 917 | ; SSE41-NEXT: popq %r13 |
| 918 | ; SSE41-NEXT: popq %r14 |
| 919 | ; SSE41-NEXT: popq %r15 |
| 920 | ; SSE41-NEXT: popq %rbp |
| 921 | ; SSE41-NEXT: retq |
| 922 | ; |
| 923 | ; AVX-LABEL: mem_shuffle_v16i8_v16i8_xxxxxxxxxxxxxxxx_i8: |
| 924 | ; AVX: # BB#0: |
| 925 | ; AVX-NEXT: pushq %rbp |
| 926 | ; AVX-NEXT: pushq %r15 |
| 927 | ; AVX-NEXT: pushq %r14 |
| 928 | ; AVX-NEXT: pushq %r13 |
| 929 | ; AVX-NEXT: pushq %r12 |
| 930 | ; AVX-NEXT: pushq %rbx |
| 931 | ; AVX-NEXT: movsbq (%rdi), %rsi |
| 932 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 933 | ; AVX-NEXT: movsbq 1(%rdi), %r15 |
| 934 | ; AVX-NEXT: movsbq 2(%rdi), %r8 |
| 935 | ; AVX-NEXT: movsbq 3(%rdi), %r9 |
| 936 | ; AVX-NEXT: movsbq 4(%rdi), %r10 |
| 937 | ; AVX-NEXT: movsbq 5(%rdi), %r11 |
| 938 | ; AVX-NEXT: movsbq 6(%rdi), %r14 |
| 939 | ; AVX-NEXT: movsbq 7(%rdi), %r12 |
| 940 | ; AVX-NEXT: movsbq 8(%rdi), %r13 |
| 941 | ; AVX-NEXT: movsbq 9(%rdi), %rdx |
| 942 | ; AVX-NEXT: movsbq 10(%rdi), %rax |
| 943 | ; AVX-NEXT: movsbq 11(%rdi), %rcx |
| 944 | ; AVX-NEXT: movsbq 12(%rdi), %rbx |
| 945 | ; AVX-NEXT: leaq -{{[0-9]+}}(%rsp), %rbp |
| 946 | ; AVX-NEXT: movzbl (%rsi,%rbp), %esi |
| 947 | ; AVX-NEXT: vmovd %esi, %xmm0 |
| 948 | ; AVX-NEXT: movsbq 13(%rdi), %rsi |
| 949 | ; AVX-NEXT: vpinsrb $1, (%r15,%rbp), %xmm0, %xmm0 |
| 950 | ; AVX-NEXT: movsbq 14(%rdi), %r15 |
| 951 | ; AVX-NEXT: movsbq 15(%rdi), %rdi |
| 952 | ; AVX-NEXT: movzbl (%rdi,%rbp), %edi |
| 953 | ; AVX-NEXT: movzbl (%r15,%rbp), %r15d |
| 954 | ; AVX-NEXT: movzbl (%rsi,%rbp), %esi |
| 955 | ; AVX-NEXT: movzbl (%rbx,%rbp), %ebx |
| 956 | ; AVX-NEXT: movzbl (%rcx,%rbp), %ecx |
| 957 | ; AVX-NEXT: movzbl (%rax,%rbp), %eax |
| 958 | ; AVX-NEXT: movzbl (%rdx,%rbp), %edx |
| 959 | ; AVX-NEXT: movzbl (%r13,%rbp), %r13d |
| 960 | ; AVX-NEXT: movzbl (%r12,%rbp), %r12d |
| 961 | ; AVX-NEXT: movzbl (%r14,%rbp), %r14d |
| 962 | ; AVX-NEXT: movzbl (%r11,%rbp), %r11d |
| 963 | ; AVX-NEXT: movzbl (%r10,%rbp), %r10d |
| 964 | ; AVX-NEXT: movzbl (%r9,%rbp), %r9d |
| 965 | ; AVX-NEXT: movzbl (%r8,%rbp), %ebp |
| 966 | ; AVX-NEXT: vpinsrb $2, %ebp, %xmm0, %xmm0 |
| 967 | ; AVX-NEXT: vpinsrb $3, %r9d, %xmm0, %xmm0 |
| 968 | ; AVX-NEXT: vpinsrb $4, %r10d, %xmm0, %xmm0 |
| 969 | ; AVX-NEXT: vpinsrb $5, %r11d, %xmm0, %xmm0 |
| 970 | ; AVX-NEXT: vpinsrb $6, %r14d, %xmm0, %xmm0 |
| 971 | ; AVX-NEXT: vpinsrb $7, %r12d, %xmm0, %xmm0 |
| 972 | ; AVX-NEXT: vpinsrb $8, %r13d, %xmm0, %xmm0 |
| 973 | ; AVX-NEXT: vpinsrb $9, %edx, %xmm0, %xmm0 |
| 974 | ; AVX-NEXT: vpinsrb $10, %eax, %xmm0, %xmm0 |
| 975 | ; AVX-NEXT: vpinsrb $11, %ecx, %xmm0, %xmm0 |
| 976 | ; AVX-NEXT: vpinsrb $12, %ebx, %xmm0, %xmm0 |
| 977 | ; AVX-NEXT: vpinsrb $13, %esi, %xmm0, %xmm0 |
| 978 | ; AVX-NEXT: vpinsrb $14, %r15d, %xmm0, %xmm0 |
| 979 | ; AVX-NEXT: vpinsrb $15, %edi, %xmm0, %xmm0 |
| 980 | ; AVX-NEXT: popq %rbx |
| 981 | ; AVX-NEXT: popq %r12 |
| 982 | ; AVX-NEXT: popq %r13 |
| 983 | ; AVX-NEXT: popq %r14 |
| 984 | ; AVX-NEXT: popq %r15 |
| 985 | ; AVX-NEXT: popq %rbp |
| 986 | ; AVX-NEXT: retq |
| 987 | %p0 = getelementptr inbounds i8, i8* %i, i64 0 |
| 988 | %p1 = getelementptr inbounds i8, i8* %i, i64 1 |
| 989 | %p2 = getelementptr inbounds i8, i8* %i, i64 2 |
| 990 | %p3 = getelementptr inbounds i8, i8* %i, i64 3 |
| 991 | %p4 = getelementptr inbounds i8, i8* %i, i64 4 |
| 992 | %p5 = getelementptr inbounds i8, i8* %i, i64 5 |
| 993 | %p6 = getelementptr inbounds i8, i8* %i, i64 6 |
| 994 | %p7 = getelementptr inbounds i8, i8* %i, i64 7 |
| 995 | %p8 = getelementptr inbounds i8, i8* %i, i64 8 |
| 996 | %p9 = getelementptr inbounds i8, i8* %i, i64 9 |
| 997 | %p10 = getelementptr inbounds i8, i8* %i, i64 10 |
| 998 | %p11 = getelementptr inbounds i8, i8* %i, i64 11 |
| 999 | %p12 = getelementptr inbounds i8, i8* %i, i64 12 |
| 1000 | %p13 = getelementptr inbounds i8, i8* %i, i64 13 |
| 1001 | %p14 = getelementptr inbounds i8, i8* %i, i64 14 |
| 1002 | %p15 = getelementptr inbounds i8, i8* %i, i64 15 |
| 1003 | %i0 = load i8, i8* %p0 , align 4 |
| 1004 | %i1 = load i8, i8* %p1 , align 4 |
| 1005 | %i2 = load i8, i8* %p2 , align 4 |
| 1006 | %i3 = load i8, i8* %p3 , align 4 |
| 1007 | %i4 = load i8, i8* %p4 , align 4 |
| 1008 | %i5 = load i8, i8* %p5 , align 4 |
| 1009 | %i6 = load i8, i8* %p6 , align 4 |
| 1010 | %i7 = load i8, i8* %p7 , align 4 |
| 1011 | %i8 = load i8, i8* %p8 , align 4 |
| 1012 | %i9 = load i8, i8* %p9 , align 4 |
| 1013 | %i10 = load i8, i8* %p10, align 4 |
| 1014 | %i11 = load i8, i8* %p11, align 4 |
| 1015 | %i12 = load i8, i8* %p12, align 4 |
| 1016 | %i13 = load i8, i8* %p13, align 4 |
| 1017 | %i14 = load i8, i8* %p14, align 4 |
| 1018 | %i15 = load i8, i8* %p15, align 4 |
| 1019 | %x0 = extractelement <16 x i8> %x, i8 %i0 |
| 1020 | %x1 = extractelement <16 x i8> %x, i8 %i1 |
| 1021 | %x2 = extractelement <16 x i8> %x, i8 %i2 |
| 1022 | %x3 = extractelement <16 x i8> %x, i8 %i3 |
| 1023 | %x4 = extractelement <16 x i8> %x, i8 %i4 |
| 1024 | %x5 = extractelement <16 x i8> %x, i8 %i5 |
| 1025 | %x6 = extractelement <16 x i8> %x, i8 %i6 |
| 1026 | %x7 = extractelement <16 x i8> %x, i8 %i7 |
| 1027 | %x8 = extractelement <16 x i8> %x, i8 %i8 |
| 1028 | %x9 = extractelement <16 x i8> %x, i8 %i9 |
| 1029 | %x10 = extractelement <16 x i8> %x, i8 %i10 |
| 1030 | %x11 = extractelement <16 x i8> %x, i8 %i11 |
| 1031 | %x12 = extractelement <16 x i8> %x, i8 %i12 |
| 1032 | %x13 = extractelement <16 x i8> %x, i8 %i13 |
| 1033 | %x14 = extractelement <16 x i8> %x, i8 %i14 |
| 1034 | %x15 = extractelement <16 x i8> %x, i8 %i15 |
| 1035 | %r0 = insertelement <16 x i8> undef, i8 %x0 , i32 0 |
| 1036 | %r1 = insertelement <16 x i8> %r0 , i8 %x1 , i32 1 |
| 1037 | %r2 = insertelement <16 x i8> %r1 , i8 %x2 , i32 2 |
| 1038 | %r3 = insertelement <16 x i8> %r2 , i8 %x3 , i32 3 |
| 1039 | %r4 = insertelement <16 x i8> %r3 , i8 %x4 , i32 4 |
| 1040 | %r5 = insertelement <16 x i8> %r4 , i8 %x5 , i32 5 |
| 1041 | %r6 = insertelement <16 x i8> %r5 , i8 %x6 , i32 6 |
| 1042 | %r7 = insertelement <16 x i8> %r6 , i8 %x7 , i32 7 |
| 1043 | %r8 = insertelement <16 x i8> %r7 , i8 %x8 , i32 8 |
| 1044 | %r9 = insertelement <16 x i8> %r8 , i8 %x9 , i32 9 |
| 1045 | %r10 = insertelement <16 x i8> %r9 , i8 %x10, i32 10 |
| 1046 | %r11 = insertelement <16 x i8> %r10, i8 %x11, i32 11 |
| 1047 | %r12 = insertelement <16 x i8> %r11, i8 %x12, i32 12 |
| 1048 | %r13 = insertelement <16 x i8> %r12, i8 %x13, i32 13 |
| 1049 | %r14 = insertelement <16 x i8> %r13, i8 %x14, i32 14 |
| 1050 | %r15 = insertelement <16 x i8> %r14, i8 %x15, i32 15 |
| 1051 | ret <16 x i8> %r15 |
| 1052 | } |
| 1053 | |
| 1054 | ; |
| 1055 | ; Binary shuffle indices from registers |
| 1056 | ; |
| 1057 | |
| 1058 | define <4 x float> @var_shuffle_v4f32_v4f32_x0yx_i32(<4 x float> %x, <4 x float> %y, i32 %i0, i32 %i1, i32 %i2, i32 %i3) nounwind { |
| 1059 | ; SSE-LABEL: var_shuffle_v4f32_v4f32_x0yx_i32: |
| 1060 | ; SSE: # BB#0: |
| 1061 | ; SSE-NEXT: movslq %edi, %rax |
| 1062 | ; SSE-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) |
| 1063 | ; SSE-NEXT: movslq %edx, %rdx |
| 1064 | ; SSE-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 1065 | ; SSE-NEXT: movslq %ecx, %rcx |
| 1066 | ; SSE-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 1067 | ; SSE-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 1068 | ; SSE-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 1069 | ; SSE-NEXT: unpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] |
| 1070 | ; SSE-NEXT: unpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] |
| 1071 | ; SSE-NEXT: retq |
| 1072 | ; |
| 1073 | ; AVX-LABEL: var_shuffle_v4f32_v4f32_x0yx_i32: |
| 1074 | ; AVX: # BB#0: |
| 1075 | ; AVX-NEXT: movslq %edi, %rax |
| 1076 | ; AVX-NEXT: vmovaps %xmm1, -{{[0-9]+}}(%rsp) |
| 1077 | ; AVX-NEXT: movslq %edx, %rdx |
| 1078 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 1079 | ; AVX-NEXT: movslq %ecx, %rcx |
| 1080 | ; AVX-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero |
| 1081 | ; AVX-NEXT: vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero |
| 1082 | ; AVX-NEXT: vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero |
| 1083 | ; AVX-NEXT: vunpcklps {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] |
| 1084 | ; AVX-NEXT: vunpcklpd {{.*#+}} xmm0 = xmm0[0],xmm1[0] |
| 1085 | ; AVX-NEXT: retq |
| 1086 | %x0 = extractelement <4 x float> %x, i32 %i0 |
| 1087 | %x1 = extractelement <4 x float> %x, i32 %i1 |
| 1088 | %y2 = extractelement <4 x float> %y, i32 %i2 |
| 1089 | %x3 = extractelement <4 x float> %x, i32 %i3 |
| 1090 | %r0 = insertelement <4 x float> undef, float %x0, i32 0 |
| 1091 | %r1 = insertelement <4 x float> %r0, float 0.0, i32 1 |
| 1092 | %r2 = insertelement <4 x float> %r1, float %y2, i32 2 |
| 1093 | %r3 = insertelement <4 x float> %r2, float %x3, i32 3 |
| 1094 | ret <4 x float> %r3 |
| 1095 | } |
| 1096 | |
| 1097 | define <8 x i16> @var_shuffle_v8i16_v8i16_xyxyxy00_i16(<8 x i16> %x, <8 x i16> %y, i16 %i0, i16 %i1, i16 %i2, i16 %i3, i16 %i4, i16 %i5, i16 %i6, i16 %i7) nounwind { |
| 1098 | ; SSE2-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: |
| 1099 | ; SSE2: # BB#0: |
| 1100 | ; SSE2-NEXT: movswq %di, %r10 |
| 1101 | ; SSE2-NEXT: movswq %si, %rsi |
| 1102 | ; SSE2-NEXT: movswq %dx, %r11 |
| 1103 | ; SSE2-NEXT: movswq %cx, %rcx |
| 1104 | ; SSE2-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 1105 | ; SSE2-NEXT: movswq %r8w, %rdi |
| 1106 | ; SSE2-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) |
| 1107 | ; SSE2-NEXT: movswq %r9w, %rax |
| 1108 | ; SSE2-NEXT: movzwl -24(%rsp,%rsi,2), %esi |
| 1109 | ; SSE2-NEXT: xorl %edx, %edx |
| 1110 | ; SSE2-NEXT: movd %edx, %xmm0 |
| 1111 | ; SSE2-NEXT: movzwl -24(%rsp,%rcx,2), %ecx |
| 1112 | ; SSE2-NEXT: movd %ecx, %xmm1 |
| 1113 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] |
| 1114 | ; SSE2-NEXT: movd %esi, %xmm2 |
| 1115 | ; SSE2-NEXT: movzwl -24(%rsp,%rax,2), %eax |
| 1116 | ; SSE2-NEXT: movd %eax, %xmm3 |
| 1117 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3] |
| 1118 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] |
| 1119 | ; SSE2-NEXT: movzwl -40(%rsp,%r10,2), %eax |
| 1120 | ; SSE2-NEXT: movzwl -40(%rsp,%r11,2), %ecx |
| 1121 | ; SSE2-NEXT: movd %ecx, %xmm1 |
| 1122 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] |
| 1123 | ; SSE2-NEXT: movd %eax, %xmm0 |
| 1124 | ; SSE2-NEXT: movzwl -40(%rsp,%rdi,2), %eax |
| 1125 | ; SSE2-NEXT: movd %eax, %xmm3 |
| 1126 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] |
| 1127 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] |
| 1128 | ; SSE2-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] |
| 1129 | ; SSE2-NEXT: retq |
| 1130 | ; |
| 1131 | ; SSSE3-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: |
| 1132 | ; SSSE3: # BB#0: |
| 1133 | ; SSSE3-NEXT: movswq %di, %r10 |
| 1134 | ; SSSE3-NEXT: movswq %si, %rsi |
| 1135 | ; SSSE3-NEXT: movswq %dx, %r11 |
| 1136 | ; SSSE3-NEXT: movswq %cx, %rcx |
| 1137 | ; SSSE3-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp) |
| 1138 | ; SSSE3-NEXT: movswq %r8w, %rdi |
| 1139 | ; SSSE3-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) |
| 1140 | ; SSSE3-NEXT: movswq %r9w, %rax |
| 1141 | ; SSSE3-NEXT: movzwl -24(%rsp,%rsi,2), %esi |
| 1142 | ; SSSE3-NEXT: xorl %edx, %edx |
| 1143 | ; SSSE3-NEXT: movd %edx, %xmm0 |
| 1144 | ; SSSE3-NEXT: movzwl -24(%rsp,%rcx,2), %ecx |
| 1145 | ; SSSE3-NEXT: movd %ecx, %xmm1 |
| 1146 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] |
| 1147 | ; SSSE3-NEXT: movd %esi, %xmm2 |
| 1148 | ; SSSE3-NEXT: movzwl -24(%rsp,%rax,2), %eax |
| 1149 | ; SSSE3-NEXT: movd %eax, %xmm3 |
| 1150 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm3[0],xmm2[1],xmm3[1],xmm2[2],xmm3[2],xmm2[3],xmm3[3] |
| 1151 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm1[0],xmm2[1],xmm1[1],xmm2[2],xmm1[2],xmm2[3],xmm1[3] |
| 1152 | ; SSSE3-NEXT: movzwl -40(%rsp,%r10,2), %eax |
| 1153 | ; SSSE3-NEXT: movzwl -40(%rsp,%r11,2), %ecx |
| 1154 | ; SSSE3-NEXT: movd %ecx, %xmm1 |
| 1155 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm0[0],xmm1[1],xmm0[1],xmm1[2],xmm0[2],xmm1[3],xmm0[3] |
| 1156 | ; SSSE3-NEXT: movd %eax, %xmm0 |
| 1157 | ; SSSE3-NEXT: movzwl -40(%rsp,%rdi,2), %eax |
| 1158 | ; SSSE3-NEXT: movd %eax, %xmm3 |
| 1159 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1],xmm0[2],xmm3[2],xmm0[3],xmm3[3] |
| 1160 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1],xmm0[2],xmm1[2],xmm0[3],xmm1[3] |
| 1161 | ; SSSE3-NEXT: punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3] |
| 1162 | ; SSSE3-NEXT: retq |
| 1163 | ; |
| 1164 | ; SSE41-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: |
| 1165 | ; SSE41: # BB#0: |
| 1166 | ; SSE41-NEXT: movswq %di, %rax |
| 1167 | ; SSE41-NEXT: movswq %si, %rsi |
| 1168 | ; SSE41-NEXT: movswq %dx, %rdx |
| 1169 | ; SSE41-NEXT: movswq %cx, %r10 |
| 1170 | ; SSE41-NEXT: movdqa %xmm0, -{{[0-9]+}}(%rsp) |
| 1171 | ; SSE41-NEXT: movswq %r8w, %rdi |
| 1172 | ; SSE41-NEXT: movaps %xmm1, -{{[0-9]+}}(%rsp) |
| 1173 | ; SSE41-NEXT: movswq %r9w, %rcx |
| 1174 | ; SSE41-NEXT: movzwl -40(%rsp,%rax,2), %eax |
| 1175 | ; SSE41-NEXT: movd %eax, %xmm1 |
| 1176 | ; SSE41-NEXT: pinsrw $1, -24(%rsp,%rsi,2), %xmm1 |
| 1177 | ; SSE41-NEXT: pinsrw $2, -40(%rsp,%rdx,2), %xmm1 |
| 1178 | ; SSE41-NEXT: pinsrw $3, -24(%rsp,%r10,2), %xmm1 |
| 1179 | ; SSE41-NEXT: pinsrw $4, -40(%rsp,%rdi,2), %xmm1 |
| 1180 | ; SSE41-NEXT: pinsrw $5, -24(%rsp,%rcx,2), %xmm1 |
| 1181 | ; SSE41-NEXT: pxor %xmm0, %xmm0 |
| 1182 | ; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5],xmm0[6,7] |
| 1183 | ; SSE41-NEXT: retq |
| 1184 | ; |
| 1185 | ; AVX-LABEL: var_shuffle_v8i16_v8i16_xyxyxy00_i16: |
| 1186 | ; AVX: # BB#0: |
| 1187 | ; AVX-NEXT: movswq %di, %r10 |
| 1188 | ; AVX-NEXT: movswq %si, %r11 |
| 1189 | ; AVX-NEXT: movswq %dx, %rdx |
| 1190 | ; AVX-NEXT: movswq %cx, %rcx |
| 1191 | ; AVX-NEXT: vmovaps %xmm0, -{{[0-9]+}}(%rsp) |
| 1192 | ; AVX-NEXT: movswq %r8w, %rdi |
| 1193 | ; AVX-NEXT: vmovdqa %xmm1, -{{[0-9]+}}(%rsp) |
| 1194 | ; AVX-NEXT: movswq %r9w, %rax |
| 1195 | ; AVX-NEXT: movzwl -40(%rsp,%r10,2), %esi |
| 1196 | ; AVX-NEXT: vmovd %esi, %xmm0 |
| 1197 | ; AVX-NEXT: vpinsrw $1, -24(%rsp,%r11,2), %xmm0, %xmm0 |
| 1198 | ; AVX-NEXT: vpinsrw $2, -40(%rsp,%rdx,2), %xmm0, %xmm0 |
| 1199 | ; AVX-NEXT: vpinsrw $3, -24(%rsp,%rcx,2), %xmm0, %xmm0 |
| 1200 | ; AVX-NEXT: vpinsrw $4, -40(%rsp,%rdi,2), %xmm0, %xmm0 |
| 1201 | ; AVX-NEXT: vpinsrw $5, -24(%rsp,%rax,2), %xmm0, %xmm0 |
| 1202 | ; AVX-NEXT: vpxor %xmm1, %xmm1, %xmm1 |
| 1203 | ; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7] |
| 1204 | ; AVX-NEXT: retq |
| 1205 | %x0 = extractelement <8 x i16> %x, i16 %i0 |
| 1206 | %y1 = extractelement <8 x i16> %y, i16 %i1 |
| 1207 | %x2 = extractelement <8 x i16> %x, i16 %i2 |
| 1208 | %y3 = extractelement <8 x i16> %y, i16 %i3 |
| 1209 | %x4 = extractelement <8 x i16> %x, i16 %i4 |
| 1210 | %y5 = extractelement <8 x i16> %y, i16 %i5 |
| 1211 | %x6 = extractelement <8 x i16> %x, i16 %i6 |
| 1212 | %x7 = extractelement <8 x i16> %x, i16 %i7 |
| 1213 | %r0 = insertelement <8 x i16> undef, i16 %x0, i32 0 |
| 1214 | %r1 = insertelement <8 x i16> %r0, i16 %y1, i32 1 |
| 1215 | %r2 = insertelement <8 x i16> %r1, i16 %x2, i32 2 |
| 1216 | %r3 = insertelement <8 x i16> %r2, i16 %y3, i32 3 |
| 1217 | %r4 = insertelement <8 x i16> %r3, i16 %x4, i32 4 |
| 1218 | %r5 = insertelement <8 x i16> %r4, i16 %y5, i32 5 |
| 1219 | %r6 = insertelement <8 x i16> %r5, i16 0, i32 6 |
| 1220 | %r7 = insertelement <8 x i16> %r6, i16 0, i32 7 |
| 1221 | ret <8 x i16> %r7 |
| 1222 | } |