| Oliver Stannard | a34e470 | 2015-12-01 10:48:51 +0000 | [diff] [blame] | 1 | # RUN: llvm-mc -triple aarch64-none-linux-gnu -mattr=+spe --disassemble < %s | FileCheck %s |
| 2 | # RUN: llvm-mc -triple aarch64-none-linux-gnu --disassemble < %s | FileCheck --check-prefix=NO_SPE %s |
| 3 | |
| Oliver Stannard | a34e470 | 2015-12-01 10:48:51 +0000 | [diff] [blame] | 4 | [0x3f,0x22,0x03,0xd5] |
| 5 | # CHECK: psb csync |
| 6 | # NO_SPE: hint #0x11 |
| 7 | |
| 8 | [0x00,0x9a,0x18,0xd5] |
| 9 | [0x20,0x9a,0x18,0xd5] |
| 10 | [0x60,0x9a,0x18,0xd5] |
| 11 | [0xe0,0x9a,0x18,0xd5] |
| 12 | [0x00,0x99,0x1c,0xd5] |
| 13 | [0x00,0x99,0x1d,0xd5] |
| 14 | [0x00,0x99,0x18,0xd5] |
| 15 | [0x40,0x99,0x18,0xd5] |
| 16 | [0x60,0x99,0x18,0xd5] |
| 17 | [0x80,0x99,0x18,0xd5] |
| 18 | [0xa0,0x99,0x18,0xd5] |
| 19 | [0xc0,0x99,0x18,0xd5] |
| 20 | [0xe0,0x99,0x18,0xd5] |
| 21 | # CHECK: msr PMBLIMITR_EL1, x0 |
| 22 | # NO_SPE: msr S3_0_C9_C10_0, x0 |
| 23 | # CHECK: msr PMBPTR_EL1, x0 |
| 24 | # NO_SPE: msr S3_0_C9_C10_1, x0 |
| 25 | # CHECK: msr PMBSR_EL1, x0 |
| 26 | # NO_SPE: msr S3_0_C9_C10_3, x0 |
| 27 | # CHECK: msr PMBIDR_EL1, x0 |
| 28 | # NO_SPE: msr S3_0_C9_C10_7, x0 |
| 29 | # CHECK: msr PMSCR_EL2, x0 |
| 30 | # NO_SPE: msr S3_4_C9_C9_0, x0 |
| 31 | # CHECK: msr PMSCR_EL12, x0 |
| 32 | # NO_SPE: msr S3_5_C9_C9_0, x0 |
| 33 | # CHECK: msr PMSCR_EL1, x0 |
| 34 | # NO_SPE: msr S3_0_C9_C9_0, x0 |
| 35 | # CHECK: msr PMSICR_EL1, x0 |
| 36 | # NO_SPE: msr S3_0_C9_C9_2, x0 |
| 37 | # CHECK: msr PMSIRR_EL1, x0 |
| 38 | # NO_SPE: msr S3_0_C9_C9_3, x0 |
| 39 | # CHECK: msr PMSFCR_EL1, x0 |
| 40 | # NO_SPE: msr S3_0_C9_C9_4, x0 |
| 41 | # CHECK: msr PMSEVFR_EL1, x0 |
| 42 | # NO_SPE: msr S3_0_C9_C9_5, x0 |
| 43 | # CHECK: msr PMSLATFR_EL1, x0 |
| 44 | # NO_SPE: msr S3_0_C9_C9_6, x0 |
| 45 | # CHECK: msr PMSIDR_EL1, x0 |
| 46 | # NO_SPE: msr S3_0_C9_C9_7, x0 |
| 47 | |
| 48 | [0x00,0x9a,0x38,0xd5] |
| 49 | [0x20,0x9a,0x38,0xd5] |
| 50 | [0x60,0x9a,0x38,0xd5] |
| 51 | [0xe0,0x9a,0x38,0xd5] |
| 52 | [0x00,0x99,0x3c,0xd5] |
| 53 | [0x00,0x99,0x3d,0xd5] |
| 54 | [0x00,0x99,0x38,0xd5] |
| 55 | [0x40,0x99,0x38,0xd5] |
| 56 | [0x60,0x99,0x38,0xd5] |
| 57 | [0x80,0x99,0x38,0xd5] |
| 58 | [0xa0,0x99,0x38,0xd5] |
| 59 | [0xc0,0x99,0x38,0xd5] |
| 60 | [0xe0,0x99,0x38,0xd5] |
| 61 | |
| 62 | # CHECK: mrs x0, PMBLIMITR_EL1 |
| 63 | # NO_SPE: mrs x0, S3_0_C9_C10_0 |
| 64 | # CHECK: mrs x0, PMBPTR_EL1 |
| 65 | # NO_SPE: mrs x0, S3_0_C9_C10_1 |
| 66 | # CHECK: mrs x0, PMBSR_EL1 |
| 67 | # NO_SPE: mrs x0, S3_0_C9_C10_3 |
| 68 | # CHECK: mrs x0, PMBIDR_EL1 |
| 69 | # NO_SPE: mrs x0, S3_0_C9_C10_7 |
| 70 | # CHECK: mrs x0, PMSCR_EL2 |
| 71 | # NO_SPE: mrs x0, S3_4_C9_C9_0 |
| 72 | # CHECK: mrs x0, PMSCR_EL12 |
| 73 | # NO_SPE: mrs x0, S3_5_C9_C9_0 |
| 74 | # CHECK: mrs x0, PMSCR_EL1 |
| 75 | # NO_SPE: mrs x0, S3_0_C9_C9_0 |
| 76 | # CHECK: mrs x0, PMSICR_EL1 |
| 77 | # NO_SPE: mrs x0, S3_0_C9_C9_2 |
| 78 | # CHECK: mrs x0, PMSIRR_EL1 |
| 79 | # NO_SPE: mrs x0, S3_0_C9_C9_3 |
| 80 | # CHECK: mrs x0, PMSFCR_EL1 |
| 81 | # NO_SPE: mrs x0, S3_0_C9_C9_4 |
| 82 | # CHECK: mrs x0, PMSEVFR_EL1 |
| 83 | # NO_SPE: mrs x0, S3_0_C9_C9_5 |
| 84 | # CHECK: mrs x0, PMSLATFR_EL1 |
| 85 | # NO_SPE: mrs x0, S3_0_C9_C9_6 |
| 86 | # CHECK: mrs x0, PMSIDR_EL1 |
| 87 | # NO_SPE: mrs x0, S3_0_C9_C9_7 |