| Vladimir Sukharev | 4b18c72 | 2015-03-26 18:29:02 +0000 | [diff] [blame] | 1 | # RUN: not llvm-mc -triple armv8 -mattr=+v8.1a --disassemble < %s 2>&1 | FileCheck %s |
| 2 | |
| 3 | # Check, if sizes 00 and 11 are undefined for RDMA |
| 4 | [0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2 |
| 5 | # CHECK: warning: invalid instruction encoding |
| 6 | # CHECK-NEXT: [0x12,0x0b,0x01,0xf3] # vqrdmlah.s8 d0, d1, d2 |
| 7 | # CHECK-NEXT: ^ |
| 8 | |
| 9 | [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2 |
| 10 | # CHECK: warning: invalid instruction encoding |
| 11 | # CHECK-NEXT: [0x12,0x0b,0x31,0xf3] # vqrdmlah.s64 d0, d1, d2 |
| 12 | # CHECK-NEXT: ^ |
| 13 | |
| 14 | [0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2 |
| 15 | # CHECK: warning: invalid instruction encoding |
| 16 | # CHECK-NEXT: [0x54,0x0b,0x02,0xf3] # vqrdmlah.s8 q0, q1, q2 |
| 17 | # CHECK-NEXT: ^ |
| 18 | |
| 19 | [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0 |
| 20 | # CHECK: warning: invalid instruction encoding |
| 21 | # CHECK-NEXT: [0x54,0x0b,0x32,0xf3] # vqrdmlah.s64 q2, q3, q0 |
| 22 | # CHECK-NEXT: ^ |
| 23 | |
| 24 | [0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2 |
| 25 | # CHECK: warning: invalid instruction encoding |
| 26 | # CHECK-NEXT: [0x15,0x7c,0x06,0xf3] # vqrdmlsh.s8 d0, d1, d2 |
| 27 | # CHECK-NEXT: ^ |
| 28 | |
| 29 | [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2 |
| 30 | # CHECK: warning: invalid instruction encoding |
| 31 | # CHECK-NEXT: [0x15,0x7c,0x36,0xf3] # vqrdmlsh.s64 d0, d1, d2 |
| 32 | # CHECK-NEXT: ^ |
| 33 | |
| 34 | [0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2 |
| 35 | # CHECK: warning: invalid instruction encoding |
| 36 | # CHECK-NEXT: [0x54,0x0c,0x02,0xf3] # vqrdmlsh.s8 q0, q1, q2 |
| 37 | # CHECK-NEXT: ^ |
| 38 | |
| 39 | [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2 |
| 40 | # CHECK: warning: invalid instruction encoding |
| 41 | # CHECK-NEXT: [0x54,0x0c,0x32,0xf3] # vqrdmlsh.s64 q0, q1, q2 |
| 42 | # CHECK-NEXT: ^ |
| 43 | |
| 44 | [0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0] |
| 45 | # CHECK: warning: invalid instruction encoding |
| 46 | # CHECK-NEXT: [0x42,0x0e,0x81,0xf2] # vqrdmlah.s8 d0, d1, d2[0] |
| 47 | # CHECK-NEXT: ^ |
| 48 | |
| 49 | [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0] |
| 50 | # CHECK: warning: invalid instruction encoding |
| 51 | # CHECK-NEXT: [0x42,0x0e,0xb1,0xf2] # vqrdmlah.s64 d0, d1, d2[0] |
| 52 | # CHECK-NEXT: ^ |
| 53 | |
| 54 | [0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0] |
| 55 | # CHECK: warning: invalid instruction encoding |
| 56 | # CHECK-NEXT: [0x42,0x0e,0x82,0xf3] # vqrdmlah.s8 q0, q1, d2[0] |
| 57 | # CHECK-NEXT: ^ |
| 58 | |
| 59 | [0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0] |
| 60 | # CHECK: warning: invalid instruction encoding |
| 61 | # CHECK-NEXT: [0x42,0x0e,0xb2,0xf3] # vqrdmlah.s64 q0, q1, d2[0] |
| 62 | # CHECK-NEXT: ^ |
| 63 | |
| 64 | |
| 65 | [0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0] |
| 66 | # CHECK: warning: invalid instruction encoding |
| 67 | # CHECK-NEXT: [0x42,0x0f,0x81,0xf2] # vqrdmlsh.s8 d0, d1, d2[0] |
| 68 | # CHECK-NEXT: ^ |
| 69 | |
| 70 | [0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0] |
| 71 | # CHECK: warning: invalid instruction encoding |
| 72 | # CHECK-NEXT: [0x42,0x0f,0xb1,0xf2] # vqrdmlsh.s64 d0, d1, d2[0] |
| 73 | # CHECK-NEXT: ^ |
| 74 | |
| 75 | [0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0] |
| 76 | # CHECK: warning: invalid instruction encoding |
| 77 | # CHECK-NEXT: [0x42,0x0f,0x82,0xf3] # vqrdmlsh.s8 q0, q1, d2[0] |
| 78 | # CHECK-NEXT: ^ |
| 79 | |
| 80 | [0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0] |
| 81 | # CHECK: warning: invalid instruction encoding |
| 82 | # CHECK-NEXT: [0x42,0x0f,0xb2,0xf3] # vqrdmlsh.s64 q0, q1, d2[0] |
| 83 | # CHECK-NEXT: ^ |