blob: 220965ce66034949b633a177c12fe1c7b5d23cf7 [file] [log] [blame]
Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
17#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000018#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000019#include "llvm/Target/TargetSubtargetInfo.h"
20
21using namespace llvm;
22
Quentin Colombet000b5802016-03-11 17:27:51 +000023void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000024 this->MF = &MF;
25 this->MBB = nullptr;
26 this->TII = MF.getSubtarget().getInstrInfo();
27 this->DL = DebugLoc();
28 this->MI = nullptr;
29}
30
Quentin Colombet91ebd712016-03-11 17:27:47 +000031void MachineIRBuilder::setMBB(MachineBasicBlock &MBB, bool Beginning) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000032 this->MBB = &MBB;
33 Before = Beginning;
34 assert(&getMF() == MBB.getParent() &&
35 "Basic block is in a different function");
36}
37
38void MachineIRBuilder::setInstr(MachineInstr &MI, bool Before) {
39 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000040 setMBB(*MI.getParent());
Quentin Colombet2ad1f852016-02-11 17:44:59 +000041 this->MI = &MI;
42 this->Before = Before;
43}
44
45MachineBasicBlock::iterator MachineIRBuilder::getInsertPt() {
46 if (MI) {
47 if (Before)
48 return MI;
49 if (!MI->getNextNode())
50 return getMBB().end();
51 return MI->getNextNode();
52 }
53 return Before ? getMBB().begin() : getMBB().end();
54}
55
Quentin Colombetf9b49342016-03-11 17:27:58 +000056//------------------------------------------------------------------------------
57// Build instruction variants.
58//------------------------------------------------------------------------------
Tim Northover62ae5682016-07-20 19:09:30 +000059MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty) {
Quentin Colombetf9b49342016-03-11 17:27:58 +000060 MachineInstr *NewMI = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northover62ae5682016-07-20 19:09:30 +000061 if (Ty.isValid()) {
Quentin Colombet8fd67182016-02-11 21:16:56 +000062 assert(isPreISelGenericOpcode(Opcode) &&
63 "Only generic instruction can have a type");
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000064 NewMI->setType(Ty);
Quentin Colombet8fd67182016-02-11 21:16:56 +000065 } else
66 assert(!isPreISelGenericOpcode(Opcode) &&
67 "Generic instruction must have a type");
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000068 getMBB().insert(getInsertPt(), NewMI);
69 return NewMI;
70}
71
72MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res,
Quentin Colombetf9b49342016-03-11 17:27:58 +000073 unsigned Op0, unsigned Op1) {
Tim Northover62ae5682016-07-20 19:09:30 +000074 return buildInstr(Opcode, LLT{}, Res, Op0, Op1);
Quentin Colombetf9b49342016-03-11 17:27:58 +000075}
Quentin Colombet8fd67182016-02-11 21:16:56 +000076
Tim Northover62ae5682016-07-20 19:09:30 +000077MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty,
Quentin Colombetf9b49342016-03-11 17:27:58 +000078 unsigned Res, unsigned Op0,
79 unsigned Op1) {
80 MachineInstr *NewMI = buildInstr(Opcode, Ty);
81 MachineInstrBuilder(getMF(), NewMI)
82 .addReg(Res, RegState::Define)
83 .addReg(Op0)
84 .addReg(Op1);
85 return NewMI;
86}
87
88MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, unsigned Res,
89 unsigned Op0) {
Tim Northover62ae5682016-07-20 19:09:30 +000090 MachineInstr *NewMI = buildInstr(Opcode, LLT{});
Quentin Colombetf9b49342016-03-11 17:27:58 +000091 MachineInstrBuilder(getMF(), NewMI).addReg(Res, RegState::Define).addReg(Op0);
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000092 return NewMI;
93}
94
95MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northover62ae5682016-07-20 19:09:30 +000096 return buildInstr(Opcode, LLT{});
Quentin Colombet2ad1f852016-02-11 17:44:59 +000097}
Quentin Colombetdd4b1372016-03-11 17:28:03 +000098
Tim Northover62ae5682016-07-20 19:09:30 +000099MachineInstr *MachineIRBuilder::buildInstr(unsigned Opcode, LLT Ty,
Quentin Colombetdd4b1372016-03-11 17:28:03 +0000100 MachineBasicBlock &BB) {
101 MachineInstr *NewMI = buildInstr(Opcode, Ty);
102 MachineInstrBuilder(getMF(), NewMI).addMBB(&BB);
103 return NewMI;
104}
Tim Northoverbd505462016-07-22 16:59:52 +0000105
106MachineInstr *MachineIRBuilder::buildFrameIndex(LLT Ty, unsigned Res, int Idx) {
107 MachineInstr *NewMI = buildInstr(TargetOpcode::G_FRAME_INDEX, Ty);
108 auto MIB = MachineInstrBuilder(getMF(), NewMI);
109 MIB.addReg(Res, RegState::Define);
110 MIB.addImm(Idx);
111 return NewMI;
112}