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Colin LeMahieu2c769202014-11-06 17:05:51 +00001//===-- HexagonAsmBackend.cpp - Hexagon Assembler Backend -----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Colin LeMahieu86f218e2015-05-30 18:55:47 +000010#include "Hexagon.h"
11#include "HexagonFixupKinds.h"
Colin LeMahieu2c769202014-11-06 17:05:51 +000012#include "HexagonMCTargetDesc.h"
Colin LeMahieu86f218e2015-05-30 18:55:47 +000013#include "MCTargetDesc/HexagonBaseInfo.h"
14#include "MCTargetDesc/HexagonMCInstrInfo.h"
Colin LeMahieu2c769202014-11-06 17:05:51 +000015#include "llvm/MC/MCAsmBackend.h"
Colin LeMahieu86f218e2015-05-30 18:55:47 +000016#include "llvm/MC/MCAssembler.h"
Colin LeMahieu2c769202014-11-06 17:05:51 +000017#include "llvm/MC/MCELFObjectWriter.h"
Colin LeMahieua6750772015-06-03 17:34:16 +000018#include "llvm/MC/MCFixupKindInfo.h"
Colin LeMahieube8c4532015-06-05 16:00:11 +000019#include "llvm/MC/MCInstrInfo.h"
Colin LeMahieua6750772015-06-03 17:34:16 +000020#include "llvm/Support/TargetRegistry.h"
Colin LeMahieu2c769202014-11-06 17:05:51 +000021
22using namespace llvm;
Colin LeMahieu86f218e2015-05-30 18:55:47 +000023using namespace Hexagon;
Colin LeMahieu2c769202014-11-06 17:05:51 +000024
25namespace {
26
27class HexagonAsmBackend : public MCAsmBackend {
Colin LeMahieua6750772015-06-03 17:34:16 +000028 uint8_t OSABI;
29 StringRef CPU;
Colin LeMahieu86f218e2015-05-30 18:55:47 +000030 mutable uint64_t relaxedCnt;
31 std::unique_ptr <MCInstrInfo> MCII;
32 std::unique_ptr <MCInst *> RelaxTarget;
Colin LeMahieu2c769202014-11-06 17:05:51 +000033public:
Colin LeMahieua6750772015-06-03 17:34:16 +000034 HexagonAsmBackend(Target const &T, uint8_t OSABI, StringRef CPU) :
35 OSABI(OSABI), MCII (T.createMCInstrInfo()), RelaxTarget(new MCInst *){}
Colin LeMahieu2c769202014-11-06 17:05:51 +000036
Colin LeMahieua6750772015-06-03 17:34:16 +000037 MCObjectWriter *createObjectWriter(raw_pwrite_stream &OS) const override {
38 return createHexagonELFObjectWriter(OS, OSABI, CPU);
39 }
40
41 unsigned getNumFixupKinds() const override {
42 return Hexagon::NumTargetFixupKinds;
43 }
44
45 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override {
46 const static MCFixupKindInfo Infos[Hexagon::NumTargetFixupKinds] = {
47 // This table *must* be in same the order of fixup_* kinds in
48 // HexagonFixupKinds.h.
49 //
50 // namei offset bits flags
51 {"fixup_Hexagon_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
52 {"fixup_Hexagon_B15_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
53 {"fixup_Hexagon_B7_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
54 {"fixup_Hexagon_LO16", 0, 32, 0},
55 {"fixup_Hexagon_HI16", 0, 32, 0},
56 {"fixup_Hexagon_32", 0, 32, 0},
57 {"fixup_Hexagon_16", 0, 32, 0},
58 {"fixup_Hexagon_8", 0, 32, 0},
59 {"fixup_Hexagon_GPREL16_0", 0, 32, 0},
60 {"fixup_Hexagon_GPREL16_1", 0, 32, 0},
61 {"fixup_Hexagon_GPREL16_2", 0, 32, 0},
62 {"fixup_Hexagon_GPREL16_3", 0, 32, 0},
63 {"fixup_Hexagon_HL16", 0, 32, 0},
64 {"fixup_Hexagon_B13_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
65 {"fixup_Hexagon_B9_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
66 {"fixup_Hexagon_B32_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
67 {"fixup_Hexagon_32_6_X", 0, 32, 0},
68 {"fixup_Hexagon_B22_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
69 {"fixup_Hexagon_B15_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
70 {"fixup_Hexagon_B13_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
71 {"fixup_Hexagon_B9_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
72 {"fixup_Hexagon_B7_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
73 {"fixup_Hexagon_16_X", 0, 32, 0},
74 {"fixup_Hexagon_12_X", 0, 32, 0},
75 {"fixup_Hexagon_11_X", 0, 32, 0},
76 {"fixup_Hexagon_10_X", 0, 32, 0},
77 {"fixup_Hexagon_9_X", 0, 32, 0},
78 {"fixup_Hexagon_8_X", 0, 32, 0},
79 {"fixup_Hexagon_7_X", 0, 32, 0},
80 {"fixup_Hexagon_6_X", 0, 32, 0},
81 {"fixup_Hexagon_32_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
82 {"fixup_Hexagon_COPY", 0, 32, 0},
83 {"fixup_Hexagon_GLOB_DAT", 0, 32, 0},
84 {"fixup_Hexagon_JMP_SLOT", 0, 32, 0},
85 {"fixup_Hexagon_RELATIVE", 0, 32, 0},
86 {"fixup_Hexagon_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
87 {"fixup_Hexagon_GOTREL_LO16", 0, 32, 0},
88 {"fixup_Hexagon_GOTREL_HI16", 0, 32, 0},
89 {"fixup_Hexagon_GOTREL_32", 0, 32, 0},
90 {"fixup_Hexagon_GOT_LO16", 0, 32, 0},
91 {"fixup_Hexagon_GOT_HI16", 0, 32, 0},
92 {"fixup_Hexagon_GOT_32", 0, 32, 0},
93 {"fixup_Hexagon_GOT_16", 0, 32, 0},
94 {"fixup_Hexagon_DTPMOD_32", 0, 32, 0},
95 {"fixup_Hexagon_DTPREL_LO16", 0, 32, 0},
96 {"fixup_Hexagon_DTPREL_HI16", 0, 32, 0},
97 {"fixup_Hexagon_DTPREL_32", 0, 32, 0},
98 {"fixup_Hexagon_DTPREL_16", 0, 32, 0},
99 {"fixup_Hexagon_GD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
100 {"fixup_Hexagon_LD_PLT_B22_PCREL", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
101 {"fixup_Hexagon_GD_GOT_LO16", 0, 32, 0},
102 {"fixup_Hexagon_GD_GOT_HI16", 0, 32, 0},
103 {"fixup_Hexagon_GD_GOT_32", 0, 32, 0},
104 {"fixup_Hexagon_GD_GOT_16", 0, 32, 0},
105 {"fixup_Hexagon_LD_GOT_LO16", 0, 32, 0},
106 {"fixup_Hexagon_LD_GOT_HI16", 0, 32, 0},
107 {"fixup_Hexagon_LD_GOT_32", 0, 32, 0},
108 {"fixup_Hexagon_LD_GOT_16", 0, 32, 0},
109 {"fixup_Hexagon_IE_LO16", 0, 32, 0},
110 {"fixup_Hexagon_IE_HI16", 0, 32, 0},
111 {"fixup_Hexagon_IE_32", 0, 32, 0},
112 {"fixup_Hexagon_IE_16", 0, 32, 0},
113 {"fixup_Hexagon_IE_GOT_LO16", 0, 32, 0},
114 {"fixup_Hexagon_IE_GOT_HI16", 0, 32, 0},
115 {"fixup_Hexagon_IE_GOT_32", 0, 32, 0},
116 {"fixup_Hexagon_IE_GOT_16", 0, 32, 0},
117 {"fixup_Hexagon_TPREL_LO16", 0, 32, 0},
118 {"fixup_Hexagon_TPREL_HI16", 0, 32, 0},
119 {"fixup_Hexagon_TPREL_32", 0, 32, 0},
120 {"fixup_Hexagon_TPREL_16", 0, 32, 0},
121 {"fixup_Hexagon_6_PCREL_X", 0, 32, MCFixupKindInfo::FKF_IsPCRel},
122 {"fixup_Hexagon_GOTREL_32_6_X", 0, 32, 0},
123 {"fixup_Hexagon_GOTREL_16_X", 0, 32, 0},
124 {"fixup_Hexagon_GOTREL_11_X", 0, 32, 0},
125 {"fixup_Hexagon_GOT_32_6_X", 0, 32, 0},
126 {"fixup_Hexagon_GOT_16_X", 0, 32, 0},
127 {"fixup_Hexagon_GOT_11_X", 0, 32, 0},
128 {"fixup_Hexagon_DTPREL_32_6_X", 0, 32, 0},
129 {"fixup_Hexagon_DTPREL_16_X", 0, 32, 0},
130 {"fixup_Hexagon_DTPREL_11_X", 0, 32, 0},
131 {"fixup_Hexagon_GD_GOT_32_6_X", 0, 32, 0},
132 {"fixup_Hexagon_GD_GOT_16_X", 0, 32, 0},
133 {"fixup_Hexagon_GD_GOT_11_X", 0, 32, 0},
134 {"fixup_Hexagon_LD_GOT_32_6_X", 0, 32, 0},
135 {"fixup_Hexagon_LD_GOT_16_X", 0, 32, 0},
136 {"fixup_Hexagon_LD_GOT_11_X", 0, 32, 0},
137 {"fixup_Hexagon_IE_32_6_X", 0, 32, 0},
138 {"fixup_Hexagon_IE_16_X", 0, 32, 0},
139 {"fixup_Hexagon_IE_GOT_32_6_X", 0, 32, 0},
140 {"fixup_Hexagon_IE_GOT_16_X", 0, 32, 0},
141 {"fixup_Hexagon_IE_GOT_11_X", 0, 32, 0},
142 {"fixup_Hexagon_TPREL_32_6_X", 0, 32, 0},
143 {"fixup_Hexagon_TPREL_16_X", 0, 32, 0},
144 {"fixup_Hexagon_TPREL_11_X", 0, 32, 0}};
145
146 if (Kind < FirstTargetFixupKind) {
147 return MCAsmBackend::getFixupKindInfo(Kind);
148 }
149
150 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
151 "Invalid kind!");
152 return Infos[Kind - FirstTargetFixupKind];
153 }
Colin LeMahieu2c769202014-11-06 17:05:51 +0000154
155 void applyFixup(MCFixup const & /*Fixup*/, char * /*Data*/,
156 unsigned /*DataSize*/, uint64_t /*Value*/,
157 bool /*IsPCRel*/) const override {
158 return;
159 }
160
Colin LeMahieu86f218e2015-05-30 18:55:47 +0000161 bool isInstRelaxable(MCInst const &HMI) const {
162 const MCInstrDesc &MCID = HexagonMCInstrInfo::getDesc(*MCII, HMI);
Colin LeMahieu86f218e2015-05-30 18:55:47 +0000163 bool Relaxable = false;
164 // Branches and loop-setup insns are handled as necessary by relaxation.
165 if (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeJ ||
166 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeNV &&
167 MCID.isBranch()) ||
168 (llvm::HexagonMCInstrInfo::getType(*MCII, HMI) == HexagonII::TypeCR &&
169 HMI.getOpcode() != Hexagon::C4_addipc))
170 if (HexagonMCInstrInfo::isExtendable(*MCII, HMI))
171 Relaxable = true;
172
173 return Relaxable;
174 }
175
176 /// MayNeedRelaxation - Check whether the given instruction may need
177 /// relaxation.
178 ///
179 /// \param Inst - The instruction to test.
Colin LeMahieub510fb32015-05-30 20:03:07 +0000180 bool mayNeedRelaxation(MCInst const &Inst) const override {
Colin LeMahieu86f218e2015-05-30 18:55:47 +0000181 assert(HexagonMCInstrInfo::isBundle(Inst));
182 bool PreviousIsExtender = false;
183 for (auto const &I : HexagonMCInstrInfo::bundleInstructions(Inst)) {
184 auto const &Inst = *I.getInst();
185 if (!PreviousIsExtender) {
186 if (isInstRelaxable(Inst))
187 return true;
188 }
189 PreviousIsExtender = HexagonMCInstrInfo::isImmext(Inst);
190 }
Colin LeMahieu2c769202014-11-06 17:05:51 +0000191 return false;
192 }
193
Colin LeMahieu86f218e2015-05-30 18:55:47 +0000194 /// fixupNeedsRelaxation - Target specific predicate for whether a given
195 /// fixup requires the associated instruction to be relaxed.
196 bool fixupNeedsRelaxationAdvanced(const MCFixup &Fixup, bool Resolved,
197 uint64_t Value,
198 const MCRelaxableFragment *DF,
Colin LeMahieub510fb32015-05-30 20:03:07 +0000199 const MCAsmLayout &Layout) const override {
Colin LeMahieu86f218e2015-05-30 18:55:47 +0000200 MCInst const &MCB = DF->getInst();
201 assert(HexagonMCInstrInfo::isBundle(MCB));
202
203 *RelaxTarget = nullptr;
204 MCInst &MCI = const_cast<MCInst &>(HexagonMCInstrInfo::instruction(
205 MCB, Fixup.getOffset() / HEXAGON_INSTR_SIZE));
206 // If we cannot resolve the fixup value, it requires relaxation.
207 if (!Resolved) {
208 switch ((unsigned)Fixup.getKind()) {
209 case fixup_Hexagon_B22_PCREL:
210 // GetFixupCount assumes B22 won't relax
211 // Fallthrough
212 default:
213 return false;
214 break;
215 case fixup_Hexagon_B13_PCREL:
216 case fixup_Hexagon_B15_PCREL:
217 case fixup_Hexagon_B9_PCREL:
218 case fixup_Hexagon_B7_PCREL: {
219 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
220 ++relaxedCnt;
221 *RelaxTarget = &MCI;
222 return true;
223 } else {
224 return false;
225 }
226 break;
227 }
228 }
229 }
230 bool Relaxable = isInstRelaxable(MCI);
231 if (Relaxable == false)
232 return false;
233
234 MCFixupKind Kind = Fixup.getKind();
235 int64_t sValue = Value;
236 int64_t maxValue;
237
238 switch ((unsigned)Kind) {
239 case fixup_Hexagon_B7_PCREL:
240 maxValue = 1 << 8;
241 break;
242 case fixup_Hexagon_B9_PCREL:
243 maxValue = 1 << 10;
244 break;
245 case fixup_Hexagon_B15_PCREL:
246 maxValue = 1 << 16;
247 break;
248 case fixup_Hexagon_B22_PCREL:
249 maxValue = 1 << 23;
250 break;
251 default:
252 maxValue = INT64_MAX;
253 break;
254 }
255
256 bool isFarAway = -maxValue > sValue || sValue > maxValue - 1;
257
258 if (isFarAway) {
259 if (HexagonMCInstrInfo::bundleSize(MCB) < HEXAGON_PACKET_SIZE) {
260 ++relaxedCnt;
261 *RelaxTarget = &MCI;
262 return true;
263 }
264 }
265
266 return false;
267 }
268
269 /// Simple predicate for targets where !Resolved implies requiring relaxation
270 bool fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value,
271 const MCRelaxableFragment *DF,
272 const MCAsmLayout &Layout) const override {
273 llvm_unreachable("Handled by fixupNeedsRelaxationAdvanced");
Colin LeMahieu2c769202014-11-06 17:05:51 +0000274 }
275
276 void relaxInstruction(MCInst const & /*Inst*/,
277 MCInst & /*Res*/) const override {
278 llvm_unreachable("relaxInstruction() unimplemented");
279 }
280
281 bool writeNopData(uint64_t /*Count*/,
282 MCObjectWriter * /*OW*/) const override {
283 return true;
284 }
285};
286} // end anonymous namespace
287
Colin LeMahieu2c769202014-11-06 17:05:51 +0000288namespace llvm {
289MCAsmBackend *createHexagonAsmBackend(Target const &T,
290 MCRegisterInfo const & /*MRI*/,
Colin LeMahieua6750772015-06-03 17:34:16 +0000291 StringRef TT, StringRef CPU) {
Colin LeMahieu2c769202014-11-06 17:05:51 +0000292 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS());
Colin LeMahieua6750772015-06-03 17:34:16 +0000293 return new HexagonAsmBackend(T, OSABI, CPU);
Colin LeMahieu2c769202014-11-06 17:05:51 +0000294}
295}