Krzysztof Parzyszek | d91a9e2 | 2018-08-02 22:17:53 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=hexagon -hexagon-initial-cfg-cleanup=0 < %s | FileCheck %s |
Krzysztof Parzyszek | 9f041b1 | 2018-03-26 16:50:11 +0000 | [diff] [blame] | 2 | |
| 3 | ; Test that the pipeliner schedules a store before the load in which there is a |
| 4 | ; loop carried dependence. Previously, the loop carried dependence wasn't added |
| 5 | ; and the load from iteration n was scheduled prior to the store from iteration |
| 6 | ; n-1. |
| 7 | |
| 8 | ; CHECK: loop0(.LBB0_[[LOOP:.]], |
| 9 | ; CHECK: .LBB0_[[LOOP]]: |
| 10 | ; CHECK: memh({{.*}}) = |
| 11 | ; CHECK: = memuh({{.*}}) |
| 12 | ; CHECK: endloop0 |
| 13 | |
| 14 | %s.0 = type { i16, i16 } |
| 15 | |
| 16 | ; Function Attrs: nounwind |
| 17 | define void @f0() local_unnamed_addr #0 { |
| 18 | b0: |
| 19 | br label %b1 |
| 20 | |
| 21 | b1: ; preds = %b1, %b0 |
| 22 | %v0 = phi i32 [ 0, %b0 ], [ %v22, %b1 ] |
| 23 | %v1 = load %s.0*, %s.0** undef, align 4 |
| 24 | %v2 = getelementptr inbounds %s.0, %s.0* %v1, i32 0, i32 0 |
| 25 | %v3 = load i16, i16* %v2, align 2 |
| 26 | %v4 = add i16 0, %v3 |
| 27 | %v5 = add i16 %v4, 0 |
| 28 | %v6 = add i16 %v5, 0 |
| 29 | %v7 = add i16 %v6, 0 |
| 30 | %v8 = add i16 %v7, 0 |
| 31 | %v9 = add i16 %v8, 0 |
| 32 | %v10 = add i16 %v9, 0 |
| 33 | %v11 = add i16 %v10, 0 |
| 34 | %v12 = add i16 %v11, 0 |
| 35 | %v13 = add i16 %v12, 0 |
| 36 | %v14 = add i16 %v13, 0 |
| 37 | %v15 = add i16 %v14, 0 |
| 38 | %v16 = add i16 %v15, 0 |
| 39 | %v17 = add i16 %v16, 0 |
| 40 | %v18 = add i16 %v17, 0 |
| 41 | %v19 = add i16 %v18, 0 |
| 42 | %v20 = load %s.0*, %s.0** undef, align 4 |
| 43 | store i16 %v19, i16* undef, align 2 |
| 44 | %v21 = getelementptr inbounds %s.0, %s.0* %v20, i32 0, i32 1 |
| 45 | store i16 0, i16* %v21, align 2 |
| 46 | %v22 = add nuw nsw i32 %v0, 1 |
| 47 | %v23 = icmp eq i32 %v22, 6 |
| 48 | br i1 %v23, label %b2, label %b1 |
| 49 | |
| 50 | b2: ; preds = %b1 |
| 51 | ret void |
| 52 | } |
| 53 | |
| 54 | attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx-length64b,+hvxv60" } |