| Nemanja Ivanovic | 6a39d32 | 2018-09-18 13:21:58 +0000 | [diff] [blame] | 1 | ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \ |
| 3 | ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s |
| 4 | ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \ |
| 5 | ; RUN: -mcpu=pwr8 -ppc-asm-full-reg-names < %s | FileCheck %s |
| 6 | define float @floatundisf(i64 %a) { |
| 7 | ; CHECK-LABEL: floatundisf: |
| 8 | ; CHECK: # %bb.0: # %entry |
| 9 | ; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_2 |
| 10 | ; CHECK-NEXT: # %bb.1: |
| 11 | ; CHECK-NEXT: xxlxor f1, f1, f1 |
| 12 | ; CHECK-NEXT: blr |
| 13 | ; CHECK-NEXT: .LBB0_2: # %sw.epilog |
| 14 | ; CHECK-NEXT: addi r3, r3, 1 |
| 15 | ; CHECK-NEXT: li r5, 2 |
| 16 | ; CHECK-NEXT: andis. r4, r3, 1024 |
| 17 | ; CHECK-NEXT: li r4, 3 |
| 18 | ; CHECK-NEXT: isel r4, r5, r4, eq |
| 19 | ; CHECK-NEXT: srd r3, r3, r4 |
| 20 | ; CHECK-NEXT: rlwinm r3, r3, 0, 9, 31 |
| 21 | ; CHECK-NEXT: mtvsrd f0, r3 |
| 22 | ; CHECK-NEXT: xxsldwi vs0, vs0, vs0, 1 |
| 23 | ; CHECK-NEXT: xscvspdpn f1, vs0 |
| 24 | ; CHECK-NEXT: blr |
| 25 | entry: |
| 26 | br i1 undef, label %return, label %sw.epilog |
| 27 | |
| 28 | sw.epilog: ; preds = %entry |
| 29 | %or14 = or i64 0, %a |
| 30 | %inc = add i64 %or14, 1 |
| 31 | %and16 = and i64 %inc, 67108864 |
| 32 | %tobool = icmp eq i64 %and16, 0 |
| 33 | %tmp.select.v = select i1 %tobool, i64 2, i64 3 |
| 34 | %tmp.select = lshr i64 %inc, %tmp.select.v |
| 35 | %conv26 = trunc i64 %tmp.select to i32 |
| 36 | %and27 = and i32 %conv26, 8388607 |
| 37 | %or28 = or i32 0, %and27 |
| 38 | %0 = bitcast i32 %or28 to float |
| 39 | br label %return |
| 40 | |
| 41 | return: ; preds = %sw.epilog, %entry |
| 42 | %retval.0 = phi float [ %0, %sw.epilog ], [ 0.000000e+00, %entry ] |
| 43 | ret float %retval.0 |
| 44 | } |