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gerrit-public.fairphone.software / toolchain / llvm-project / c0dc9bb93e017deadee80825381ddcfc5acadc24 / . / llvm / test / CodeGen / RISCV / calling-conv.ll
blob: 1d6f4c50731bf19efeb6261648cf2af0f7d82f40 [file] [log] [blame]
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]3; RUN: | FileCheck -check-prefix=RV32I-FPELIM %s
4; RUN: llc -mtriple=riscv32 -verify-machineinstrs -disable-fp-elim < %s \
5; RUN: | FileCheck -check-prefix=RV32I-WITHFP %s
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]6
7; As well as calling convention details, we check that ra and fp are
8; consistently stored to fp-4 and fp-8.
9
10; Check that on RV32, i64 and double are passed in a pair of registers. Unlike
11; the convention for varargs, this need not be an aligned pair.
12
13define i32 @callee_scalars(i32 %a, i64 %b, i32 %c, i32 %d, double %e) nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]14; RV32I-FPELIM-LABEL: callee_scalars:
15; RV32I-FPELIM: # %bb.0:
16; RV32I-FPELIM-NEXT: addi sp, sp, -32
17; RV32I-FPELIM-NEXT: sw ra, 28(sp)
18; RV32I-FPELIM-NEXT: sw s1, 24(sp)
19; RV32I-FPELIM-NEXT: sw s2, 20(sp)
20; RV32I-FPELIM-NEXT: sw s3, 16(sp)
21; RV32I-FPELIM-NEXT: sw s4, 12(sp)
22; RV32I-FPELIM-NEXT: mv s1, a4
23; RV32I-FPELIM-NEXT: mv s2, a3
24; RV32I-FPELIM-NEXT: mv s3, a1
25; RV32I-FPELIM-NEXT: mv s4, a0
26; RV32I-FPELIM-NEXT: lui a0, %hi(__fixdfsi)
27; RV32I-FPELIM-NEXT: addi a2, a0, %lo(__fixdfsi)
28; RV32I-FPELIM-NEXT: mv a0, a5
29; RV32I-FPELIM-NEXT: mv a1, a6
30; RV32I-FPELIM-NEXT: jalr a2
31; RV32I-FPELIM-NEXT: add a1, s4, s3
32; RV32I-FPELIM-NEXT: add a1, a1, s2
33; RV32I-FPELIM-NEXT: add a1, a1, s1
34; RV32I-FPELIM-NEXT: add a0, a1, a0
35; RV32I-FPELIM-NEXT: lw s4, 12(sp)
36; RV32I-FPELIM-NEXT: lw s3, 16(sp)
37; RV32I-FPELIM-NEXT: lw s2, 20(sp)
38; RV32I-FPELIM-NEXT: lw s1, 24(sp)
39; RV32I-FPELIM-NEXT: lw ra, 28(sp)
40; RV32I-FPELIM-NEXT: addi sp, sp, 32
41; RV32I-FPELIM-NEXT: ret
42;
43; RV32I-WITHFP-LABEL: callee_scalars:
44; RV32I-WITHFP: # %bb.0:
45; RV32I-WITHFP-NEXT: addi sp, sp, -32
46; RV32I-WITHFP-NEXT: sw ra, 28(sp)
47; RV32I-WITHFP-NEXT: sw s0, 24(sp)
48; RV32I-WITHFP-NEXT: sw s1, 20(sp)
49; RV32I-WITHFP-NEXT: sw s2, 16(sp)
50; RV32I-WITHFP-NEXT: sw s3, 12(sp)
51; RV32I-WITHFP-NEXT: sw s4, 8(sp)
52; RV32I-WITHFP-NEXT: addi s0, sp, 32
53; RV32I-WITHFP-NEXT: mv s1, a4
54; RV32I-WITHFP-NEXT: mv s2, a3
55; RV32I-WITHFP-NEXT: mv s3, a1
56; RV32I-WITHFP-NEXT: mv s4, a0
57; RV32I-WITHFP-NEXT: lui a0, %hi(__fixdfsi)
58; RV32I-WITHFP-NEXT: addi a2, a0, %lo(__fixdfsi)
59; RV32I-WITHFP-NEXT: mv a0, a5
60; RV32I-WITHFP-NEXT: mv a1, a6
61; RV32I-WITHFP-NEXT: jalr a2
62; RV32I-WITHFP-NEXT: add a1, s4, s3
63; RV32I-WITHFP-NEXT: add a1, a1, s2
64; RV32I-WITHFP-NEXT: add a1, a1, s1
65; RV32I-WITHFP-NEXT: add a0, a1, a0
66; RV32I-WITHFP-NEXT: lw s4, 8(sp)
67; RV32I-WITHFP-NEXT: lw s3, 12(sp)
68; RV32I-WITHFP-NEXT: lw s2, 16(sp)
69; RV32I-WITHFP-NEXT: lw s1, 20(sp)
70; RV32I-WITHFP-NEXT: lw s0, 24(sp)
71; RV32I-WITHFP-NEXT: lw ra, 28(sp)
72; RV32I-WITHFP-NEXT: addi sp, sp, 32
73; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]74 %b_trunc = trunc i64 %b to i32
75 %e_fptosi = fptosi double %e to i32
76 %1 = add i32 %a, %b_trunc
77 %2 = add i32 %1, %c
78 %3 = add i32 %2, %d
79 %4 = add i32 %3, %e_fptosi
80 ret i32 %4
81}
82
83define i32 @caller_scalars() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]84; RV32I-FPELIM-LABEL: caller_scalars:
85; RV32I-FPELIM: # %bb.0:
86; RV32I-FPELIM-NEXT: addi sp, sp, -16
87; RV32I-FPELIM-NEXT: sw ra, 12(sp)
88; RV32I-FPELIM-NEXT: lui a0, 262464
89; RV32I-FPELIM-NEXT: mv a6, a0
90; RV32I-FPELIM-NEXT: lui a0, %hi(callee_scalars)
91; RV32I-FPELIM-NEXT: addi a7, a0, %lo(callee_scalars)
92; RV32I-FPELIM-NEXT: addi a0, zero, 1
93; RV32I-FPELIM-NEXT: addi a1, zero, 2
94; RV32I-FPELIM-NEXT: addi a3, zero, 3
95; RV32I-FPELIM-NEXT: addi a4, zero, 4
96; RV32I-FPELIM-NEXT: mv a2, zero
97; RV32I-FPELIM-NEXT: mv a5, zero
98; RV32I-FPELIM-NEXT: jalr a7
99; RV32I-FPELIM-NEXT: lw ra, 12(sp)
100; RV32I-FPELIM-NEXT: addi sp, sp, 16
101; RV32I-FPELIM-NEXT: ret
102;
103; RV32I-WITHFP-LABEL: caller_scalars:
104; RV32I-WITHFP: # %bb.0:
105; RV32I-WITHFP-NEXT: addi sp, sp, -16
106; RV32I-WITHFP-NEXT: sw ra, 12(sp)
107; RV32I-WITHFP-NEXT: sw s0, 8(sp)
108; RV32I-WITHFP-NEXT: addi s0, sp, 16
109; RV32I-WITHFP-NEXT: lui a0, 262464
110; RV32I-WITHFP-NEXT: mv a6, a0
111; RV32I-WITHFP-NEXT: lui a0, %hi(callee_scalars)
112; RV32I-WITHFP-NEXT: addi a7, a0, %lo(callee_scalars)
113; RV32I-WITHFP-NEXT: addi a0, zero, 1
114; RV32I-WITHFP-NEXT: addi a1, zero, 2
115; RV32I-WITHFP-NEXT: addi a3, zero, 3
116; RV32I-WITHFP-NEXT: addi a4, zero, 4
117; RV32I-WITHFP-NEXT: mv a2, zero
118; RV32I-WITHFP-NEXT: mv a5, zero
119; RV32I-WITHFP-NEXT: jalr a7
120; RV32I-WITHFP-NEXT: lw s0, 8(sp)
121; RV32I-WITHFP-NEXT: lw ra, 12(sp)
122; RV32I-WITHFP-NEXT: addi sp, sp, 16
123; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]124 %1 = call i32 @callee_scalars(i32 1, i64 2, i32 3, i32 4, double 5.000000e+00)
125 ret i32 %1
126}
127
128; Check that i128 and fp128 are passed indirectly
129
130define i32 @callee_large_scalars(i128 %a, fp128 %b) nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]131; RV32I-FPELIM-LABEL: callee_large_scalars:
132; RV32I-FPELIM: # %bb.0:
133; RV32I-FPELIM-NEXT: lw a2, 12(a1)
134; RV32I-FPELIM-NEXT: lw a3, 12(a0)
135; RV32I-FPELIM-NEXT: xor a2, a3, a2
136; RV32I-FPELIM-NEXT: lw a3, 4(a1)
137; RV32I-FPELIM-NEXT: lw a4, 4(a0)
138; RV32I-FPELIM-NEXT: xor a3, a4, a3
139; RV32I-FPELIM-NEXT: or a2, a3, a2
140; RV32I-FPELIM-NEXT: lw a3, 8(a1)
141; RV32I-FPELIM-NEXT: lw a4, 8(a0)
142; RV32I-FPELIM-NEXT: xor a3, a4, a3
143; RV32I-FPELIM-NEXT: lw a1, 0(a1)
144; RV32I-FPELIM-NEXT: lw a0, 0(a0)
145; RV32I-FPELIM-NEXT: xor a0, a0, a1
146; RV32I-FPELIM-NEXT: or a0, a0, a3
147; RV32I-FPELIM-NEXT: or a0, a0, a2
148; RV32I-FPELIM-NEXT: xor a0, a0, zero
149; RV32I-FPELIM-NEXT: seqz a0, a0
150; RV32I-FPELIM-NEXT: ret
151;
152; RV32I-WITHFP-LABEL: callee_large_scalars:
153; RV32I-WITHFP: # %bb.0:
154; RV32I-WITHFP-NEXT: addi sp, sp, -16
155; RV32I-WITHFP-NEXT: sw ra, 12(sp)
156; RV32I-WITHFP-NEXT: sw s0, 8(sp)
157; RV32I-WITHFP-NEXT: addi s0, sp, 16
158; RV32I-WITHFP-NEXT: lw a2, 12(a1)
159; RV32I-WITHFP-NEXT: lw a3, 12(a0)
160; RV32I-WITHFP-NEXT: xor a2, a3, a2
161; RV32I-WITHFP-NEXT: lw a3, 4(a1)
162; RV32I-WITHFP-NEXT: lw a4, 4(a0)
163; RV32I-WITHFP-NEXT: xor a3, a4, a3
164; RV32I-WITHFP-NEXT: or a2, a3, a2
165; RV32I-WITHFP-NEXT: lw a3, 8(a1)
166; RV32I-WITHFP-NEXT: lw a4, 8(a0)
167; RV32I-WITHFP-NEXT: xor a3, a4, a3
168; RV32I-WITHFP-NEXT: lw a1, 0(a1)
169; RV32I-WITHFP-NEXT: lw a0, 0(a0)
170; RV32I-WITHFP-NEXT: xor a0, a0, a1
171; RV32I-WITHFP-NEXT: or a0, a0, a3
172; RV32I-WITHFP-NEXT: or a0, a0, a2
173; RV32I-WITHFP-NEXT: xor a0, a0, zero
174; RV32I-WITHFP-NEXT: seqz a0, a0
175; RV32I-WITHFP-NEXT: lw s0, 8(sp)
176; RV32I-WITHFP-NEXT: lw ra, 12(sp)
177; RV32I-WITHFP-NEXT: addi sp, sp, 16
178; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]179 %b_bitcast = bitcast fp128 %b to i128
180 %1 = icmp eq i128 %a, %b_bitcast
181 %2 = zext i1 %1 to i32
182 ret i32 %2
183}
184
185define i32 @caller_large_scalars() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]186; RV32I-FPELIM-LABEL: caller_large_scalars:
187; RV32I-FPELIM: # %bb.0:
188; RV32I-FPELIM-NEXT: addi sp, sp, -48
189; RV32I-FPELIM-NEXT: sw ra, 44(sp)
190; RV32I-FPELIM-NEXT: sw zero, 8(sp)
191; RV32I-FPELIM-NEXT: sw zero, 4(sp)
192; RV32I-FPELIM-NEXT: sw zero, 0(sp)
193; RV32I-FPELIM-NEXT: sw zero, 36(sp)
194; RV32I-FPELIM-NEXT: sw zero, 32(sp)
195; RV32I-FPELIM-NEXT: sw zero, 28(sp)
196; RV32I-FPELIM-NEXT: addi a0, zero, 1
197; RV32I-FPELIM-NEXT: sw a0, 24(sp)
198; RV32I-FPELIM-NEXT: lui a0, 524272
199; RV32I-FPELIM-NEXT: mv a0, a0
200; RV32I-FPELIM-NEXT: sw a0, 12(sp)
201; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars)
202; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_large_scalars)
203; RV32I-FPELIM-NEXT: addi a0, sp, 24
204; RV32I-FPELIM-NEXT: mv a1, sp
205; RV32I-FPELIM-NEXT: jalr a2
206; RV32I-FPELIM-NEXT: lw ra, 44(sp)
207; RV32I-FPELIM-NEXT: addi sp, sp, 48
208; RV32I-FPELIM-NEXT: ret
209;
210; RV32I-WITHFP-LABEL: caller_large_scalars:
211; RV32I-WITHFP: # %bb.0:
212; RV32I-WITHFP-NEXT: addi sp, sp, -48
213; RV32I-WITHFP-NEXT: sw ra, 44(sp)
214; RV32I-WITHFP-NEXT: sw s0, 40(sp)
215; RV32I-WITHFP-NEXT: addi s0, sp, 48
216; RV32I-WITHFP-NEXT: sw zero, -40(s0)
217; RV32I-WITHFP-NEXT: sw zero, -44(s0)
218; RV32I-WITHFP-NEXT: sw zero, -48(s0)
219; RV32I-WITHFP-NEXT: sw zero, -12(s0)
220; RV32I-WITHFP-NEXT: sw zero, -16(s0)
221; RV32I-WITHFP-NEXT: sw zero, -20(s0)
222; RV32I-WITHFP-NEXT: addi a0, zero, 1
223; RV32I-WITHFP-NEXT: sw a0, -24(s0)
224; RV32I-WITHFP-NEXT: lui a0, 524272
225; RV32I-WITHFP-NEXT: mv a0, a0
226; RV32I-WITHFP-NEXT: sw a0, -36(s0)
227; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars)
228; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_large_scalars)
229; RV32I-WITHFP-NEXT: addi a0, s0, -24
230; RV32I-WITHFP-NEXT: addi a1, s0, -48
231; RV32I-WITHFP-NEXT: jalr a2
232; RV32I-WITHFP-NEXT: lw s0, 40(sp)
233; RV32I-WITHFP-NEXT: lw ra, 44(sp)
234; RV32I-WITHFP-NEXT: addi sp, sp, 48
235; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]236 %1 = call i32 @callee_large_scalars(i128 1, fp128 0xL00000000000000007FFF000000000000)
237 ret i32 %1
238}
239
240; Must keep define on a single line due to an update_llc_test_checks.py limitation
241define i32 @callee_large_scalars_exhausted_regs(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i128 %h, i32 %i, fp128 %j) nounwind {
242; Check that arguments larger than 2*xlen are handled correctly when their
243; address is passed on the stack rather than in memory
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]244; RV32I-FPELIM-LABEL: callee_large_scalars_exhausted_regs:
245; RV32I-FPELIM: # %bb.0:
246; RV32I-FPELIM-NEXT: lw a0, 4(sp)
247; RV32I-FPELIM-NEXT: lw a1, 12(a0)
248; RV32I-FPELIM-NEXT: lw a2, 12(a7)
249; RV32I-FPELIM-NEXT: xor a1, a2, a1
250; RV32I-FPELIM-NEXT: lw a2, 4(a0)
251; RV32I-FPELIM-NEXT: lw a3, 4(a7)
252; RV32I-FPELIM-NEXT: xor a2, a3, a2
253; RV32I-FPELIM-NEXT: or a1, a2, a1
254; RV32I-FPELIM-NEXT: lw a2, 8(a0)
255; RV32I-FPELIM-NEXT: lw a3, 8(a7)
256; RV32I-FPELIM-NEXT: xor a2, a3, a2
257; RV32I-FPELIM-NEXT: lw a0, 0(a0)
258; RV32I-FPELIM-NEXT: lw a3, 0(a7)
259; RV32I-FPELIM-NEXT: xor a0, a3, a0
260; RV32I-FPELIM-NEXT: or a0, a0, a2
261; RV32I-FPELIM-NEXT: or a0, a0, a1
262; RV32I-FPELIM-NEXT: xor a0, a0, zero
263; RV32I-FPELIM-NEXT: seqz a0, a0
264; RV32I-FPELIM-NEXT: ret
265;
266; RV32I-WITHFP-LABEL: callee_large_scalars_exhausted_regs:
267; RV32I-WITHFP: # %bb.0:
268; RV32I-WITHFP-NEXT: addi sp, sp, -16
269; RV32I-WITHFP-NEXT: sw ra, 12(sp)
270; RV32I-WITHFP-NEXT: sw s0, 8(sp)
271; RV32I-WITHFP-NEXT: addi s0, sp, 16
272; RV32I-WITHFP-NEXT: lw a0, 4(s0)
273; RV32I-WITHFP-NEXT: lw a1, 12(a0)
274; RV32I-WITHFP-NEXT: lw a2, 12(a7)
275; RV32I-WITHFP-NEXT: xor a1, a2, a1
276; RV32I-WITHFP-NEXT: lw a2, 4(a0)
277; RV32I-WITHFP-NEXT: lw a3, 4(a7)
278; RV32I-WITHFP-NEXT: xor a2, a3, a2
279; RV32I-WITHFP-NEXT: or a1, a2, a1
280; RV32I-WITHFP-NEXT: lw a2, 8(a0)
281; RV32I-WITHFP-NEXT: lw a3, 8(a7)
282; RV32I-WITHFP-NEXT: xor a2, a3, a2
283; RV32I-WITHFP-NEXT: lw a0, 0(a0)
284; RV32I-WITHFP-NEXT: lw a3, 0(a7)
285; RV32I-WITHFP-NEXT: xor a0, a3, a0
286; RV32I-WITHFP-NEXT: or a0, a0, a2
287; RV32I-WITHFP-NEXT: or a0, a0, a1
288; RV32I-WITHFP-NEXT: xor a0, a0, zero
289; RV32I-WITHFP-NEXT: seqz a0, a0
290; RV32I-WITHFP-NEXT: lw s0, 8(sp)
291; RV32I-WITHFP-NEXT: lw ra, 12(sp)
292; RV32I-WITHFP-NEXT: addi sp, sp, 16
293; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]294 %j_bitcast = bitcast fp128 %j to i128
295 %1 = icmp eq i128 %h, %j_bitcast
296 %2 = zext i1 %1 to i32
297 ret i32 %2
298}
299
300define i32 @caller_large_scalars_exhausted_regs() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]301; RV32I-FPELIM-LABEL: caller_large_scalars_exhausted_regs:
302; RV32I-FPELIM: # %bb.0:
303; RV32I-FPELIM-NEXT: addi sp, sp, -64
304; RV32I-FPELIM-NEXT: sw ra, 60(sp)
305; RV32I-FPELIM-NEXT: addi a0, sp, 16
306; RV32I-FPELIM-NEXT: sw a0, 4(sp)
307; RV32I-FPELIM-NEXT: addi a0, zero, 9
308; RV32I-FPELIM-NEXT: sw a0, 0(sp)
309; RV32I-FPELIM-NEXT: sw zero, 24(sp)
310; RV32I-FPELIM-NEXT: sw zero, 20(sp)
311; RV32I-FPELIM-NEXT: sw zero, 16(sp)
312; RV32I-FPELIM-NEXT: sw zero, 52(sp)
313; RV32I-FPELIM-NEXT: sw zero, 48(sp)
314; RV32I-FPELIM-NEXT: sw zero, 44(sp)
315; RV32I-FPELIM-NEXT: addi a0, zero, 8
316; RV32I-FPELIM-NEXT: sw a0, 40(sp)
317; RV32I-FPELIM-NEXT: lui a0, 524272
318; RV32I-FPELIM-NEXT: mv a0, a0
319; RV32I-FPELIM-NEXT: sw a0, 28(sp)
320; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
321; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
322; RV32I-FPELIM-NEXT: addi a0, zero, 1
323; RV32I-FPELIM-NEXT: addi a1, zero, 2
324; RV32I-FPELIM-NEXT: addi a2, zero, 3
325; RV32I-FPELIM-NEXT: addi a3, zero, 4
326; RV32I-FPELIM-NEXT: addi a4, zero, 5
327; RV32I-FPELIM-NEXT: addi a5, zero, 6
328; RV32I-FPELIM-NEXT: addi a6, zero, 7
329; RV32I-FPELIM-NEXT: addi a7, sp, 40
330; RV32I-FPELIM-NEXT: jalr t0
331; RV32I-FPELIM-NEXT: lw ra, 60(sp)
332; RV32I-FPELIM-NEXT: addi sp, sp, 64
333; RV32I-FPELIM-NEXT: ret
334;
335; RV32I-WITHFP-LABEL: caller_large_scalars_exhausted_regs:
336; RV32I-WITHFP: # %bb.0:
337; RV32I-WITHFP-NEXT: addi sp, sp, -64
338; RV32I-WITHFP-NEXT: sw ra, 60(sp)
339; RV32I-WITHFP-NEXT: sw s0, 56(sp)
340; RV32I-WITHFP-NEXT: addi s0, sp, 64
341; RV32I-WITHFP-NEXT: addi a0, s0, -48
342; RV32I-WITHFP-NEXT: sw a0, 4(sp)
343; RV32I-WITHFP-NEXT: addi a0, zero, 9
344; RV32I-WITHFP-NEXT: sw a0, 0(sp)
345; RV32I-WITHFP-NEXT: sw zero, -40(s0)
346; RV32I-WITHFP-NEXT: sw zero, -44(s0)
347; RV32I-WITHFP-NEXT: sw zero, -48(s0)
348; RV32I-WITHFP-NEXT: sw zero, -12(s0)
349; RV32I-WITHFP-NEXT: sw zero, -16(s0)
350; RV32I-WITHFP-NEXT: sw zero, -20(s0)
351; RV32I-WITHFP-NEXT: addi a0, zero, 8
352; RV32I-WITHFP-NEXT: sw a0, -24(s0)
353; RV32I-WITHFP-NEXT: lui a0, 524272
354; RV32I-WITHFP-NEXT: mv a0, a0
355; RV32I-WITHFP-NEXT: sw a0, -36(s0)
356; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalars_exhausted_regs)
357; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_large_scalars_exhausted_regs)
358; RV32I-WITHFP-NEXT: addi a0, zero, 1
359; RV32I-WITHFP-NEXT: addi a1, zero, 2
360; RV32I-WITHFP-NEXT: addi a2, zero, 3
361; RV32I-WITHFP-NEXT: addi a3, zero, 4
362; RV32I-WITHFP-NEXT: addi a4, zero, 5
363; RV32I-WITHFP-NEXT: addi a5, zero, 6
364; RV32I-WITHFP-NEXT: addi a6, zero, 7
365; RV32I-WITHFP-NEXT: addi a7, s0, -24
366; RV32I-WITHFP-NEXT: jalr t0
367; RV32I-WITHFP-NEXT: lw s0, 56(sp)
368; RV32I-WITHFP-NEXT: lw ra, 60(sp)
369; RV32I-WITHFP-NEXT: addi sp, sp, 64
370; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]371 %1 = call i32 @callee_large_scalars_exhausted_regs(
372 i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i128 8, i32 9,
373 fp128 0xL00000000000000007FFF000000000000)
374 ret i32 %1
375}
376
377; Ensure that libcalls generated in the middle-end obey the calling convention
378
379define i32 @caller_mixed_scalar_libcalls(i64 %a) nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]380; RV32I-FPELIM-LABEL: caller_mixed_scalar_libcalls:
381; RV32I-FPELIM: # %bb.0:
382; RV32I-FPELIM-NEXT: addi sp, sp, -32
383; RV32I-FPELIM-NEXT: sw ra, 28(sp)
384; RV32I-FPELIM-NEXT: mv a2, a1
385; RV32I-FPELIM-NEXT: mv a1, a0
386; RV32I-FPELIM-NEXT: lui a0, %hi(__floatditf)
387; RV32I-FPELIM-NEXT: addi a3, a0, %lo(__floatditf)
388; RV32I-FPELIM-NEXT: addi a0, sp, 8
389; RV32I-FPELIM-NEXT: jalr a3
390; RV32I-FPELIM-NEXT: lw a0, 8(sp)
391; RV32I-FPELIM-NEXT: lw ra, 28(sp)
392; RV32I-FPELIM-NEXT: addi sp, sp, 32
393; RV32I-FPELIM-NEXT: ret
394;
395; RV32I-WITHFP-LABEL: caller_mixed_scalar_libcalls:
396; RV32I-WITHFP: # %bb.0:
397; RV32I-WITHFP-NEXT: addi sp, sp, -32
398; RV32I-WITHFP-NEXT: sw ra, 28(sp)
399; RV32I-WITHFP-NEXT: sw s0, 24(sp)
400; RV32I-WITHFP-NEXT: addi s0, sp, 32
401; RV32I-WITHFP-NEXT: mv a2, a1
402; RV32I-WITHFP-NEXT: mv a1, a0
403; RV32I-WITHFP-NEXT: lui a0, %hi(__floatditf)
404; RV32I-WITHFP-NEXT: addi a3, a0, %lo(__floatditf)
405; RV32I-WITHFP-NEXT: addi a0, s0, -24
406; RV32I-WITHFP-NEXT: jalr a3
407; RV32I-WITHFP-NEXT: lw a0, -24(s0)
408; RV32I-WITHFP-NEXT: lw s0, 24(sp)
409; RV32I-WITHFP-NEXT: lw ra, 28(sp)
410; RV32I-WITHFP-NEXT: addi sp, sp, 32
411; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]412 %1 = sitofp i64 %a to fp128
413 %2 = bitcast fp128 %1 to i128
414 %3 = trunc i128 %2 to i32
415 ret i32 %3
416}
417
418; Check that the stack is used once the GPRs are exhausted
419
420define i32 @callee_many_scalars(i8 %a, i16 %b, i32 %c, i64 %d, i32 %e, i32 %f, i64 %g, i32 %h) nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]421; RV32I-FPELIM-LABEL: callee_many_scalars:
422; RV32I-FPELIM: # %bb.0:
423; RV32I-FPELIM-NEXT: lw t0, 0(sp)
424; RV32I-FPELIM-NEXT: xor a4, a4, t0
425; RV32I-FPELIM-NEXT: xor a3, a3, a7
426; RV32I-FPELIM-NEXT: or a3, a3, a4
427; RV32I-FPELIM-NEXT: xor a3, a3, zero
428; RV32I-FPELIM-NEXT: lui a4, 16
429; RV32I-FPELIM-NEXT: addi a4, a4, -1
430; RV32I-FPELIM-NEXT: and a1, a1, a4
431; RV32I-FPELIM-NEXT: andi a0, a0, 255
432; RV32I-FPELIM-NEXT: add a0, a0, a1
433; RV32I-FPELIM-NEXT: add a0, a0, a2
434; RV32I-FPELIM-NEXT: seqz a1, a3
435; RV32I-FPELIM-NEXT: add a0, a1, a0
436; RV32I-FPELIM-NEXT: add a0, a0, a5
437; RV32I-FPELIM-NEXT: add a0, a0, a6
438; RV32I-FPELIM-NEXT: lw a1, 4(sp)
439; RV32I-FPELIM-NEXT: add a0, a0, a1
440; RV32I-FPELIM-NEXT: ret
441;
442; RV32I-WITHFP-LABEL: callee_many_scalars:
443; RV32I-WITHFP: # %bb.0:
444; RV32I-WITHFP-NEXT: addi sp, sp, -16
445; RV32I-WITHFP-NEXT: sw ra, 12(sp)
446; RV32I-WITHFP-NEXT: sw s0, 8(sp)
447; RV32I-WITHFP-NEXT: addi s0, sp, 16
448; RV32I-WITHFP-NEXT: lw t0, 0(s0)
449; RV32I-WITHFP-NEXT: xor a4, a4, t0
450; RV32I-WITHFP-NEXT: xor a3, a3, a7
451; RV32I-WITHFP-NEXT: or a3, a3, a4
452; RV32I-WITHFP-NEXT: xor a3, a3, zero
453; RV32I-WITHFP-NEXT: lui a4, 16
454; RV32I-WITHFP-NEXT: addi a4, a4, -1
455; RV32I-WITHFP-NEXT: and a1, a1, a4
456; RV32I-WITHFP-NEXT: andi a0, a0, 255
457; RV32I-WITHFP-NEXT: add a0, a0, a1
458; RV32I-WITHFP-NEXT: add a0, a0, a2
459; RV32I-WITHFP-NEXT: seqz a1, a3
460; RV32I-WITHFP-NEXT: add a0, a1, a0
461; RV32I-WITHFP-NEXT: add a0, a0, a5
462; RV32I-WITHFP-NEXT: add a0, a0, a6
463; RV32I-WITHFP-NEXT: lw a1, 4(s0)
464; RV32I-WITHFP-NEXT: add a0, a0, a1
465; RV32I-WITHFP-NEXT: lw s0, 8(sp)
466; RV32I-WITHFP-NEXT: lw ra, 12(sp)
467; RV32I-WITHFP-NEXT: addi sp, sp, 16
468; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]469 %a_ext = zext i8 %a to i32
470 %b_ext = zext i16 %b to i32
471 %1 = add i32 %a_ext, %b_ext
472 %2 = add i32 %1, %c
473 %3 = icmp eq i64 %d, %g
474 %4 = zext i1 %3 to i32
475 %5 = add i32 %4, %2
476 %6 = add i32 %5, %e
477 %7 = add i32 %6, %f
478 %8 = add i32 %7, %h
479 ret i32 %8
480}
481
482define i32 @caller_many_scalars() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]483; RV32I-FPELIM-LABEL: caller_many_scalars:
484; RV32I-FPELIM: # %bb.0:
485; RV32I-FPELIM-NEXT: addi sp, sp, -16
486; RV32I-FPELIM-NEXT: sw ra, 12(sp)
487; RV32I-FPELIM-NEXT: addi a0, zero, 8
488; RV32I-FPELIM-NEXT: sw a0, 4(sp)
489; RV32I-FPELIM-NEXT: sw zero, 0(sp)
490; RV32I-FPELIM-NEXT: lui a0, %hi(callee_many_scalars)
491; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_many_scalars)
492; RV32I-FPELIM-NEXT: addi a0, zero, 1
493; RV32I-FPELIM-NEXT: addi a1, zero, 2
494; RV32I-FPELIM-NEXT: addi a2, zero, 3
495; RV32I-FPELIM-NEXT: addi a3, zero, 4
496; RV32I-FPELIM-NEXT: addi a5, zero, 5
497; RV32I-FPELIM-NEXT: addi a6, zero, 6
498; RV32I-FPELIM-NEXT: addi a7, zero, 7
499; RV32I-FPELIM-NEXT: mv a4, zero
500; RV32I-FPELIM-NEXT: jalr t0
501; RV32I-FPELIM-NEXT: lw ra, 12(sp)
502; RV32I-FPELIM-NEXT: addi sp, sp, 16
503; RV32I-FPELIM-NEXT: ret
504;
505; RV32I-WITHFP-LABEL: caller_many_scalars:
506; RV32I-WITHFP: # %bb.0:
507; RV32I-WITHFP-NEXT: addi sp, sp, -32
508; RV32I-WITHFP-NEXT: sw ra, 28(sp)
509; RV32I-WITHFP-NEXT: sw s0, 24(sp)
510; RV32I-WITHFP-NEXT: addi s0, sp, 32
511; RV32I-WITHFP-NEXT: addi a0, zero, 8
512; RV32I-WITHFP-NEXT: sw a0, 4(sp)
513; RV32I-WITHFP-NEXT: sw zero, 0(sp)
514; RV32I-WITHFP-NEXT: lui a0, %hi(callee_many_scalars)
515; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_many_scalars)
516; RV32I-WITHFP-NEXT: addi a0, zero, 1
517; RV32I-WITHFP-NEXT: addi a1, zero, 2
518; RV32I-WITHFP-NEXT: addi a2, zero, 3
519; RV32I-WITHFP-NEXT: addi a3, zero, 4
520; RV32I-WITHFP-NEXT: addi a5, zero, 5
521; RV32I-WITHFP-NEXT: addi a6, zero, 6
522; RV32I-WITHFP-NEXT: addi a7, zero, 7
523; RV32I-WITHFP-NEXT: mv a4, zero
524; RV32I-WITHFP-NEXT: jalr t0
525; RV32I-WITHFP-NEXT: lw s0, 24(sp)
526; RV32I-WITHFP-NEXT: lw ra, 28(sp)
527; RV32I-WITHFP-NEXT: addi sp, sp, 32
528; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]529 %1 = call i32 @callee_many_scalars(i8 1, i16 2, i32 3, i64 4, i32 5, i32 6, i64 7, i32 8)
530 ret i32 %1
531}
532
533; Check passing of coerced integer arrays
534
535%struct.small = type { i32, i32* }
536
537define i32 @callee_small_coerced_struct([2 x i32] %a.coerce) nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]538; RV32I-FPELIM-LABEL: callee_small_coerced_struct:
539; RV32I-FPELIM: # %bb.0:
540; RV32I-FPELIM-NEXT: xor a0, a0, a1
541; RV32I-FPELIM-NEXT: seqz a0, a0
542; RV32I-FPELIM-NEXT: ret
543;
544; RV32I-WITHFP-LABEL: callee_small_coerced_struct:
545; RV32I-WITHFP: # %bb.0:
546; RV32I-WITHFP-NEXT: addi sp, sp, -16
547; RV32I-WITHFP-NEXT: sw ra, 12(sp)
548; RV32I-WITHFP-NEXT: sw s0, 8(sp)
549; RV32I-WITHFP-NEXT: addi s0, sp, 16
550; RV32I-WITHFP-NEXT: xor a0, a0, a1
551; RV32I-WITHFP-NEXT: seqz a0, a0
552; RV32I-WITHFP-NEXT: lw s0, 8(sp)
553; RV32I-WITHFP-NEXT: lw ra, 12(sp)
554; RV32I-WITHFP-NEXT: addi sp, sp, 16
555; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]556 %1 = extractvalue [2 x i32] %a.coerce, 0
557 %2 = extractvalue [2 x i32] %a.coerce, 1
558 %3 = icmp eq i32 %1, %2
559 %4 = zext i1 %3 to i32
560 ret i32 %4
561}
562
563define i32 @caller_small_coerced_struct() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]564; RV32I-FPELIM-LABEL: caller_small_coerced_struct:
565; RV32I-FPELIM: # %bb.0:
566; RV32I-FPELIM-NEXT: addi sp, sp, -16
567; RV32I-FPELIM-NEXT: sw ra, 12(sp)
568; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_coerced_struct)
569; RV32I-FPELIM-NEXT: addi a2, a0, %lo(callee_small_coerced_struct)
570; RV32I-FPELIM-NEXT: addi a0, zero, 1
571; RV32I-FPELIM-NEXT: addi a1, zero, 2
572; RV32I-FPELIM-NEXT: jalr a2
573; RV32I-FPELIM-NEXT: lw ra, 12(sp)
574; RV32I-FPELIM-NEXT: addi sp, sp, 16
575; RV32I-FPELIM-NEXT: ret
576;
577; RV32I-WITHFP-LABEL: caller_small_coerced_struct:
578; RV32I-WITHFP: # %bb.0:
579; RV32I-WITHFP-NEXT: addi sp, sp, -16
580; RV32I-WITHFP-NEXT: sw ra, 12(sp)
581; RV32I-WITHFP-NEXT: sw s0, 8(sp)
582; RV32I-WITHFP-NEXT: addi s0, sp, 16
583; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_coerced_struct)
584; RV32I-WITHFP-NEXT: addi a2, a0, %lo(callee_small_coerced_struct)
585; RV32I-WITHFP-NEXT: addi a0, zero, 1
586; RV32I-WITHFP-NEXT: addi a1, zero, 2
587; RV32I-WITHFP-NEXT: jalr a2
588; RV32I-WITHFP-NEXT: lw s0, 8(sp)
589; RV32I-WITHFP-NEXT: lw ra, 12(sp)
590; RV32I-WITHFP-NEXT: addi sp, sp, 16
591; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]592 %1 = call i32 @callee_small_coerced_struct([2 x i32] [i32 1, i32 2])
593 ret i32 %1
594}
595
596; Check large struct arguments, which are passed byval
597
598%struct.large = type { i32, i32, i32, i32 }
599
600define i32 @callee_large_struct(%struct.large* byval align 4 %a) nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]601; RV32I-FPELIM-LABEL: callee_large_struct:
602; RV32I-FPELIM: # %bb.0:
603; RV32I-FPELIM-NEXT: lw a1, 12(a0)
604; RV32I-FPELIM-NEXT: lw a0, 0(a0)
605; RV32I-FPELIM-NEXT: add a0, a0, a1
606; RV32I-FPELIM-NEXT: ret
607;
608; RV32I-WITHFP-LABEL: callee_large_struct:
609; RV32I-WITHFP: # %bb.0:
610; RV32I-WITHFP-NEXT: addi sp, sp, -16
611; RV32I-WITHFP-NEXT: sw ra, 12(sp)
612; RV32I-WITHFP-NEXT: sw s0, 8(sp)
613; RV32I-WITHFP-NEXT: addi s0, sp, 16
614; RV32I-WITHFP-NEXT: lw a1, 12(a0)
615; RV32I-WITHFP-NEXT: lw a0, 0(a0)
616; RV32I-WITHFP-NEXT: add a0, a0, a1
617; RV32I-WITHFP-NEXT: lw s0, 8(sp)
618; RV32I-WITHFP-NEXT: lw ra, 12(sp)
619; RV32I-WITHFP-NEXT: addi sp, sp, 16
620; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]621 %1 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 0
622 %2 = getelementptr inbounds %struct.large, %struct.large* %a, i32 0, i32 3
623 %3 = load i32, i32* %1
624 %4 = load i32, i32* %2
625 %5 = add i32 %3, %4
626 ret i32 %5
627}
628
629define i32 @caller_large_struct() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]630; RV32I-FPELIM-LABEL: caller_large_struct:
631; RV32I-FPELIM: # %bb.0:
632; RV32I-FPELIM-NEXT: addi sp, sp, -48
633; RV32I-FPELIM-NEXT: sw ra, 44(sp)
634; RV32I-FPELIM-NEXT: addi a0, zero, 1
635; RV32I-FPELIM-NEXT: sw a0, 24(sp)
636; RV32I-FPELIM-NEXT: sw a0, 8(sp)
637; RV32I-FPELIM-NEXT: addi a0, zero, 2
638; RV32I-FPELIM-NEXT: sw a0, 28(sp)
639; RV32I-FPELIM-NEXT: sw a0, 12(sp)
640; RV32I-FPELIM-NEXT: addi a0, zero, 3
641; RV32I-FPELIM-NEXT: sw a0, 32(sp)
642; RV32I-FPELIM-NEXT: sw a0, 16(sp)
643; RV32I-FPELIM-NEXT: addi a0, zero, 4
644; RV32I-FPELIM-NEXT: sw a0, 36(sp)
645; RV32I-FPELIM-NEXT: sw a0, 20(sp)
646; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct)
647; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct)
648; RV32I-FPELIM-NEXT: addi a0, sp, 8
649; RV32I-FPELIM-NEXT: jalr a1
650; RV32I-FPELIM-NEXT: lw ra, 44(sp)
651; RV32I-FPELIM-NEXT: addi sp, sp, 48
652; RV32I-FPELIM-NEXT: ret
653;
654; RV32I-WITHFP-LABEL: caller_large_struct:
655; RV32I-WITHFP: # %bb.0:
656; RV32I-WITHFP-NEXT: addi sp, sp, -48
657; RV32I-WITHFP-NEXT: sw ra, 44(sp)
658; RV32I-WITHFP-NEXT: sw s0, 40(sp)
659; RV32I-WITHFP-NEXT: addi s0, sp, 48
660; RV32I-WITHFP-NEXT: addi a0, zero, 1
661; RV32I-WITHFP-NEXT: sw a0, -24(s0)
662; RV32I-WITHFP-NEXT: sw a0, -40(s0)
663; RV32I-WITHFP-NEXT: addi a0, zero, 2
664; RV32I-WITHFP-NEXT: sw a0, -20(s0)
665; RV32I-WITHFP-NEXT: sw a0, -36(s0)
666; RV32I-WITHFP-NEXT: addi a0, zero, 3
667; RV32I-WITHFP-NEXT: sw a0, -16(s0)
668; RV32I-WITHFP-NEXT: sw a0, -32(s0)
669; RV32I-WITHFP-NEXT: addi a0, zero, 4
670; RV32I-WITHFP-NEXT: sw a0, -12(s0)
671; RV32I-WITHFP-NEXT: sw a0, -28(s0)
672; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct)
673; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct)
674; RV32I-WITHFP-NEXT: addi a0, s0, -40
675; RV32I-WITHFP-NEXT: jalr a1
676; RV32I-WITHFP-NEXT: lw s0, 40(sp)
677; RV32I-WITHFP-NEXT: lw ra, 44(sp)
678; RV32I-WITHFP-NEXT: addi sp, sp, 48
679; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]680 %ls = alloca %struct.large, align 4
681 %1 = bitcast %struct.large* %ls to i8*
682 %a = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 0
683 store i32 1, i32* %a
684 %b = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 1
685 store i32 2, i32* %b
686 %c = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 2
687 store i32 3, i32* %c
688 %d = getelementptr inbounds %struct.large, %struct.large* %ls, i32 0, i32 3
689 store i32 4, i32* %d
690 %2 = call i32 @callee_large_struct(%struct.large* byval align 4 %ls)
691 ret i32 %2
692}
693
694; Check 2x*xlen values are aligned appropriately when passed on the stack
695; Must keep define on a single line due to an update_llc_test_checks.py limitation
696define i32 @callee_aligned_stack(i32 %a, i32 %b, fp128 %c, i32 %d, i32 %e, i64 %f, i32 %g, i32 %h, double %i, i32 %j, [2 x i32] %k) nounwind {
697; The double should be 8-byte aligned on the stack, but the two-element array
698; should only be 4-byte aligned
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]699; RV32I-FPELIM-LABEL: callee_aligned_stack:
700; RV32I-FPELIM: # %bb.0:
701; RV32I-FPELIM-NEXT: lw a0, 0(a2)
702; RV32I-FPELIM-NEXT: add a0, a0, a7
703; RV32I-FPELIM-NEXT: lw a1, 0(sp)
704; RV32I-FPELIM-NEXT: add a0, a0, a1
705; RV32I-FPELIM-NEXT: lw a1, 8(sp)
706; RV32I-FPELIM-NEXT: add a0, a0, a1
707; RV32I-FPELIM-NEXT: lw a1, 16(sp)
708; RV32I-FPELIM-NEXT: add a0, a0, a1
709; RV32I-FPELIM-NEXT: lw a1, 20(sp)
710; RV32I-FPELIM-NEXT: add a0, a0, a1
711; RV32I-FPELIM-NEXT: ret
712;
713; RV32I-WITHFP-LABEL: callee_aligned_stack:
714; RV32I-WITHFP: # %bb.0:
715; RV32I-WITHFP-NEXT: addi sp, sp, -16
716; RV32I-WITHFP-NEXT: sw ra, 12(sp)
717; RV32I-WITHFP-NEXT: sw s0, 8(sp)
718; RV32I-WITHFP-NEXT: addi s0, sp, 16
719; RV32I-WITHFP-NEXT: lw a0, 0(a2)
720; RV32I-WITHFP-NEXT: add a0, a0, a7
721; RV32I-WITHFP-NEXT: lw a1, 0(s0)
722; RV32I-WITHFP-NEXT: add a0, a0, a1
723; RV32I-WITHFP-NEXT: lw a1, 8(s0)
724; RV32I-WITHFP-NEXT: add a0, a0, a1
725; RV32I-WITHFP-NEXT: lw a1, 16(s0)
726; RV32I-WITHFP-NEXT: add a0, a0, a1
727; RV32I-WITHFP-NEXT: lw a1, 20(s0)
728; RV32I-WITHFP-NEXT: add a0, a0, a1
729; RV32I-WITHFP-NEXT: lw s0, 8(sp)
730; RV32I-WITHFP-NEXT: lw ra, 12(sp)
731; RV32I-WITHFP-NEXT: addi sp, sp, 16
732; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]733 %1 = bitcast fp128 %c to i128
734 %2 = trunc i128 %1 to i32
735 %3 = add i32 %2, %g
736 %4 = add i32 %3, %h
737 %5 = bitcast double %i to i64
738 %6 = trunc i64 %5 to i32
739 %7 = add i32 %4, %6
740 %8 = add i32 %7, %j
741 %9 = extractvalue [2 x i32] %k, 0
742 %10 = add i32 %8, %9
743 ret i32 %10
744}
745
746define void @caller_aligned_stack() nounwind {
747; The double should be 8-byte aligned on the stack, but the two-element array
748; should only be 4-byte aligned
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]749; RV32I-FPELIM-LABEL: caller_aligned_stack:
750; RV32I-FPELIM: # %bb.0:
751; RV32I-FPELIM-NEXT: addi sp, sp, -64
752; RV32I-FPELIM-NEXT: sw ra, 60(sp)
753; RV32I-FPELIM-NEXT: addi a0, zero, 18
754; RV32I-FPELIM-NEXT: sw a0, 24(sp)
755; RV32I-FPELIM-NEXT: addi a0, zero, 17
756; RV32I-FPELIM-NEXT: sw a0, 20(sp)
757; RV32I-FPELIM-NEXT: addi a0, zero, 16
758; RV32I-FPELIM-NEXT: sw a0, 16(sp)
759; RV32I-FPELIM-NEXT: lui a0, 262236
760; RV32I-FPELIM-NEXT: addi a0, a0, 655
761; RV32I-FPELIM-NEXT: sw a0, 12(sp)
762; RV32I-FPELIM-NEXT: lui a0, 377487
763; RV32I-FPELIM-NEXT: addi a0, a0, 1475
764; RV32I-FPELIM-NEXT: sw a0, 8(sp)
765; RV32I-FPELIM-NEXT: addi a0, zero, 15
766; RV32I-FPELIM-NEXT: sw a0, 0(sp)
767; RV32I-FPELIM-NEXT: lui a0, 262153
768; RV32I-FPELIM-NEXT: addi a0, a0, 491
769; RV32I-FPELIM-NEXT: sw a0, 44(sp)
770; RV32I-FPELIM-NEXT: lui a0, 545260
771; RV32I-FPELIM-NEXT: addi a0, a0, -1967
772; RV32I-FPELIM-NEXT: sw a0, 40(sp)
773; RV32I-FPELIM-NEXT: lui a0, 964690
774; RV32I-FPELIM-NEXT: addi a0, a0, -328
775; RV32I-FPELIM-NEXT: sw a0, 36(sp)
776; RV32I-FPELIM-NEXT: lui a0, 335544
777; RV32I-FPELIM-NEXT: addi a0, a0, 1311
778; RV32I-FPELIM-NEXT: sw a0, 32(sp)
779; RV32I-FPELIM-NEXT: lui a0, 688509
780; RV32I-FPELIM-NEXT: addi a5, a0, -2048
781; RV32I-FPELIM-NEXT: lui a0, %hi(callee_aligned_stack)
782; RV32I-FPELIM-NEXT: addi t0, a0, %lo(callee_aligned_stack)
783; RV32I-FPELIM-NEXT: addi a0, zero, 1
784; RV32I-FPELIM-NEXT: addi a1, zero, 11
785; RV32I-FPELIM-NEXT: addi a2, sp, 32
786; RV32I-FPELIM-NEXT: addi a3, zero, 12
787; RV32I-FPELIM-NEXT: addi a4, zero, 13
788; RV32I-FPELIM-NEXT: addi a6, zero, 4
789; RV32I-FPELIM-NEXT: addi a7, zero, 14
790; RV32I-FPELIM-NEXT: jalr t0
791; RV32I-FPELIM-NEXT: lw ra, 60(sp)
792; RV32I-FPELIM-NEXT: addi sp, sp, 64
793; RV32I-FPELIM-NEXT: ret
794;
795; RV32I-WITHFP-LABEL: caller_aligned_stack:
796; RV32I-WITHFP: # %bb.0:
797; RV32I-WITHFP-NEXT: addi sp, sp, -64
798; RV32I-WITHFP-NEXT: sw ra, 60(sp)
799; RV32I-WITHFP-NEXT: sw s0, 56(sp)
800; RV32I-WITHFP-NEXT: addi s0, sp, 64
801; RV32I-WITHFP-NEXT: addi a0, zero, 18
802; RV32I-WITHFP-NEXT: sw a0, 24(sp)
803; RV32I-WITHFP-NEXT: addi a0, zero, 17
804; RV32I-WITHFP-NEXT: sw a0, 20(sp)
805; RV32I-WITHFP-NEXT: addi a0, zero, 16
806; RV32I-WITHFP-NEXT: sw a0, 16(sp)
807; RV32I-WITHFP-NEXT: lui a0, 262236
808; RV32I-WITHFP-NEXT: addi a0, a0, 655
809; RV32I-WITHFP-NEXT: sw a0, 12(sp)
810; RV32I-WITHFP-NEXT: lui a0, 377487
811; RV32I-WITHFP-NEXT: addi a0, a0, 1475
812; RV32I-WITHFP-NEXT: sw a0, 8(sp)
813; RV32I-WITHFP-NEXT: addi a0, zero, 15
814; RV32I-WITHFP-NEXT: sw a0, 0(sp)
815; RV32I-WITHFP-NEXT: lui a0, 262153
816; RV32I-WITHFP-NEXT: addi a0, a0, 491
817; RV32I-WITHFP-NEXT: sw a0, -20(s0)
818; RV32I-WITHFP-NEXT: lui a0, 545260
819; RV32I-WITHFP-NEXT: addi a0, a0, -1967
820; RV32I-WITHFP-NEXT: sw a0, -24(s0)
821; RV32I-WITHFP-NEXT: lui a0, 964690
822; RV32I-WITHFP-NEXT: addi a0, a0, -328
823; RV32I-WITHFP-NEXT: sw a0, -28(s0)
824; RV32I-WITHFP-NEXT: lui a0, 335544
825; RV32I-WITHFP-NEXT: addi a0, a0, 1311
826; RV32I-WITHFP-NEXT: sw a0, -32(s0)
827; RV32I-WITHFP-NEXT: lui a0, 688509
828; RV32I-WITHFP-NEXT: addi a5, a0, -2048
829; RV32I-WITHFP-NEXT: lui a0, %hi(callee_aligned_stack)
830; RV32I-WITHFP-NEXT: addi t0, a0, %lo(callee_aligned_stack)
831; RV32I-WITHFP-NEXT: addi a0, zero, 1
832; RV32I-WITHFP-NEXT: addi a1, zero, 11
833; RV32I-WITHFP-NEXT: addi a2, s0, -32
834; RV32I-WITHFP-NEXT: addi a3, zero, 12
835; RV32I-WITHFP-NEXT: addi a4, zero, 13
836; RV32I-WITHFP-NEXT: addi a6, zero, 4
837; RV32I-WITHFP-NEXT: addi a7, zero, 14
838; RV32I-WITHFP-NEXT: jalr t0
839; RV32I-WITHFP-NEXT: lw s0, 56(sp)
840; RV32I-WITHFP-NEXT: lw ra, 60(sp)
841; RV32I-WITHFP-NEXT: addi sp, sp, 64
842; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]843 %1 = call i32 @callee_aligned_stack(i32 1, i32 11,
844 fp128 0xLEB851EB851EB851F400091EB851EB851, i32 12, i32 13,
845 i64 20000000000, i32 14, i32 15, double 2.720000e+00, i32 16,
846 [2 x i32] [i32 17, i32 18])
847 ret void
848}
849
850; Check return of 2x xlen scalars
851
852define i64 @callee_small_scalar_ret() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]853; RV32I-FPELIM-LABEL: callee_small_scalar_ret:
854; RV32I-FPELIM: # %bb.0:
855; RV32I-FPELIM-NEXT: lui a0, 466866
856; RV32I-FPELIM-NEXT: addi a0, a0, 1677
857; RV32I-FPELIM-NEXT: addi a1, zero, 287
858; RV32I-FPELIM-NEXT: ret
859;
860; RV32I-WITHFP-LABEL: callee_small_scalar_ret:
861; RV32I-WITHFP: # %bb.0:
862; RV32I-WITHFP-NEXT: addi sp, sp, -16
863; RV32I-WITHFP-NEXT: sw ra, 12(sp)
864; RV32I-WITHFP-NEXT: sw s0, 8(sp)
865; RV32I-WITHFP-NEXT: addi s0, sp, 16
866; RV32I-WITHFP-NEXT: lui a0, 466866
867; RV32I-WITHFP-NEXT: addi a0, a0, 1677
868; RV32I-WITHFP-NEXT: addi a1, zero, 287
869; RV32I-WITHFP-NEXT: lw s0, 8(sp)
870; RV32I-WITHFP-NEXT: lw ra, 12(sp)
871; RV32I-WITHFP-NEXT: addi sp, sp, 16
872; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]873 ret i64 1234567898765
874}
875
876define i32 @caller_small_scalar_ret() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]877; RV32I-FPELIM-LABEL: caller_small_scalar_ret:
878; RV32I-FPELIM: # %bb.0:
879; RV32I-FPELIM-NEXT: addi sp, sp, -16
880; RV32I-FPELIM-NEXT: sw ra, 12(sp)
881; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_scalar_ret)
882; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_scalar_ret)
883; RV32I-FPELIM-NEXT: jalr a0
884; RV32I-FPELIM-NEXT: lui a2, 56
885; RV32I-FPELIM-NEXT: addi a2, a2, 580
886; RV32I-FPELIM-NEXT: xor a1, a1, a2
887; RV32I-FPELIM-NEXT: lui a2, 200614
888; RV32I-FPELIM-NEXT: addi a2, a2, 647
889; RV32I-FPELIM-NEXT: xor a0, a0, a2
890; RV32I-FPELIM-NEXT: or a0, a0, a1
891; RV32I-FPELIM-NEXT: xor a0, a0, zero
892; RV32I-FPELIM-NEXT: seqz a0, a0
893; RV32I-FPELIM-NEXT: lw ra, 12(sp)
894; RV32I-FPELIM-NEXT: addi sp, sp, 16
895; RV32I-FPELIM-NEXT: ret
896;
897; RV32I-WITHFP-LABEL: caller_small_scalar_ret:
898; RV32I-WITHFP: # %bb.0:
899; RV32I-WITHFP-NEXT: addi sp, sp, -16
900; RV32I-WITHFP-NEXT: sw ra, 12(sp)
901; RV32I-WITHFP-NEXT: sw s0, 8(sp)
902; RV32I-WITHFP-NEXT: addi s0, sp, 16
903; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_scalar_ret)
904; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_scalar_ret)
905; RV32I-WITHFP-NEXT: jalr a0
906; RV32I-WITHFP-NEXT: lui a2, 56
907; RV32I-WITHFP-NEXT: addi a2, a2, 580
908; RV32I-WITHFP-NEXT: xor a1, a1, a2
909; RV32I-WITHFP-NEXT: lui a2, 200614
910; RV32I-WITHFP-NEXT: addi a2, a2, 647
911; RV32I-WITHFP-NEXT: xor a0, a0, a2
912; RV32I-WITHFP-NEXT: or a0, a0, a1
913; RV32I-WITHFP-NEXT: xor a0, a0, zero
914; RV32I-WITHFP-NEXT: seqz a0, a0
915; RV32I-WITHFP-NEXT: lw s0, 8(sp)
916; RV32I-WITHFP-NEXT: lw ra, 12(sp)
917; RV32I-WITHFP-NEXT: addi sp, sp, 16
918; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]919 %1 = call i64 @callee_small_scalar_ret()
920 %2 = icmp eq i64 987654321234567, %1
921 %3 = zext i1 %2 to i32
922 ret i32 %3
923}
924
925; Check return of 2x xlen structs
926
927define %struct.small @callee_small_struct_ret() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]928; RV32I-FPELIM-LABEL: callee_small_struct_ret:
929; RV32I-FPELIM: # %bb.0:
930; RV32I-FPELIM-NEXT: addi a0, zero, 1
931; RV32I-FPELIM-NEXT: mv a1, zero
932; RV32I-FPELIM-NEXT: ret
933;
934; RV32I-WITHFP-LABEL: callee_small_struct_ret:
935; RV32I-WITHFP: # %bb.0:
936; RV32I-WITHFP-NEXT: addi sp, sp, -16
937; RV32I-WITHFP-NEXT: sw ra, 12(sp)
938; RV32I-WITHFP-NEXT: sw s0, 8(sp)
939; RV32I-WITHFP-NEXT: addi s0, sp, 16
940; RV32I-WITHFP-NEXT: addi a0, zero, 1
941; RV32I-WITHFP-NEXT: mv a1, zero
942; RV32I-WITHFP-NEXT: lw s0, 8(sp)
943; RV32I-WITHFP-NEXT: lw ra, 12(sp)
944; RV32I-WITHFP-NEXT: addi sp, sp, 16
945; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]946 ret %struct.small { i32 1, i32* null }
947}
948
949define i32 @caller_small_struct_ret() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]950; RV32I-FPELIM-LABEL: caller_small_struct_ret:
951; RV32I-FPELIM: # %bb.0:
952; RV32I-FPELIM-NEXT: addi sp, sp, -16
953; RV32I-FPELIM-NEXT: sw ra, 12(sp)
954; RV32I-FPELIM-NEXT: lui a0, %hi(callee_small_struct_ret)
955; RV32I-FPELIM-NEXT: addi a0, a0, %lo(callee_small_struct_ret)
956; RV32I-FPELIM-NEXT: jalr a0
957; RV32I-FPELIM-NEXT: add a0, a0, a1
958; RV32I-FPELIM-NEXT: lw ra, 12(sp)
959; RV32I-FPELIM-NEXT: addi sp, sp, 16
960; RV32I-FPELIM-NEXT: ret
961;
962; RV32I-WITHFP-LABEL: caller_small_struct_ret:
963; RV32I-WITHFP: # %bb.0:
964; RV32I-WITHFP-NEXT: addi sp, sp, -16
965; RV32I-WITHFP-NEXT: sw ra, 12(sp)
966; RV32I-WITHFP-NEXT: sw s0, 8(sp)
967; RV32I-WITHFP-NEXT: addi s0, sp, 16
968; RV32I-WITHFP-NEXT: lui a0, %hi(callee_small_struct_ret)
969; RV32I-WITHFP-NEXT: addi a0, a0, %lo(callee_small_struct_ret)
970; RV32I-WITHFP-NEXT: jalr a0
971; RV32I-WITHFP-NEXT: add a0, a0, a1
972; RV32I-WITHFP-NEXT: lw s0, 8(sp)
973; RV32I-WITHFP-NEXT: lw ra, 12(sp)
974; RV32I-WITHFP-NEXT: addi sp, sp, 16
975; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]976 %1 = call %struct.small @callee_small_struct_ret()
977 %2 = extractvalue %struct.small %1, 0
978 %3 = extractvalue %struct.small %1, 1
979 %4 = ptrtoint i32* %3 to i32
980 %5 = add i32 %2, %4
981 ret i32 %5
982}
983
984; Check return of >2x xlen scalars
985
986define fp128 @callee_large_scalar_ret() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]987; RV32I-FPELIM-LABEL: callee_large_scalar_ret:
988; RV32I-FPELIM: # %bb.0:
989; RV32I-FPELIM-NEXT: lui a1, 524272
990; RV32I-FPELIM-NEXT: mv a1, a1
991; RV32I-FPELIM-NEXT: sw a1, 12(a0)
992; RV32I-FPELIM-NEXT: sw zero, 8(a0)
993; RV32I-FPELIM-NEXT: sw zero, 4(a0)
994; RV32I-FPELIM-NEXT: sw zero, 0(a0)
995; RV32I-FPELIM-NEXT: ret
996;
997; RV32I-WITHFP-LABEL: callee_large_scalar_ret:
998; RV32I-WITHFP: # %bb.0:
999; RV32I-WITHFP-NEXT: addi sp, sp, -16
1000; RV32I-WITHFP-NEXT: sw ra, 12(sp)
1001; RV32I-WITHFP-NEXT: sw s0, 8(sp)
1002; RV32I-WITHFP-NEXT: addi s0, sp, 16
1003; RV32I-WITHFP-NEXT: lui a1, 524272
1004; RV32I-WITHFP-NEXT: mv a1, a1
1005; RV32I-WITHFP-NEXT: sw a1, 12(a0)
1006; RV32I-WITHFP-NEXT: sw zero, 8(a0)
1007; RV32I-WITHFP-NEXT: sw zero, 4(a0)
1008; RV32I-WITHFP-NEXT: sw zero, 0(a0)
1009; RV32I-WITHFP-NEXT: lw s0, 8(sp)
1010; RV32I-WITHFP-NEXT: lw ra, 12(sp)
1011; RV32I-WITHFP-NEXT: addi sp, sp, 16
1012; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]1013 ret fp128 0xL00000000000000007FFF000000000000
1014}
1015
1016define void @caller_large_scalar_ret() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1017; RV32I-FPELIM-LABEL: caller_large_scalar_ret:
1018; RV32I-FPELIM: # %bb.0:
1019; RV32I-FPELIM-NEXT: addi sp, sp, -32
1020; RV32I-FPELIM-NEXT: sw ra, 28(sp)
1021; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_scalar_ret)
1022; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_scalar_ret)
1023; RV32I-FPELIM-NEXT: mv a0, sp
1024; RV32I-FPELIM-NEXT: jalr a1
1025; RV32I-FPELIM-NEXT: lw ra, 28(sp)
1026; RV32I-FPELIM-NEXT: addi sp, sp, 32
1027; RV32I-FPELIM-NEXT: ret
1028;
1029; RV32I-WITHFP-LABEL: caller_large_scalar_ret:
1030; RV32I-WITHFP: # %bb.0:
1031; RV32I-WITHFP-NEXT: addi sp, sp, -32
1032; RV32I-WITHFP-NEXT: sw ra, 28(sp)
1033; RV32I-WITHFP-NEXT: sw s0, 24(sp)
1034; RV32I-WITHFP-NEXT: addi s0, sp, 32
1035; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_scalar_ret)
1036; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_scalar_ret)
1037; RV32I-WITHFP-NEXT: addi a0, s0, -32
1038; RV32I-WITHFP-NEXT: jalr a1
1039; RV32I-WITHFP-NEXT: lw s0, 24(sp)
1040; RV32I-WITHFP-NEXT: lw ra, 28(sp)
1041; RV32I-WITHFP-NEXT: addi sp, sp, 32
1042; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]1043 %1 = call fp128 @callee_large_scalar_ret()
1044 ret void
1045}
1046
1047; Check return of >2x xlen structs
1048
1049define void @callee_large_struct_ret(%struct.large* noalias sret %agg.result) nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1050; RV32I-FPELIM-LABEL: callee_large_struct_ret:
1051; RV32I-FPELIM: # %bb.0:
1052; RV32I-FPELIM-NEXT: addi a1, zero, 2
1053; RV32I-FPELIM-NEXT: sw a1, 4(a0)
1054; RV32I-FPELIM-NEXT: addi a1, zero, 1
1055; RV32I-FPELIM-NEXT: sw a1, 0(a0)
1056; RV32I-FPELIM-NEXT: addi a1, zero, 3
1057; RV32I-FPELIM-NEXT: sw a1, 8(a0)
1058; RV32I-FPELIM-NEXT: addi a1, zero, 4
1059; RV32I-FPELIM-NEXT: sw a1, 12(a0)
1060; RV32I-FPELIM-NEXT: ret
1061;
1062; RV32I-WITHFP-LABEL: callee_large_struct_ret:
1063; RV32I-WITHFP: # %bb.0:
1064; RV32I-WITHFP-NEXT: addi sp, sp, -16
1065; RV32I-WITHFP-NEXT: sw ra, 12(sp)
1066; RV32I-WITHFP-NEXT: sw s0, 8(sp)
1067; RV32I-WITHFP-NEXT: addi s0, sp, 16
1068; RV32I-WITHFP-NEXT: addi a1, zero, 2
1069; RV32I-WITHFP-NEXT: sw a1, 4(a0)
1070; RV32I-WITHFP-NEXT: addi a1, zero, 1
1071; RV32I-WITHFP-NEXT: sw a1, 0(a0)
1072; RV32I-WITHFP-NEXT: addi a1, zero, 3
1073; RV32I-WITHFP-NEXT: sw a1, 8(a0)
1074; RV32I-WITHFP-NEXT: addi a1, zero, 4
1075; RV32I-WITHFP-NEXT: sw a1, 12(a0)
1076; RV32I-WITHFP-NEXT: lw s0, 8(sp)
1077; RV32I-WITHFP-NEXT: lw ra, 12(sp)
1078; RV32I-WITHFP-NEXT: addi sp, sp, 16
1079; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]1080 %a = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 0
1081 store i32 1, i32* %a, align 4
1082 %b = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 1
1083 store i32 2, i32* %b, align 4
1084 %c = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 2
1085 store i32 3, i32* %c, align 4
1086 %d = getelementptr inbounds %struct.large, %struct.large* %agg.result, i32 0, i32 3
1087 store i32 4, i32* %d, align 4
1088 ret void
1089}
1090
1091define i32 @caller_large_struct_ret() nounwind {
Alex Bradbury7d6aa1f2018-01-18 11:34:02 +0000[diff] [blame]1092; RV32I-FPELIM-LABEL: caller_large_struct_ret:
1093; RV32I-FPELIM: # %bb.0:
1094; RV32I-FPELIM-NEXT: addi sp, sp, -32
1095; RV32I-FPELIM-NEXT: sw ra, 28(sp)
1096; RV32I-FPELIM-NEXT: lui a0, %hi(callee_large_struct_ret)
1097; RV32I-FPELIM-NEXT: addi a1, a0, %lo(callee_large_struct_ret)
1098; RV32I-FPELIM-NEXT: addi a0, sp, 8
1099; RV32I-FPELIM-NEXT: jalr a1
1100; RV32I-FPELIM-NEXT: lw a0, 20(sp)
1101; RV32I-FPELIM-NEXT: lw a1, 8(sp)
1102; RV32I-FPELIM-NEXT: add a0, a1, a0
1103; RV32I-FPELIM-NEXT: lw ra, 28(sp)
1104; RV32I-FPELIM-NEXT: addi sp, sp, 32
1105; RV32I-FPELIM-NEXT: ret
1106;
1107; RV32I-WITHFP-LABEL: caller_large_struct_ret:
1108; RV32I-WITHFP: # %bb.0:
1109; RV32I-WITHFP-NEXT: addi sp, sp, -32
1110; RV32I-WITHFP-NEXT: sw ra, 28(sp)
1111; RV32I-WITHFP-NEXT: sw s0, 24(sp)
1112; RV32I-WITHFP-NEXT: addi s0, sp, 32
1113; RV32I-WITHFP-NEXT: lui a0, %hi(callee_large_struct_ret)
1114; RV32I-WITHFP-NEXT: addi a1, a0, %lo(callee_large_struct_ret)
1115; RV32I-WITHFP-NEXT: addi a0, s0, -24
1116; RV32I-WITHFP-NEXT: jalr a1
1117; RV32I-WITHFP-NEXT: lw a0, -12(s0)
1118; RV32I-WITHFP-NEXT: lw a1, -24(s0)
1119; RV32I-WITHFP-NEXT: add a0, a1, a0
1120; RV32I-WITHFP-NEXT: lw s0, 24(sp)
1121; RV32I-WITHFP-NEXT: lw ra, 28(sp)
1122; RV32I-WITHFP-NEXT: addi sp, sp, 32
1123; RV32I-WITHFP-NEXT: ret
Alex Bradburydc31c612017-12-11 12:49:02 +0000[diff] [blame]1124 %1 = alloca %struct.large
1125 call void @callee_large_struct_ret(%struct.large* sret %1)
1126 %2 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 0
1127 %3 = load i32, i32* %2
1128 %4 = getelementptr inbounds %struct.large, %struct.large* %1, i32 0, i32 3
1129 %5 = load i32, i32* %4
1130 %6 = add i32 %3, %5
1131 ret i32 %6
1132}