| NAKAMURA Takumi | 0ff86ac | 2012-11-16 16:07:37 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -tailcallopt -code-model=medium -stack-alignment=8 -mtriple=x86_64-linux-gnu -mcpu=opteron | FileCheck %s |
| Duncan Sands | d71b4e4 | 2012-11-16 12:36:39 +0000 | [diff] [blame] | 2 | |
| 3 | ; Check the HiPE calling convention works (x86-64) |
| 4 | |
| 5 | define void @zap(i64 %a, i64 %b) nounwind { |
| 6 | entry: |
| 7 | ; CHECK: movq %rsi, %rax |
| Andrew Trick | 121124a | 2013-06-25 02:48:58 +0000 | [diff] [blame] | 8 | ; CHECK-NEXT: movl $8, %ecx |
| 9 | ; CHECK-NEXT: movl $9, %r8d |
| Andrew Trick | e97d8d6 | 2013-10-15 23:33:07 +0000 | [diff] [blame] | 10 | ; CHECK-NEXT: movq %rdi, %rsi |
| 11 | ; CHECK-NEXT: movq %rax, %rdx |
| Duncan Sands | d71b4e4 | 2012-11-16 12:36:39 +0000 | [diff] [blame] | 12 | ; CHECK-NEXT: callq addfour |
| 13 | %0 = call cc 11 {i64, i64, i64} @addfour(i64 undef, i64 undef, i64 %a, i64 %b, i64 8, i64 9) |
| 14 | %res = extractvalue {i64, i64, i64} %0, 2 |
| 15 | |
| 16 | ; CHECK: movl $1, %edx |
| 17 | ; CHECK-NEXT: movl $2, %ecx |
| 18 | ; CHECK-NEXT: movl $3, %r8d |
| 19 | ; CHECK-NEXT: movq %rax, %r9 |
| 20 | ; CHECK: callq foo |
| 21 | tail call void @foo(i64 undef, i64 undef, i64 1, i64 2, i64 3, i64 %res) nounwind |
| 22 | ret void |
| 23 | } |
| 24 | |
| 25 | define cc 11 {i64, i64, i64} @addfour(i64 %hp, i64 %p, i64 %x, i64 %y, i64 %z, i64 %w) nounwind { |
| 26 | entry: |
| 27 | ; CHECK: leaq (%rsi,%rdx), %rax |
| 28 | ; CHECK-NEXT: addq %rcx, %rax |
| 29 | ; CHECK-NEXT: addq %r8, %rax |
| 30 | %0 = add i64 %x, %y |
| 31 | %1 = add i64 %0, %z |
| 32 | %2 = add i64 %1, %w |
| 33 | |
| 34 | ; CHECK: ret |
| 35 | %res = insertvalue {i64, i64, i64} undef, i64 %2, 2 |
| 36 | ret {i64, i64, i64} %res |
| 37 | } |
| 38 | |
| 39 | define cc 11 void @foo(i64 %hp, i64 %p, i64 %arg0, i64 %arg1, i64 %arg2, i64 %arg3) nounwind { |
| 40 | entry: |
| 41 | ; CHECK: movq %r15, 40(%rsp) |
| 42 | ; CHECK-NEXT: movq %rbp, 32(%rsp) |
| 43 | ; CHECK-NEXT: movq %rsi, 24(%rsp) |
| 44 | ; CHECK-NEXT: movq %rdx, 16(%rsp) |
| 45 | ; CHECK-NEXT: movq %rcx, 8(%rsp) |
| 46 | ; CHECK-NEXT: movq %r8, (%rsp) |
| 47 | %hp_var = alloca i64 |
| 48 | %p_var = alloca i64 |
| 49 | %arg0_var = alloca i64 |
| 50 | %arg1_var = alloca i64 |
| 51 | %arg2_var = alloca i64 |
| 52 | %arg3_var = alloca i64 |
| 53 | store i64 %hp, i64* %hp_var |
| 54 | store i64 %p, i64* %p_var |
| 55 | store i64 %arg0, i64* %arg0_var |
| 56 | store i64 %arg1, i64* %arg1_var |
| 57 | store i64 %arg2, i64* %arg2_var |
| 58 | store i64 %arg3, i64* %arg3_var |
| 59 | |
| Andrew Trick | e97d8d6 | 2013-10-15 23:33:07 +0000 | [diff] [blame] | 60 | ; CHECK: movq 40(%rsp), %r15 |
| Andrew Trick | 121124a | 2013-06-25 02:48:58 +0000 | [diff] [blame] | 61 | ; CHECK-NEXT: movq 32(%rsp), %rbp |
| Andrew Trick | e97d8d6 | 2013-10-15 23:33:07 +0000 | [diff] [blame] | 62 | ; CHECK-NEXT: movq 24(%rsp), %rsi |
| 63 | ; CHECK-NEXT: movq 16(%rsp), %rdx |
| 64 | ; CHECK-NEXT: movq 8(%rsp), %rcx |
| Duncan Sands | d71b4e4 | 2012-11-16 12:36:39 +0000 | [diff] [blame] | 65 | %0 = load i64* %hp_var |
| 66 | %1 = load i64* %p_var |
| 67 | %2 = load i64* %arg0_var |
| 68 | %3 = load i64* %arg1_var |
| 69 | %4 = load i64* %arg2_var |
| 70 | %5 = load i64* %arg3_var |
| 71 | ; CHECK: jmp bar |
| 72 | tail call cc 11 void @bar(i64 %0, i64 %1, i64 %2, i64 %3, i64 %4, i64 %5) nounwind |
| 73 | ret void |
| 74 | } |
| 75 | |
| 76 | define cc 11 void @baz() nounwind { |
| 77 | %tmp_clos = load i64* @clos |
| 78 | %tmp_clos2 = inttoptr i64 %tmp_clos to i64* |
| 79 | %indirect_call = bitcast i64* %tmp_clos2 to void (i64, i64, i64)* |
| 80 | ; CHECK: movl $42, %esi |
| 81 | ; CHECK-NEXT: jmpq *(%rax) |
| 82 | tail call cc 11 void %indirect_call(i64 undef, i64 undef, i64 42) nounwind |
| 83 | ret void |
| 84 | } |
| 85 | |
| 86 | @clos = external constant i64 |
| 87 | declare cc 11 void @bar(i64, i64, i64, i64, i64, i64) |