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gerrit-public.fairphone.software / toolchain / llvm-project / c7e55d4f5213d27456c8a2f74ee5284181067d73 / . / llvm / test / CodeGen / Thumb2 / mve-pred-build-var.ll
blob: b8b518c471e922ccc57757ee81a66bb634926c2c [file] [log] [blame]
David Greenc7e55d42019-07-24 11:51:36 +0000[diff] [blame^]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=thumbv8.1m.main-arm-none-eabi -mattr=+mve -verify-machineinstrs %s -o - | FileCheck %s
3
4
5define arm_aapcs_vfpcc <4 x i32> @build_var0_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
6; CHECK-LABEL: build_var0_v4i1:
7; CHECK: @ %bb.0: @ %entry
8; CHECK-NEXT: cmp r0, r1
9; CHECK-NEXT: mov.w r0, #0
10; CHECK-NEXT: it lo
11; CHECK-NEXT: movlo r0, #1
12; CHECK-NEXT: movs r2, #0
13; CHECK-NEXT: rsbs r0, r0, #0
14; CHECK-NEXT: bfi r2, r0, #0, #4
15; CHECK-NEXT: vmsr p0, r2
16; CHECK-NEXT: vpsel q0, q0, q1
17; CHECK-NEXT: bx lr
18entry:
19 %c = icmp ult i32 %s, %t
20 %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 0
21 %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
22 ret <4 x i32> %r
23}
24
25define arm_aapcs_vfpcc <4 x i32> @build_var3_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
26; CHECK-LABEL: build_var3_v4i1:
27; CHECK: @ %bb.0: @ %entry
28; CHECK-NEXT: cmp r0, r1
29; CHECK-NEXT: mov.w r0, #0
30; CHECK-NEXT: it lo
31; CHECK-NEXT: movlo r0, #1
32; CHECK-NEXT: movs r2, #0
33; CHECK-NEXT: rsbs r0, r0, #0
34; CHECK-NEXT: bfi r2, r0, #12, #4
35; CHECK-NEXT: vmsr p0, r2
36; CHECK-NEXT: vpsel q0, q0, q1
37; CHECK-NEXT: bx lr
38entry:
39 %c = icmp ult i32 %s, %t
40 %vc = insertelement <4 x i1> zeroinitializer, i1 %c, i64 3
41 %r = select <4 x i1> %vc, <4 x i32> %a, <4 x i32> %b
42 ret <4 x i32> %r
43}
44
45define arm_aapcs_vfpcc <4 x i32> @build_varN_v4i1(i32 %s, i32 %t, <4 x i32> %a, <4 x i32> %b) {
46; CHECK-LABEL: build_varN_v4i1:
47; CHECK: @ %bb.0: @ %entry
48; CHECK-NEXT: cmp r0, r1
49; CHECK-NEXT: mov.w r0, #0
50; CHECK-NEXT: it lo
51; CHECK-NEXT: movlo r0, #1
52; CHECK-NEXT: movs r2, #0
53; CHECK-NEXT: rsbs r0, r0, #0
54; CHECK-NEXT: bfi r2, r0, #0, #4
55; CHECK-NEXT: bfi r2, r0, #4, #4
56; CHECK-NEXT: bfi r2, r0, #8, #4
57; CHECK-NEXT: bfi r2, r0, #12, #4
58; CHECK-NEXT: vmsr p0, r2
59; CHECK-NEXT: vpsel q0, q0, q1
60; CHECK-NEXT: bx lr
61entry:
62 %c = icmp ult i32 %s, %t
63 %vc1 = insertelement <4 x i1> undef, i1 %c, i64 0
64 %vc4 = shufflevector <4 x i1> %vc1, <4 x i1> undef, <4 x i32> zeroinitializer
65 %r = select <4 x i1> %vc4, <4 x i32> %a, <4 x i32> %b
66 ret <4 x i32> %r
67}
68
69
70define arm_aapcs_vfpcc <8 x i16> @build_var0_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
71; CHECK-LABEL: build_var0_v8i1:
72; CHECK: @ %bb.0: @ %entry
73; CHECK-NEXT: cmp r0, r1
74; CHECK-NEXT: mov.w r0, #0
75; CHECK-NEXT: it lo
76; CHECK-NEXT: movlo r0, #1
77; CHECK-NEXT: movs r2, #0
78; CHECK-NEXT: rsbs r0, r0, #0
79; CHECK-NEXT: bfi r2, r0, #0, #2
80; CHECK-NEXT: vmsr p0, r2
81; CHECK-NEXT: vpsel q0, q0, q1
82; CHECK-NEXT: bx lr
83entry:
84 %c = icmp ult i32 %s, %t
85 %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 0
86 %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
87 ret <8 x i16> %r
88}
89
90define arm_aapcs_vfpcc <8 x i16> @build_var3_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
91; CHECK-LABEL: build_var3_v8i1:
92; CHECK: @ %bb.0: @ %entry
93; CHECK-NEXT: cmp r0, r1
94; CHECK-NEXT: mov.w r0, #0
95; CHECK-NEXT: it lo
96; CHECK-NEXT: movlo r0, #1
97; CHECK-NEXT: movs r2, #0
98; CHECK-NEXT: rsbs r0, r0, #0
99; CHECK-NEXT: bfi r2, r0, #6, #2
100; CHECK-NEXT: vmsr p0, r2
101; CHECK-NEXT: vpsel q0, q0, q1
102; CHECK-NEXT: bx lr
103entry:
104 %c = icmp ult i32 %s, %t
105 %vc = insertelement <8 x i1> zeroinitializer, i1 %c, i64 3
106 %r = select <8 x i1> %vc, <8 x i16> %a, <8 x i16> %b
107 ret <8 x i16> %r
108}
109
110define arm_aapcs_vfpcc <8 x i16> @build_varN_v8i1(i32 %s, i32 %t, <8 x i16> %a, <8 x i16> %b) {
111; CHECK-LABEL: build_varN_v8i1:
112; CHECK: @ %bb.0: @ %entry
113; CHECK-NEXT: cmp r0, r1
114; CHECK-NEXT: mov.w r0, #0
115; CHECK-NEXT: it lo
116; CHECK-NEXT: movlo r0, #1
117; CHECK-NEXT: movs r2, #0
118; CHECK-NEXT: rsbs r0, r0, #0
119; CHECK-NEXT: bfi r2, r0, #0, #2
120; CHECK-NEXT: bfi r2, r0, #2, #2
121; CHECK-NEXT: bfi r2, r0, #4, #2
122; CHECK-NEXT: bfi r2, r0, #6, #2
123; CHECK-NEXT: bfi r2, r0, #8, #2
124; CHECK-NEXT: bfi r2, r0, #10, #2
125; CHECK-NEXT: bfi r2, r0, #12, #2
126; CHECK-NEXT: bfi r2, r0, #14, #2
127; CHECK-NEXT: vmsr p0, r2
128; CHECK-NEXT: vpsel q0, q0, q1
129; CHECK-NEXT: bx lr
130entry:
131 %c = icmp ult i32 %s, %t
132 %vc1 = insertelement <8 x i1> undef, i1 %c, i64 0
133 %vc4 = shufflevector <8 x i1> %vc1, <8 x i1> undef, <8 x i32> zeroinitializer
134 %r = select <8 x i1> %vc4, <8 x i16> %a, <8 x i16> %b
135 ret <8 x i16> %r
136}
137
138
139define arm_aapcs_vfpcc <16 x i8> @build_var0_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
140; CHECK-LABEL: build_var0_v16i1:
141; CHECK: @ %bb.0: @ %entry
142; CHECK-NEXT: cmp r0, r1
143; CHECK-NEXT: mov.w r0, #0
144; CHECK-NEXT: it lo
145; CHECK-NEXT: movlo r0, #1
146; CHECK-NEXT: movs r2, #0
147; CHECK-NEXT: rsbs r0, r0, #0
148; CHECK-NEXT: bfi r2, r0, #0, #1
149; CHECK-NEXT: vmsr p0, r2
150; CHECK-NEXT: vpsel q0, q0, q1
151; CHECK-NEXT: bx lr
152entry:
153 %c = icmp ult i32 %s, %t
154 %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 0
155 %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
156 ret <16 x i8> %r
157}
158
159define arm_aapcs_vfpcc <16 x i8> @build_var3_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
160; CHECK-LABEL: build_var3_v16i1:
161; CHECK: @ %bb.0: @ %entry
162; CHECK-NEXT: cmp r0, r1
163; CHECK-NEXT: mov.w r0, #0
164; CHECK-NEXT: it lo
165; CHECK-NEXT: movlo r0, #1
166; CHECK-NEXT: movs r2, #0
167; CHECK-NEXT: rsbs r0, r0, #0
168; CHECK-NEXT: bfi r2, r0, #3, #1
169; CHECK-NEXT: vmsr p0, r2
170; CHECK-NEXT: vpsel q0, q0, q1
171; CHECK-NEXT: bx lr
172entry:
173 %c = icmp ult i32 %s, %t
174 %vc = insertelement <16 x i1> zeroinitializer, i1 %c, i64 3
175 %r = select <16 x i1> %vc, <16 x i8> %a, <16 x i8> %b
176 ret <16 x i8> %r
177}
178
179define arm_aapcs_vfpcc <16 x i8> @build_varN_v16i1(i32 %s, i32 %t, <16 x i8> %a, <16 x i8> %b) {
180; CHECK-LABEL: build_varN_v16i1:
181; CHECK: @ %bb.0: @ %entry
182; CHECK-NEXT: cmp r0, r1
183; CHECK-NEXT: mov.w r0, #0
184; CHECK-NEXT: it lo
185; CHECK-NEXT: movlo r0, #1
186; CHECK-NEXT: movs r2, #0
187; CHECK-NEXT: rsbs r0, r0, #0
188; CHECK-NEXT: bfi r2, r0, #0, #1
189; CHECK-NEXT: bfi r2, r0, #1, #1
190; CHECK-NEXT: bfi r2, r0, #2, #1
191; CHECK-NEXT: bfi r2, r0, #3, #1
192; CHECK-NEXT: bfi r2, r0, #4, #1
193; CHECK-NEXT: bfi r2, r0, #5, #1
194; CHECK-NEXT: bfi r2, r0, #6, #1
195; CHECK-NEXT: bfi r2, r0, #7, #1
196; CHECK-NEXT: bfi r2, r0, #8, #1
197; CHECK-NEXT: bfi r2, r0, #9, #1
198; CHECK-NEXT: bfi r2, r0, #10, #1
199; CHECK-NEXT: bfi r2, r0, #11, #1
200; CHECK-NEXT: bfi r2, r0, #12, #1
201; CHECK-NEXT: bfi r2, r0, #13, #1
202; CHECK-NEXT: bfi r2, r0, #14, #1
203; CHECK-NEXT: bfi r2, r0, #15, #1
204; CHECK-NEXT: vmsr p0, r2
205; CHECK-NEXT: vpsel q0, q0, q1
206; CHECK-NEXT: bx lr
207entry:
208 %c = icmp ult i32 %s, %t
209 %vc1 = insertelement <16 x i1> undef, i1 %c, i64 0
210 %vc4 = shufflevector <16 x i1> %vc1, <16 x i1> undef, <16 x i32> zeroinitializer
211 %r = select <16 x i1> %vc4, <16 x i8> %a, <16 x i8> %b
212 ret <16 x i8> %r
213}
214
215
216define arm_aapcs_vfpcc <2 x i64> @build_var0_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
217; CHECK-LABEL: build_var0_v2i1:
218; CHECK: @ %bb.0: @ %entry
219; CHECK-NEXT: movs r2, #0
220; CHECK-NEXT: cmp r0, r1
221; CHECK-NEXT: it lo
222; CHECK-NEXT: movlo r2, #1
223; CHECK-NEXT: rsbs r0, r2, #0
224; CHECK-NEXT: vmov s8, r0
225; CHECK-NEXT: vldr s10, .LCPI9_0
226; CHECK-NEXT: vmov.f32 s9, s8
227; CHECK-NEXT: vmov.f32 s11, s10
228; CHECK-NEXT: vbic q1, q1, q2
229; CHECK-NEXT: vand q0, q0, q2
230; CHECK-NEXT: vorr q0, q0, q1
231; CHECK-NEXT: bx lr
232; CHECK-NEXT: .p2align 2
233; CHECK-NEXT: @ %bb.1:
234; CHECK-NEXT: .LCPI9_0:
235; CHECK-NEXT: .long 0 @ float 0
236entry:
237 %c = icmp ult i32 %s, %t
238 %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 0
239 %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
240 ret <2 x i64> %r
241}
242
243define arm_aapcs_vfpcc <2 x i64> @build_var1_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
244; CHECK-LABEL: build_var1_v2i1:
245; CHECK: @ %bb.0: @ %entry
246; CHECK-NEXT: movs r2, #0
247; CHECK-NEXT: cmp r0, r1
248; CHECK-NEXT: it lo
249; CHECK-NEXT: movlo r2, #1
250; CHECK-NEXT: rsbs r0, r2, #0
251; CHECK-NEXT: vmov s10, r0
252; CHECK-NEXT: vldr s8, .LCPI10_0
253; CHECK-NEXT: vmov.f32 s9, s8
254; CHECK-NEXT: vmov.f32 s11, s10
255; CHECK-NEXT: vbic q1, q1, q2
256; CHECK-NEXT: vand q0, q0, q2
257; CHECK-NEXT: vorr q0, q0, q1
258; CHECK-NEXT: bx lr
259; CHECK-NEXT: .p2align 2
260; CHECK-NEXT: @ %bb.1:
261; CHECK-NEXT: .LCPI10_0:
262; CHECK-NEXT: .long 0 @ float 0
263entry:
264 %c = icmp ult i32 %s, %t
265 %vc = insertelement <2 x i1> zeroinitializer, i1 %c, i64 1
266 %r = select <2 x i1> %vc, <2 x i64> %a, <2 x i64> %b
267 ret <2 x i64> %r
268}
269
270define arm_aapcs_vfpcc <2 x i64> @build_varN_v2i1(i32 %s, i32 %t, <2 x i64> %a, <2 x i64> %b) {
271; CHECK-LABEL: build_varN_v2i1:
272; CHECK: @ %bb.0: @ %entry
273; CHECK-NEXT: movs r2, #0
274; CHECK-NEXT: cmp r0, r1
275; CHECK-NEXT: it lo
276; CHECK-NEXT: movlo r2, #1
277; CHECK-NEXT: rsbs r0, r2, #0
278; CHECK-NEXT: vdup.32 q2, r0
279; CHECK-NEXT: vbic q1, q1, q2
280; CHECK-NEXT: vand q0, q0, q2
281; CHECK-NEXT: vorr q0, q0, q1
282; CHECK-NEXT: bx lr
283entry:
284 %c = icmp ult i32 %s, %t
285 %vc1 = insertelement <2 x i1> undef, i1 %c, i64 0
286 %vc4 = shufflevector <2 x i1> %vc1, <2 x i1> undef, <2 x i32> zeroinitializer
287 %r = select <2 x i1> %vc4, <2 x i64> %a, <2 x i64> %b
288 ret <2 x i64> %r
289}