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gerrit-public.fairphone.software / toolchain / llvm-project / c7f241cba9267897eef6ddc8feca28ce16184a53 / . / llvm / test / CodeGen / ARM / big-endian-neon-extend.ll
blob: 1498356eb971d365b4e95a9f173d8edfdf2f5ca6 [file] [log] [blame]
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]1; RUN: llc < %s -mtriple armeb-eabi -mattr v7,neon -o - | FileCheck %s
2
3define void @vector_ext_2i8_to_2i64( <2 x i8>* %loadaddr, <2 x i64>* %storeaddr ) {
4; CHECK-LABEL: vector_ext_2i8_to_2i64:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]5; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
6; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xff
7; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
8; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
9; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
10; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
11; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
12; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
13; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
14; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame^]15; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]16; CHECK-NEXT: bx lr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]17 %1 = load <2 x i8>* %loadaddr
18 %2 = zext <2 x i8> %1 to <2 x i64>
19 store <2 x i64> %2, <2 x i64>* %storeaddr
20 ret void
21}
22
23define void @vector_ext_2i16_to_2i64( <2 x i16>* %loadaddr, <2 x i64>* %storeaddr ) {
24; CHECK-LABEL: vector_ext_2i16_to_2i64:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]25; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
26; CHECK-NEXT: vmov.i64 [[MASK:q[0-9]+]], #0xffff
27; CHECK-NEXT: vrev64.32 [[MASK]], [[MASK]]
28; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
29; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
30; CHECK-NEXT: vmovl.u32 [[QREG]], [[REG]]
31; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
32; CHECK-NEXT: vand [[QREG]], [[QREG]], [[MASK]]
33; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame^]34; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]35; CHECK-NEXT: bx lr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]36 %1 = load <2 x i16>* %loadaddr
37 %2 = zext <2 x i16> %1 to <2 x i64>
38 store <2 x i64> %2, <2 x i64>* %storeaddr
39 ret void
40}
41
42
43define void @vector_ext_2i8_to_2i32( <2 x i8>* %loadaddr, <2 x i32>* %storeaddr ) {
44; CHECK-LABEL: vector_ext_2i8_to_2i32:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]45; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
46; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
47; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
48; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
49; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
50; CHECK-NEXT: vstr [[REG]], [r1]
51; CHECK-NEXT: bx lr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]52 %1 = load <2 x i8>* %loadaddr
53 %2 = zext <2 x i8> %1 to <2 x i32>
54 store <2 x i32> %2, <2 x i32>* %storeaddr
55 ret void
56}
57
58define void @vector_ext_2i16_to_2i32( <2 x i16>* %loadaddr, <2 x i32>* %storeaddr ) {
59; CHECK-LABEL: vector_ext_2i16_to_2i32:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]60; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
61; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
62; CHECK-NEXT: vmovl.u16 [[QREG:q[0-9]+]], [[REG]]
63; CHECK-NEXT: vrev64.32 [[REG]], [[REG]]
64; CHECK-NEXT: vstr [[REG]], [r1]
65; CHECK-NEXT: bx lr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]66 %1 = load <2 x i16>* %loadaddr
67 %2 = zext <2 x i16> %1 to <2 x i32>
68 store <2 x i32> %2, <2 x i32>* %storeaddr
69 ret void
70}
71
72define void @vector_ext_2i8_to_2i16( <2 x i8>* %loadaddr, <2 x i16>* %storeaddr ) {
73; CHECK-LABEL: vector_ext_2i8_to_2i16:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]74; CHECK: vld1.16 {[[REG:d[0-9]+]][0]}, [r0:16]
75; CHECK-NEXT: vrev16.8 [[REG]], [[REG]]
76; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
77; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
78; CHECK-NEXT: vrev32.16 [[REG]], [[REG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame^]79; CHECK-NEXT: vuzp.16 [[REG]], {{d[0-9]+}}
80; CHECK-NEXT: vrev32.16 [[REG]], {{d[0-9]+}}
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]81; CHECK-NEXT: vst1.32 {[[REG]][0]}, [r1:32]
82; CHECK-NEXT: bx lr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]83 %1 = load <2 x i8>* %loadaddr
84 %2 = zext <2 x i8> %1 to <2 x i16>
85 store <2 x i16> %2, <2 x i16>* %storeaddr
86 ret void
87}
88
89define void @vector_ext_4i8_to_4i32( <4 x i8>* %loadaddr, <4 x i32>* %storeaddr ) {
90; CHECK-LABEL: vector_ext_4i8_to_4i32:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]91; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
92; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
93; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
94; CHECK-NEXT: vmovl.u16 [[QREG]], [[REG]]
95; CHECK-NEXT: vrev64.32 [[QREG]], [[QREG]]
Ahmed Bougachac7f241c2015-02-05 01:52:19 +0000[diff] [blame^]96; CHECK-NEXT: vst1.64 {[[REG]], {{d[0-9]+}}}, [r1]
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]97; CHECK-NEXT: bx lr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]98 %1 = load <4 x i8>* %loadaddr
99 %2 = zext <4 x i8> %1 to <4 x i32>
100 store <4 x i32> %2, <4 x i32>* %storeaddr
101 ret void
102}
103
104define void @vector_ext_4i8_to_4i16( <4 x i8>* %loadaddr, <4 x i16>* %storeaddr ) {
105; CHECK-LABEL: vector_ext_4i8_to_4i16:
Ahmed Bougachadaaf3d92015-02-05 01:45:28 +0000[diff] [blame]106; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}, [r0:32]
107; CHECK-NEXT: vrev32.8 [[REG]], [[REG]]
108; CHECK-NEXT: vmovl.u8 [[QREG:q[0-9]+]], [[REG]]
109; CHECK-NEXT: vrev64.16 [[REG]], [[REG]]
110; CHECK-NEXT: vstr [[REG]], [r1]
111; CHECK-NEXT: bx lr
Christian Pirker6f81e752014-06-23 18:05:53 +0000[diff] [blame]112 %1 = load <4 x i8>* %loadaddr
113 %2 = zext <4 x i8> %1 to <4 x i16>
114 store <4 x i16> %2, <4 x i16>* %storeaddr
115 ret void
116}