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Andrea Di Biagio3a6b0922018-03-08 13:05:02 +00001llvm-mca - LLVM Machine Code Analyzer
2=====================================
3
4SYNOPSIS
5--------
6
7:program:`llvm-mca` [*options*] [input]
8
9DESCRIPTION
10-----------
11
12:program:`llvm-mca` is a performance analysis tool that uses information
13available in LLVM (e.g. scheduling models) to statically measure the performance
14of machine code in a specific CPU.
15
16Performance is measured in terms of throughput as well as processor resource
17consumption. The tool currently works for processors with an out-of-order
18backend, for which there is a scheduling model available in LLVM.
19
20The main goal of this tool is not just to predict the performance of the code
21when run on the target, but also help with diagnosing potential performance
22issues.
23
24Given an assembly code sequence, llvm-mca estimates the IPC (Instructions Per
25Cycle), as well as hardware resource pressure. The analysis and reporting style
26were inspired by the IACA tool from Intel.
27
Andrea Di Biagioc6590122018-04-09 16:39:52 +000028:program:`llvm-mca` allows the usage of special code comments to mark regions of
29the assembly code to be analyzed. A comment starting with substring
30``LLVM-MCA-BEGIN`` marks the beginning of a code region. A comment starting with
31substring ``LLVM-MCA-END`` marks the end of a code region. For example:
32
33.. code-block:: none
34
35 # LLVM-MCA-BEGIN My Code Region
36 ...
37 # LLVM-MCA-END
38
Sanjay Patelc86033a2018-04-10 17:49:45 +000039Inline assembly directives may also be used from source code to annotate the
40assembly text:
41
42.. code-block:: c++
43
44int foo(int a, int b) {
45 __asm volatile("# LLVM-MCA-BEGIN foo");
46 a += 42;
47 __asm volatile("# LLVM-MCA-END");
48 a *= b;
49 return a;
50}
51
52So for example, you can compile code with clang, output assembly, and pipe it
53directly into llvm-mca for analysis:
54
55.. code-block:: bash
56
57$ clang foo.cpp -O2 -target x86_64-unknown-unknown -S -o - | llvm-mca -mcpu=btver2
58
Andrea Di Biagioc6590122018-04-09 16:39:52 +000059Multiple regions can be specified provided that they do not overlap. A code
60region can have an optional description. If no user defined region is specified,
61then :program:`llvm-mca` assumes a default region which contains every
62instruction in the input file. Every region is analyzed in isolation, and the
63final performance report is the union of all the reports generated for every
64code region.
65
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +000066OPTIONS
67-------
68
69If ``input`` is "``-``" or omitted, :program:`llvm-mca` reads from standard
70input. Otherwise, it will read from the specified filename.
71
72If the :option:`-o` option is omitted, then :program:`llvm-mca` will send its output
73to standard output if the input is from standard input. If the :option:`-o`
74option specifies "``-``", then the output will also be sent to standard output.
75
76
77.. option:: -help
78
79 Print a summary of command line options.
80
81.. option:: -mtriple=<target triple>
82
83 Specify a target triple string.
84
85.. option:: -march=<arch>
86
87 Specify the architecture for which to analyze the code. It defaults to the
88 host default target.
89
90.. option:: -mcpu=<cpuname>
91
92 Specify the processor for whic to run the analysis.
93 By default this defaults to a "generic" processor. It is not autodetected to
94 the current architecture.
95
96.. option:: -output-asm-variant=<variant id>
97
98 Specify the output assembly variant for the report generated by the tool.
99 On x86, possible values are [0, 1]. A value of 0 (vic. 1) for this flag enables
100 the AT&T (vic. Intel) assembly format for the code printed out by the tool in
101 the analysis report.
102
103.. option:: -dispatch=<width>
104
105 Specify a different dispatch width for the processor. The dispatch width
Andrea Di Biagioefc3f392018-04-05 16:42:32 +0000106 defaults to field 'IssueWidth' in the processor scheduling model. If width is
107 zero, then the default dispatch width is used.
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000108
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000109.. option:: -register-file-size=<size>
110
Andrea Di Biagioefc3f392018-04-05 16:42:32 +0000111 Specify the size of the register file. When specified, this flag limits how
112 many temporary registers are available for register renaming purposes. A value
113 of zero for this flag means "unlimited number of temporary registers".
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000114
115.. option:: -iterations=<number of iterations>
116
117 Specify the number of iterations to run. If this flag is set to 0, then the
Andrea Di Biagio074cef32018-04-10 12:50:03 +0000118 tool sets the number of iterations to a default value (i.e. 100).
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000119
120.. option:: -noalias=<bool>
121
122 If set, the tool assumes that loads and stores don't alias. This is the
123 default behavior.
124
125.. option:: -lqueue=<load queue size>
126
127 Specify the size of the load queue in the load/store unit emulated by the tool.
128 By default, the tool assumes an unbound number of entries in the load queue.
129 A value of zero for this flag is ignored, and the default load queue size is
130 used instead.
131
132.. option:: -squeue=<store queue size>
133
134 Specify the size of the store queue in the load/store unit emulated by the
135 tool. By default, the tool assumes an unbound number of entries in the store
136 queue. A value of zero for this flag is ignored, and the default store queue
137 size is used instead.
138
139.. option:: -verbose
140
141 Enable verbose output. In particular, this flag enables a number of extra
142 statistics and performance counters for the dispatch logic, the reorder
143 buffer, the retire control unit and the register file.
144
145.. option:: -timeline
146
147 Enable the timeline view.
148
149.. option:: -timeline-max-iterations=<iterations>
150
151 Limit the number of iterations to print in the timeline view. By default, the
152 timeline view prints information for up to 10 iterations.
153
154.. option:: -timeline-max-cycles=<cycles>
155
156 Limit the number of cycles in the timeline view. By default, the number of
157 cycles is set to 80.
158
Andrea Di Biagio1feccc22018-03-26 13:21:48 +0000159.. option:: -resource-pressure
160
161 Enable the resource pressure view. This is enabled by default.
162
Andrea Di Biagio8dabf4f2018-04-03 16:46:23 +0000163.. option:: -register-file-stats
164
165 Enable register file usage statistics.
166
Andrea Di Biagio821f6502018-04-10 14:55:14 +0000167.. option:: -dispatch-stats
168
169 Enable extra dispatch statistics. This view collects and analyzes instruction
170 dispatch events, as well as static/dynamic dispatch stall events. This view
171 is disabled by default.
172
Andrea Di Biagioff9c1092018-03-26 13:44:54 +0000173.. option:: -instruction-info
174
175 Enable the instruction info view. This is enabled by default.
176
Andrea Di Biagiod1569292018-03-26 12:04:53 +0000177.. option:: -instruction-tables
178
179 Prints resource pressure information based on the static information
180 available from the processor model. This differs from the resource pressure
181 view because it doesn't require that the code is simulated. It instead prints
182 the theoretical uniform distribution of resource pressure for every
183 instruction in sequence.
184
Andrea Di Biagio3a6b0922018-03-08 13:05:02 +0000185
186EXIT STATUS
187-----------
188
189:program:`llvm-mca` returns 0 on success. Otherwise, an error message is printed
190to standard error, and the tool returns 1.
191