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gerrit-public.fairphone.software / toolchain / llvm-project / c882eb0723afa9dfe626eebb9699c1871a8bbbab / . / llvm / test / CodeGen / ARM / atomic-64bit.ll
blob: a881d5fd7155d596e968407180ec867e96e19538 [file] [log] [blame]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]1; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
Joey Goulye1de9e92013-08-22 12:19:24 +0000[diff] [blame]2; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf -verify-machineinstrs | FileCheck %s --check-prefix=CHECK-THUMB
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]3
4define i64 @test1(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]5; CHECK-LABEL: test1:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]6; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]7; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
8; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
9; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
10; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]11; CHECK: cmp
12; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]13; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]15; CHECK-THUMB-LABEL: test1:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]16; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]17; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
18; CHECK-THUMB: adds.w [[REG3:[a-z0-9]+]], [[REG1]]
19; CHECK-THUMB: adc.w [[REG4:[a-z0-9]+]], [[REG2]]
20; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
21; CHECK-THUMB: cmp
22; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]23; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]24
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]25 %r = atomicrmw add i64* %ptr, i64 %val seq_cst
26 ret i64 %r
27}
28
29define i64 @test2(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]30; CHECK-LABEL: test2:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]31; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]32; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
33; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
34; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
35; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]36; CHECK: cmp
37; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]38; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]39
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]40; CHECK-THUMB-LABEL: test2:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]41; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]42; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
43; CHECK-THUMB: subs.w [[REG3:[a-z0-9]+]], [[REG1]]
44; CHECK-THUMB: sbc.w [[REG4:[a-z0-9]+]], [[REG2]]
45; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
46; CHECK-THUMB: cmp
47; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]48; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]49
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]50 %r = atomicrmw sub i64* %ptr, i64 %val seq_cst
51 ret i64 %r
52}
53
54define i64 @test3(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]55; CHECK-LABEL: test3:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]56; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]57; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]58; CHECK-DAG: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
59; CHECK-DAG: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]60; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]61; CHECK: cmp
62; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]63; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]64
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]65; CHECK-THUMB-LABEL: test3:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]66; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]67; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]68; CHECK-THUMB-DAG: and.w [[REG3:[a-z0-9]+]], [[REG1]]
69; CHECK-THUMB-DAG: and.w [[REG4:[a-z0-9]+]], [[REG2]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]70; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
71; CHECK-THUMB: cmp
72; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]73; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]74
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]75 %r = atomicrmw and i64* %ptr, i64 %val seq_cst
76 ret i64 %r
77}
78
79define i64 @test4(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]80; CHECK-LABEL: test4:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]81; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]82; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]83; CHECK-DAG: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
84; CHECK-DAG: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]85; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]86; CHECK: cmp
87; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]88; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]89
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]90; CHECK-THUMB-LABEL: test4:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]91; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]92; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]93; CHECK-THUMB-DAG: orr.w [[REG3:[a-z0-9]+]], [[REG1]]
94; CHECK-THUMB-DAG: orr.w [[REG4:[a-z0-9]+]], [[REG2]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]95; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
96; CHECK-THUMB: cmp
97; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]98; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]99
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]100 %r = atomicrmw or i64* %ptr, i64 %val seq_cst
101 ret i64 %r
102}
103
104define i64 @test5(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]105; CHECK-LABEL: test5:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]106; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]107; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]108; CHECK-DAG: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
109; CHECK-DAG: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]110; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]111; CHECK: cmp
112; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]113; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]114
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]115; CHECK-THUMB-LABEL: test5:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]116; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]117; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]118; CHECK-THUMB-DAG: eor.w [[REG3:[a-z0-9]+]], [[REG1]]
119; CHECK-THUMB-DAG: eor.w [[REG4:[a-z0-9]+]], [[REG2]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]120; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
121; CHECK-THUMB: cmp
122; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]123; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]124
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]125 %r = atomicrmw xor i64* %ptr, i64 %val seq_cst
126 ret i64 %r
127}
128
129define i64 @test6(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]130; CHECK-LABEL: test6:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]131; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]132; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
133; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]134; CHECK: cmp
135; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]136; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]137
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]138; CHECK-THUMB-LABEL: test6:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]139; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]140; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
141; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
142; CHECK-THUMB: cmp
143; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]144; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]145
Eli Friedmanc3f9c4a2011-08-31 00:31:29 +0000[diff] [blame]146 %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
147 ret i64 %r
Eli Friedman2c7bb522011-08-31 00:41:05 +0000[diff] [blame]148}
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]149
150define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]151; CHECK-LABEL: test7:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]152; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]153; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]154; CHECK-DAG: eor [[MISMATCH_LO:r[0-9]+]], [[REG1]], r1
155; CHECK-DAG: eor [[MISMATCH_HI:r[0-9]+]], [[REG2]], r2
156; CHECK: orrs {{r[0-9]+}}, [[MISMATCH_LO]], [[MISMATCH_HI]]
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]157; CHECK: bne
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]158; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]159; CHECK: cmp
160; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]161; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]162
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]163; CHECK-THUMB-LABEL: test7:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]164; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]165; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]166; CHECK-THUMB-DAG: eor.w [[MISMATCH_LO:[a-z0-9]+]], [[REG1]], r2
167; CHECK-THUMB-DAG: eor.w [[MISMATCH_HI:[a-z0-9]+]], [[REG2]], r3
168; CHECK-THUMB: orrs [[MISMATCH_HI]], [[MISMATCH_LO]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]169; CHECK-THUMB: bne
170; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
171; CHECK-THUMB: cmp
172; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]173; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]174
Tim Northovere94a5182014-03-11 10:48:52 +0000[diff] [blame]175 %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst seq_cst
Eli Friedman1ccecbb2011-08-31 17:52:22 +0000[diff] [blame]176 ret i64 %r
177}
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]178
Amara Emersonb4ad2f32013-09-26 12:22:36 +0000[diff] [blame]179; Compiles down to a single ldrexd
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]180define i64 @test8(i64* %ptr) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]181; CHECK-LABEL: test8:
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]182; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]183; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]184
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]185; CHECK-THUMB-LABEL: test8:
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]186; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]187; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]188
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]189 %r = load atomic i64* %ptr seq_cst, align 8
190 ret i64 %r
191}
192
193; Compiles down to atomicrmw xchg; there really isn't any more efficient
194; way to write it.
195define void @test9(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]196; CHECK-LABEL: test9:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]197; CHECK: dmb {{ish$}}
Weiming Zhao8f56f882012-11-16 21:55:34 +0000[diff] [blame]198; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
199; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]200; CHECK: cmp
201; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]202; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]203
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]204; CHECK-THUMB-LABEL: test9:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]205; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]206; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
207; CHECK-THUMB: strexd {{[a-z0-9]+}}, {{[a-z0-9]+}}, {{[a-z0-9]+}}
208; CHECK-THUMB: cmp
209; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]210; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]211
Eli Friedman7c3bded2011-08-31 18:26:09 +0000[diff] [blame]212 store atomic i64 %val, i64* %ptr seq_cst, align 8
213 ret void
214}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]215
216define i64 @test10(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]217; CHECK-LABEL: test10:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]218; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]219; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]220; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
221; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
222; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
223; CHECK: cmp [[REG1]], r1
224; CHECK: movwls [[CARRY_LO]], #1
225; CHECK: cmp [[REG2]], r2
226; CHECK: movwle [[CARRY_HI]], #1
227; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
228; CHECK: cmp [[CARRY_HI]], #0
229; CHECK: movne [[OUT_HI]], [[REG2]]
230; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
231; CHECK: movne [[OUT_LO]], [[REG1]]
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]232; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
233; CHECK: cmp
234; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]235; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]236
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]237; CHECK-THUMB-LABEL: test10:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]238; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]239; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]240; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
241; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
242; CHECK-THUMB: cmp [[REG1]], r2
243; CHECK-THUMB: movls.w [[CARRY_LO]], #1
244; CHECK-THUMB: cmp [[REG2]], r3
245; CHECK-THUMB: movle [[CARRY_HI]], #1
246; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
247; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
248; CHECK-THUMB: cmp [[CARRY_HI]], #0
249; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
250; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
251; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]252; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
253; CHECK-THUMB: cmp
254; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]255; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]256
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]257 %r = atomicrmw min i64* %ptr, i64 %val seq_cst
258 ret i64 %r
259}
260
261define i64 @test11(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]262; CHECK-LABEL: test11:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]263; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]264; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]265; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
266; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
267; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
268; CHECK: cmp [[REG1]], r1
269; CHECK: movwls [[CARRY_LO]], #1
270; CHECK: cmp [[REG2]], r2
271; CHECK: movwls [[CARRY_HI]], #1
272; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
273; CHECK: cmp [[CARRY_HI]], #0
274; CHECK: movne [[OUT_HI]], [[REG2]]
275; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
276; CHECK: movne [[OUT_LO]], [[REG1]]
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]277; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
278; CHECK: cmp
279; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]280; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]281
282
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]283; CHECK-THUMB-LABEL: test11:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]284; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]285; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]286; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
287; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
288; CHECK-THUMB: cmp [[REG1]], r2
289; CHECK-THUMB: movls.w [[CARRY_LO]], #1
290; CHECK-THUMB: cmp [[REG2]], r3
291; CHECK-THUMB: movls [[CARRY_HI]], #1
292; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
293; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
294; CHECK-THUMB: cmp [[CARRY_HI]], #0
295; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
296; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
297; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]298; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
299; CHECK-THUMB: cmp
300; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]301; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]302
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]303 %r = atomicrmw umin i64* %ptr, i64 %val seq_cst
304 ret i64 %r
305}
306
307define i64 @test12(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]308; CHECK-LABEL: test12:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]309; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]310; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]311; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
312; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
313; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
314; CHECK: cmp [[REG1]], r1
315; CHECK: movwhi [[CARRY_LO]], #1
316; CHECK: cmp [[REG2]], r2
317; CHECK: movwgt [[CARRY_HI]], #1
318; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
319; CHECK: cmp [[CARRY_HI]], #0
320; CHECK: movne [[OUT_HI]], [[REG2]]
321; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
322; CHECK: movne [[OUT_LO]], [[REG1]]
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]323; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
324; CHECK: cmp
325; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]326; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]327
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]328; CHECK-THUMB-LABEL: test12:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]329; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]330; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]331; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
332; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
333; CHECK-THUMB: cmp [[REG1]], r2
334; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
335; CHECK-THUMB: cmp [[REG2]], r3
336; CHECK-THUMB: movgt [[CARRY_HI]], #1
337; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
338; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
339; CHECK-THUMB: cmp [[CARRY_HI]], #0
340; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
341; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
342; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]343; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
344; CHECK-THUMB: cmp
345; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]346; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]347
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]348 %r = atomicrmw max i64* %ptr, i64 %val seq_cst
349 ret i64 %r
350}
351
352define i64 @test13(i64* %ptr, i64 %val) {
Stephen Linf799e3f2013-07-13 20:38:47 +0000[diff] [blame]353; CHECK-LABEL: test13:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]354; CHECK: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]355; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]356; CHECK: mov [[CARRY_LO:[a-z0-9]+]], #0
357; CHECK: mov [[CARRY_HI:[a-z0-9]+]], #0
358; CHECK: mov [[OUT_HI:[a-z0-9]+]], r2
359; CHECK: cmp [[REG1]], r1
360; CHECK: movwhi [[CARRY_LO]], #1
361; CHECK: cmp [[REG2]], r2
362; CHECK: movwhi [[CARRY_HI]], #1
363; CHECK: moveq [[CARRY_HI]], [[CARRY_LO]]
364; CHECK: cmp [[CARRY_HI]], #0
365; CHECK: movne [[OUT_HI]], [[REG2]]
366; CHECK: mov [[OUT_LO:[a-z0-9]+]], r1
367; CHECK: movne [[OUT_LO]], [[REG1]]
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]368; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
369; CHECK: cmp
370; CHECK: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]371; CHECK: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]372
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]373; CHECK-THUMB-LABEL: test13:
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]374; CHECK-THUMB: dmb {{ish$}}
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]375; CHECK-THUMB: ldrexd [[REG1:[a-z0-9]+]], [[REG2:[a-z0-9]+]]
Tim Northoverc882eb02014-04-03 11:44:58 +0000[diff] [blame^]376; CHECK-THUMB: mov.w [[CARRY_LO:[a-z0-9]+]], #0
377; CHECK-THUMB: movs [[CARRY_HI:[a-z0-9]+]], #0
378; CHECK-THUMB: cmp [[REG1]], r2
379; CHECK-THUMB: movhi.w [[CARRY_LO]], #1
380; CHECK-THUMB: cmp [[REG2]], r3
381; CHECK-THUMB: movhi [[CARRY_HI]], #1
382; CHECK-THUMB: moveq [[CARRY_HI]], [[CARRY_LO]]
383; CHECK-THUMB: mov [[OUT_HI:[a-z0-9]+]], r3
384; CHECK-THUMB: cmp [[CARRY_HI]], #0
385; CHECK-THUMB: mov [[OUT_LO:[a-z0-9]+]], r2
386; CHECK-THUMB: movne [[OUT_HI]], [[REG2]]
387; CHECK-THUMB: movne [[OUT_LO]], [[REG1]]
Tim Northovera0edd3e2013-01-29 09:06:13 +0000[diff] [blame]388; CHECK-THUMB: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
389; CHECK-THUMB: cmp
390; CHECK-THUMB: bne
Tim Northover36b24172013-07-03 09:20:36 +0000[diff] [blame]391; CHECK-THUMB: dmb {{ish$}}
Silviu Baranga93aefa52012-11-29 14:41:25 +0000[diff] [blame]392 %r = atomicrmw umax i64* %ptr, i64 %val seq_cst
393 ret i64 %r
394}
395