Blame - llvm/lib/Target/R600/Processors.td - toolchain/llvm-project

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Tom Stellard	c2516c6	2013-05-03 17:21:14 +0000	[diff] [blame]	1	//===-- Processors.td - R600 Processor definitions ------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Tom Stellard	75aadc2	2012-12-11 21:25:42 +0000	[diff] [blame]	9
				10	class Proc<string Name, ProcessorItineraries itin, list<SubtargetFeature> Features>
				11	: Processor<Name, itin, Features>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	12
				13	//===----------------------------------------------------------------------===//
				14	// R600
				15	//===----------------------------------------------------------------------===//
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	16	def : Proc<"", R600_VLIW5_Itin,
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	17	[FeatureR600, FeatureVertexCache]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	18
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	19	def : Proc<"r600", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	20	[FeatureR600 , FeatureVertexCache, FeatureWavefrontSize64]>;
				21
				22	def : Proc<"r630", R600_VLIW5_Itin,
				23	[FeatureR600, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	24
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	25	def : Proc<"rs880", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	26	[FeatureR600, FeatureWavefrontSize16]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	27
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	28	def : Proc<"rv670", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	29	[FeatureR600, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	30
				31	//===----------------------------------------------------------------------===//
				32	// R700
				33	//===----------------------------------------------------------------------===//
				34
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	35	def : Proc<"rv710", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	36	[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	37
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	38	def : Proc<"rv730", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	39	[FeatureR700, FeatureVertexCache, FeatureWavefrontSize32]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	40
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	41	def : Proc<"rv770", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	42	[FeatureR700, FeatureFP64, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	43
				44	//===----------------------------------------------------------------------===//
				45	// Evergreen
				46	//===----------------------------------------------------------------------===//
				47
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	48	def : Proc<"cedar", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	49	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize32,
				50	FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	51
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	52	def : Proc<"redwood", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	53	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64,
				54	FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	55
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	56	def : Proc<"sumo", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	57	[FeatureEvergreen, FeatureWavefrontSize64, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	58
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	59	def : Proc<"juniper", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	60	[FeatureEvergreen, FeatureVertexCache, FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	61
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	62	def : Proc<"cypress", R600_VLIW5_Itin,
Tom Stellard	8c347b0	2014-01-22 21:55:40 +0000	[diff] [blame]	63	[FeatureEvergreen, FeatureFP64, FeatureVertexCache,
				64	FeatureWavefrontSize64]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	65
				66	//===----------------------------------------------------------------------===//
				67	// Northern Islands
				68	//===----------------------------------------------------------------------===//
				69
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	70	def : Proc<"barts", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	71	[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	72
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	73	def : Proc<"turks", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	74	[FeatureNorthernIslands, FeatureVertexCache, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	75
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	76	def : Proc<"caicos", R600_VLIW5_Itin,
Tom Stellard	348273d	2014-01-23 16:18:02 +0000	[diff] [blame]	77	[FeatureNorthernIslands, FeatureCFALUBug]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	78
Vincent Lejeune	076c0b2	2013-04-30 00:14:17 +0000	[diff] [blame]	79	def : Proc<"cayman", R600_VLIW4_Itin,
Tom Stellard	a6c6e1b	2013-06-07 20:37:48 +0000	[diff] [blame]	80	[FeatureNorthernIslands, FeatureFP64, FeatureCaymanISA]>;
Tom Stellard	3498e4f	2013-06-07 20:28:55 +0000	[diff] [blame]	81
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	82	//===----------------------------------------------------------------------===//
				83	// Southern Islands
				84	//===----------------------------------------------------------------------===//
				85
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	86	def : ProcessorModel<"SI", SIFullSpeedModel,
				87	[FeatureSouthernIslands, FeatureFastFMAF32]
				88	>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	89
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	90	def : ProcessorModel<"tahiti", SIFullSpeedModel,
				91	[FeatureSouthernIslands, FeatureFastFMAF32]
				92	>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	93
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	94	def : ProcessorModel<"pitcairn", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	95
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	96	def : ProcessorModel<"verde", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	97
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	98	def : ProcessorModel<"oland", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	99
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	100	def : ProcessorModel<"hainan", SIQuarterSpeedModel, [FeatureSouthernIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	101
				102	//===----------------------------------------------------------------------===//
				103	// Sea Islands
				104	//===----------------------------------------------------------------------===//
				105
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	106	def : ProcessorModel<"bonaire", SIQuarterSpeedModel, [FeatureSeaIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	107
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	108	def : ProcessorModel<"kabini", SIQuarterSpeedModel, [FeatureSeaIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	109
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	110	def : ProcessorModel<"kaveri", SIQuarterSpeedModel, [FeatureSeaIslands]>;
Tom Stellard	d7e146e	2013-12-11 17:51:51 +0000	[diff] [blame]	111
Matt Arsenault	b035a57	2015-01-29 19:34:25 +0000	[diff] [blame]	112	def : ProcessorModel<"hawaii", SIFullSpeedModel,
				113	[FeatureSeaIslands, FeatureFastFMAF32]
				114	>;
Tom Stellard	10b1502	2014-05-02 15:41:49 +0000	[diff] [blame]	115
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	116	def : ProcessorModel<"mullins", SIQuarterSpeedModel, [FeatureSeaIslands]>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	117
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	118	//===----------------------------------------------------------------------===//
				119	// Volcanic Islands
				120	//===----------------------------------------------------------------------===//
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	121
Matt Arsenault	572d230	2015-01-29 19:34:18 +0000	[diff] [blame]	122	def : ProcessorModel<"tonga", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
Marek Olsak	5df00d6	2014-12-07 12:18:57 +0000	[diff] [blame]	123
Tom Stellard	ae38f30	2015-01-14 01:13:19 +0000	[diff] [blame]	124	def : ProcessorModel<"iceland", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;
				125
				126	def : ProcessorModel<"carrizo", SIQuarterSpeedModel, [FeatureVolcanicIslands]>;