Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / c8930de79e0d16cb2cbb303e22e4efd72d1514e5 / . / llvm / test / Transforms / InstSimplify / shr-nop.ll
blob: b0dc8731a11223b21a478a594b296d358a39f3de [file] [log] [blame]
David Majnemerd2056022014-10-21 19:51:55 +0000[diff] [blame]1; RUN: opt < %s -instsimplify -S | FileCheck %s
2
3; CHECK-LABEL: @foo
4; CHECK: %[[and:.*]] = and i32 %x, 1
5; CHECK-NEXT: %[[add:.*]] = add i32 %[[and]], -1
6; CHECK-NEXT: ret i32 %[[add]]
7define i32 @foo(i32 %x) {
8 %o = and i32 %x, 1
9 %n = add i32 %o, -1
10 %t = ashr i32 %n, 17
11 ret i32 %t
12}
13
14; CHECK-LABEL: @exact_lshr_eq_both_zero
15; CHECK-NEXT: ret i1 true
16define i1 @exact_lshr_eq_both_zero(i8 %a) {
17 %shr = lshr exact i8 0, %a
18 %cmp = icmp eq i8 %shr, 0
19 ret i1 %cmp
20}
21
22; CHECK-LABEL: @exact_ashr_eq_both_zero
23; CHECK-NEXT: ret i1 true
24define i1 @exact_ashr_eq_both_zero(i8 %a) {
25 %shr = ashr exact i8 0, %a
26 %cmp = icmp eq i8 %shr, 0
27 ret i1 %cmp
28}
29
30; CHECK-LABEL: @nonexact_ashr_eq_both_zero
31; CHECK-NEXT: ret i1 true
32define i1 @nonexact_ashr_eq_both_zero(i8 %a) {
33 %shr = ashr i8 0, %a
34 %cmp = icmp eq i8 %shr, 0
35 ret i1 %cmp
36}
37
38; CHECK-LABEL: @exact_lshr_ne_both_zero
39; CHECK-NEXT: ret i1 false
40define i1 @exact_lshr_ne_both_zero(i8 %a) {
41 %shr = lshr exact i8 0, %a
42 %cmp = icmp ne i8 %shr, 0
43 ret i1 %cmp
44}
45
46; CHECK-LABEL: @exact_ashr_ne_both_zero
47; CHECK-NEXT: ret i1 false
48define i1 @exact_ashr_ne_both_zero(i8 %a) {
49 %shr = ashr exact i8 0, %a
50 %cmp = icmp ne i8 %shr, 0
51 ret i1 %cmp
52}
53
54; CHECK-LABEL: @nonexact_lshr_ne_both_zero
55; CHECK-NEXT: ret i1 false
56define i1 @nonexact_lshr_ne_both_zero(i8 %a) {
57 %shr = lshr i8 0, %a
58 %cmp = icmp ne i8 %shr, 0
59 ret i1 %cmp
60}
61
62; CHECK-LABEL: @nonexact_ashr_ne_both_zero
63; CHECK-NEXT: ret i1 false
64define i1 @nonexact_ashr_ne_both_zero(i8 %a) {
65 %shr = ashr i8 0, %a
66 %cmp = icmp ne i8 %shr, 0
67 ret i1 %cmp
68}
69
70; CHECK-LABEL: @exact_lshr_eq_last_zero
71; CHECK-NEXT: ret i1 false
72define i1 @exact_lshr_eq_last_zero(i8 %a) {
73 %shr = lshr exact i8 128, %a
74 %cmp = icmp eq i8 %shr, 0
75 ret i1 %cmp
76}
77
78; CHECK-LABEL: @exact_ashr_eq_last_zero
79; CHECK-NEXT: ret i1 false
80define i1 @exact_ashr_eq_last_zero(i8 %a) {
81 %shr = ashr exact i8 -128, %a
82 %cmp = icmp eq i8 %shr, 0
83 ret i1 %cmp
84}
85
86; CHECK-LABEL: @nonexact_lshr_eq_both_zero
87; CHECK-NEXT: ret i1 true
88define i1 @nonexact_lshr_eq_both_zero(i8 %a) {
89 %shr = lshr i8 0, %a
90 %cmp = icmp eq i8 %shr, 0
91 ret i1 %cmp
92}
93
94; CHECK-LABEL: @exact_lshr_ne_last_zero
95; CHECK-NEXT: ret i1 true
96define i1 @exact_lshr_ne_last_zero(i8 %a) {
97 %shr = lshr exact i8 128, %a
98 %cmp = icmp ne i8 %shr, 0
99 ret i1 %cmp
100}
101
102; CHECK-LABEL: @exact_ashr_ne_last_zero
103; CHECK-NEXT: ret i1 true
104define i1 @exact_ashr_ne_last_zero(i8 %a) {
105 %shr = ashr exact i8 -128, %a
106 %cmp = icmp ne i8 %shr, 0
107 ret i1 %cmp
108}
109
110; CHECK-LABEL: @nonexact_lshr_eq_last_zero
111; CHECK-NEXT: ret i1 false
112define i1 @nonexact_lshr_eq_last_zero(i8 %a) {
113 %shr = lshr i8 128, %a
114 %cmp = icmp eq i8 %shr, 0
115 ret i1 %cmp
116}
117
118; CHECK-LABEL: @nonexact_ashr_eq_last_zero
119; CHECK-NEXT: ret i1 false
120define i1 @nonexact_ashr_eq_last_zero(i8 %a) {
121 %shr = ashr i8 -128, %a
122 %cmp = icmp eq i8 %shr, 0
123 ret i1 %cmp
124}
125
126; CHECK-LABEL: @nonexact_lshr_ne_last_zero
127; CHECK-NEXT: ret i1 true
128define i1 @nonexact_lshr_ne_last_zero(i8 %a) {
129 %shr = lshr i8 128, %a
130 %cmp = icmp ne i8 %shr, 0
131 ret i1 %cmp
132}
133
134; CHECK-LABEL: @nonexact_ashr_ne_last_zero
135; CHECK-NEXT: ret i1 true
136define i1 @nonexact_ashr_ne_last_zero(i8 %a) {
137 %shr = ashr i8 -128, %a
138 %cmp = icmp ne i8 %shr, 0
139 ret i1 %cmp
140}
141
142; CHECK-LABEL: @lshr_eq_first_zero
143; CHECK-NEXT: ret i1 false
144define i1 @lshr_eq_first_zero(i8 %a) {
145 %shr = lshr i8 0, %a
146 %cmp = icmp eq i8 %shr, 2
147 ret i1 %cmp
148}
149
150; CHECK-LABEL: @ashr_eq_first_zero
151; CHECK-NEXT: ret i1 false
152define i1 @ashr_eq_first_zero(i8 %a) {
153 %shr = ashr i8 0, %a
154 %cmp = icmp eq i8 %shr, 2
155 ret i1 %cmp
156}
157
158; CHECK-LABEL: @lshr_ne_first_zero
159; CHECK-NEXT: ret i1 true
160define i1 @lshr_ne_first_zero(i8 %a) {
161 %shr = lshr i8 0, %a
162 %cmp = icmp ne i8 %shr, 2
163 ret i1 %cmp
164}
165
166; CHECK-LABEL: @ashr_ne_first_zero
167; CHECK-NEXT: ret i1 true
168define i1 @ashr_ne_first_zero(i8 %a) {
169 %shr = ashr i8 0, %a
170 %cmp = icmp ne i8 %shr, 2
171 ret i1 %cmp
172}
173
174; CHECK-LABEL: @ashr_eq_both_minus1
175; CHECK-NEXT: ret i1 true
176define i1 @ashr_eq_both_minus1(i8 %a) {
177 %shr = ashr i8 -1, %a
178 %cmp = icmp eq i8 %shr, -1
179 ret i1 %cmp
180}
181
182; CHECK-LABEL: @ashr_ne_both_minus1
183; CHECK-NEXT: ret i1 false
184define i1 @ashr_ne_both_minus1(i8 %a) {
185 %shr = ashr i8 -1, %a
186 %cmp = icmp ne i8 %shr, -1
187 ret i1 %cmp
188}
189
190; CHECK-LABEL: @exact_ashr_eq_both_minus1
191; CHECK-NEXT: ret i1 true
192define i1 @exact_ashr_eq_both_minus1(i8 %a) {
193 %shr = ashr exact i8 -1, %a
194 %cmp = icmp eq i8 %shr, -1
195 ret i1 %cmp
196}
197
198; CHECK-LABEL: @exact_ashr_ne_both_minus1
199; CHECK-NEXT: ret i1 false
200define i1 @exact_ashr_ne_both_minus1(i8 %a) {
201 %shr = ashr exact i8 -1, %a
202 %cmp = icmp ne i8 %shr, -1
203 ret i1 %cmp
204}
205
206; CHECK-LABEL: @exact_ashr_eq_opposite_msb
207; CHECK-NEXT: ret i1 false
208define i1 @exact_ashr_eq_opposite_msb(i8 %a) {
209 %shr = ashr exact i8 -128, %a
210 %cmp = icmp eq i8 %shr, 1
211 ret i1 %cmp
212}
213
214; CHECK-LABEL: @exact_ashr_eq_noexactlog
215; CHECK-NEXT: ret i1 false
216define i1 @exact_ashr_eq_noexactlog(i8 %a) {
217 %shr = ashr exact i8 -90, %a
218 %cmp = icmp eq i8 %shr, -30
219 ret i1 %cmp
220}
221
222; CHECK-LABEL: @exact_ashr_ne_opposite_msb
223; CHECK-NEXT: ret i1 true
224define i1 @exact_ashr_ne_opposite_msb(i8 %a) {
225 %shr = ashr exact i8 -128, %a
226 %cmp = icmp ne i8 %shr, 1
227 ret i1 %cmp
228}
229
230; CHECK-LABEL: @ashr_eq_opposite_msb
231; CHECK-NEXT: ret i1 false
232define i1 @ashr_eq_opposite_msb(i8 %a) {
233 %shr = ashr i8 -128, %a
234 %cmp = icmp eq i8 %shr, 1
235 ret i1 %cmp
236}
237
238; CHECK-LABEL: @ashr_ne_opposite_msb
239; CHECK-NEXT: ret i1 true
240define i1 @ashr_ne_opposite_msb(i8 %a) {
241 %shr = ashr i8 -128, %a
242 %cmp = icmp ne i8 %shr, 1
243 ret i1 %cmp
244}
245
246; CHECK-LABEL: @exact_ashr_eq_shift_gt
247; CHECK-NEXT : ret i1 false
248define i1 @exact_ashr_eq_shift_gt(i8 %a) {
249 %shr = ashr exact i8 -2, %a
250 %cmp = icmp eq i8 %shr, -8
251 ret i1 %cmp
252}
253
254; CHECK-LABEL: @exact_ashr_ne_shift_gt
255; CHECK-NEXT : ret i1 true
256define i1 @exact_ashr_ne_shift_gt(i8 %a) {
257 %shr = ashr exact i8 -2, %a
258 %cmp = icmp ne i8 %shr, -8
259 ret i1 %cmp
260}
261
262; CHECK-LABEL: @nonexact_ashr_eq_shift_gt
263; CHECK-NEXT : ret i1 false
264define i1 @nonexact_ashr_eq_shift_gt(i8 %a) {
265 %shr = ashr i8 -2, %a
266 %cmp = icmp eq i8 %shr, -8
267 ret i1 %cmp
268}
269
270; CHECK-LABEL: @nonexact_ashr_ne_shift_gt
271; CHECK-NEXT : ret i1 true
272define i1 @nonexact_ashr_ne_shift_gt(i8 %a) {
273 %shr = ashr i8 -2, %a
274 %cmp = icmp ne i8 %shr, -8
275 ret i1 %cmp
276}
277
278; CHECK-LABEL: @exact_lshr_eq_shift_gt
279; CHECK-NEXT: ret i1 false
280define i1 @exact_lshr_eq_shift_gt(i8 %a) {
281 %shr = lshr exact i8 2, %a
282 %cmp = icmp eq i8 %shr, 8
283 ret i1 %cmp
284}
285
286; CHECK-LABEL: @exact_lshr_ne_shift_gt
287; CHECK-NEXT: ret i1 true
288define i1 @exact_lshr_ne_shift_gt(i8 %a) {
289 %shr = lshr exact i8 2, %a
290 %cmp = icmp ne i8 %shr, 8
291 ret i1 %cmp
292}
293
294; CHECK-LABEL: @nonexact_lshr_eq_shift_gt
295; CHECK-NEXT : ret i1 false
296define i1 @nonexact_lshr_eq_shift_gt(i8 %a) {
297 %shr = lshr i8 2, %a
298 %cmp = icmp eq i8 %shr, 8
299 ret i1 %cmp
300}
301
302; CHECK-LABEL: @nonexact_lshr_ne_shift_gt
303; CHECK-NEXT : ret i1 true
304define i1 @nonexact_lshr_ne_shift_gt(i8 %a) {
305 %shr = ashr i8 2, %a
306 %cmp = icmp ne i8 %shr, 8
307 ret i1 %cmp
308}
309
310; CHECK-LABEL: @exact_ashr_ne_noexactlog
311; CHECK-NEXT: ret i1 true
312define i1 @exact_ashr_ne_noexactlog(i8 %a) {
313 %shr = ashr exact i8 -90, %a
314 %cmp = icmp ne i8 %shr, -30
315 ret i1 %cmp
316}
317
318; CHECK-LABEL: @exact_lshr_eq_noexactlog
319; CHECK-NEXT: ret i1 false
320define i1 @exact_lshr_eq_noexactlog(i8 %a) {
321 %shr = lshr exact i8 90, %a
322 %cmp = icmp eq i8 %shr, 30
323 ret i1 %cmp
324}
325
326; CHECK-LABEL: @exact_lshr_ne_noexactlog
327; CHECK-NEXT: ret i1 true
328define i1 @exact_lshr_ne_noexactlog(i8 %a) {
329 %shr = lshr exact i8 90, %a
330 %cmp = icmp ne i8 %shr, 30
331 ret i1 %cmp
332}
David Majnemerbf7550e2014-11-05 00:59:59 +0000[diff] [blame]333
334; CHECK-LABEL: @exact_lshr_lowbit
335; CHECK-NEXT: ret i32 7
336define i32 @exact_lshr_lowbit(i32 %shiftval) {
337 %shr = lshr exact i32 7, %shiftval
338 ret i32 %shr
339}
340
341; CHECK-LABEL: @exact_ashr_lowbit
342; CHECK-NEXT: ret i32 7
343define i32 @exact_ashr_lowbit(i32 %shiftval) {
344 %shr = ashr exact i32 7, %shiftval
345 ret i32 %shr
346}